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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: PCI bridge</font></b>
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<p><table  align=center border=1 cellPadding=2 cellSpacing=0 width="100%" valign="top">
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<tbody><tr bgcolor=#bbccff>    <td align=center valign=center>
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<a href="http://www.opencores.org/cores/pci/index.shtml">Introduction</a>               |
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<a href="http://www.opencores.org/cores/pci/documentation.shtml">Documentation</a>               |
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<a href="http://www.opencores.org/cores/pci/charact.shtml">Characteristics</a>               |
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<a href="http://www.opencores.org/cores/pci/current_stat.shtml">Current Status</a>               |
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<a href="http://www.opencores.org/cores/pci/todo_list.shtml">To Do list</a>               |
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<a href="http://www.opencores.org/cores/pci/test_app.shtml">Test Application</a>               |
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<a href="http://www.opencores.org/cores/pci/download.shtml">Download</a>               |
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<a href="http://www.opencores.org/cores/pci/testbench.shtml">Testbench</a>               |
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<a href="http://www.opencores.org/cores/pci/references.shtml">References</a>               |
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<a href="http://www.opencores.org/cores/pci/links.shtml">Links</a>               |
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<a href="mailto:pci@opencores.org">Mailing list</a>               |
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<a href="http://www.opencores.org/cores/pci/contacts.shtml">Contacts</a>
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</td></tr></tbody>
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</table>
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<table border=0 cellPadding=0 cellSpacing=0 width="100%">
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<tbody><tr><td>
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<p><center><font color="#bf0000" size=+3><b>To Do list</b></font></center>
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</p></td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>PCI Behavioral Models and PCI bus Monitor<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>We start using the PCI BFMs written by Blue Beaver. This BFMs support only MEMORY READ/WRITE
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and CONFIG READ/WRITE commands.
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<br><br>
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</font>
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</td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>Synchronous clock operation<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>There should be added one more DEFINE for synchronous clock operation between PCI and WISHBONE
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buses. This is usefull in FPGAs to use less slices when an application does not require different
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bus clock domains.
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<br><br>
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</font>
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</td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>Design document<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>After finishing the testbench, we will write the design document describing the PCI core structure
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and all defines that can be (an why) changed by an user.
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<br><br>
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</font>
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</td></tr>
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