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URL https://opencores.org/ocsvn/pci32tlite_oc/pci32tlite_oc/trunk

Subversion Repositories pci32tlite_oc

[/] [pci32tlite_oc/] [trunk/] [pci32tlite_oc.ipfpga] - Blame information for rev 10

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1 10 peio
# Project: pci32tlite_oc
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# Description: Compilation resource file.
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[PROJECT]
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pci32tlite_oc
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[END]
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[IP_LIST]
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[END]
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[IP_SIM_LIST]
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[END]
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[PROJECT_LIBRARY]
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onalib
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[END]
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[PROJECT_SOURCES]
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rtl/onalib.vhd onalib
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rtl/pcidec.vhd
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rtl/pciwbsequ.vhd
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rtl/pciregs.vhd
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rtl/pcidmux.vhd
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rtl/pcipargen.vhd
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rtl/pci32tlite.vhd
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[END]
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[TB_SOURCES]
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[END]
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[MODELSIM]
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vhdl_options -2008 -explicit
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[END]
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[MSIM]
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[END]
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[GHDL]
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# --std=08 --std=93c
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ghdl_options --ieee=standard --std=08 --warn-no-attribute --warn-no-shared --warn-no-hide -fexplicit -fsynopsys \
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-frelaxed -frelaxed-rules --no-vital-checks --warn-binding --mb-comments --warn-no-pure
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[END]
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[DIR_STRUCT]
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# Set directories relative to project directory
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sim_dir sim/
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[END]

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