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peio |
--+-------------------------------------------------------------------------------------------------+
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--| |
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--| File: pciregs.vhd |
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--| |
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--| Project: pci32tLite |
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--| |
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--| Description: PCI Registers |
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--| |
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--| +-----------------------------------------------------------------------+ |
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--| | PCI CONFIGURATION SPACE REGISTERS | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--| +-------------------------------------------------------------------+ |
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--| | REGISTER | adr(7..2) | offset | Byte Enable | Size | |
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--| +-------------------------------------------------------------------+ |
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--| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | |
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--| +-------------------------------------------------------------------+ |
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--| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | |
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--| +-------------------------------------------------------------------+ |
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--| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | |
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--| +-------------------------------------------------------------------+ |
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--| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | |
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--| +-------------------------------------------------------------------+ |
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--| | REVISIONID | 000010 (r) | 08 | 0 | 1 | |
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--| +-------------------------------------------------------------------+ |
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--| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | |
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--| +-------------------------------------------------------------------+ |
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--| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | |
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--| +-------------------------------------------------------------------+ |
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--| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | |
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--| +-------------------------------------------------------------------+ |
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--| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | |
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--| +-------------------------------------------------------------------+ |
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--| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | |
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--| +-------------------------------------------------------------------+ |
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--| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | |
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--| +-------------------------------------------------------------------+ |
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--| | INTPIN | 001111 (r) | 3D | 1 | 1 | |
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--| +-------------------------------------------------------------------+ |
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--| (w*) Reseteable |
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--| |
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--| +-----------------------------------------------+ |
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--| | VENDORID (r) Vendor ID register | |
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--| +-----------------------------------------------+-----------------------+ |
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--| | Identifies manufacturer of device. | |
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--| | VENDORIDr : vendorID (generic) | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--| +-----------------------------------------------+ |
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--| | DEVICEID (r) Device ID register | |
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--| +-----------------------------------------------+-----------------------+ |
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--| | Identifies the device. | |
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--| | DEVICEIDr : deviceID (generic) | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--| +-----------------------------------------------+ |
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--| | CMD (r/w) CoMmanD register | |
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--| +-----------------------------------------------+------------------------------+ |
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--| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb | (15-8) |
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--| +------------------------------------------------------------------------------+ |
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--| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb|IOSPACEENb| (7-0) |
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--| +------------------------------------------------------------------------------+ |
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--| | SERRENb : System ERRor ENable (1 = Enabled) | |
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--| | PERRENb : Parity ERRor ENable (1 = Enabled) | |
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--| | MEMSPACEENb : MEMory SPACE ENable (1 = Enabled) | |
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--| | IOSPACEENb : IO SPACE ENable (1 = Enabled) | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--| +-----------------------------------------------+ |
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--| | ST (r/w*) STatus register | |
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--| +-----------------------------------------------+-------------------------+ |
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--| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) |
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--| +-------------------------------------------------------------------------+ |
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--| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) |
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--| +-------------------------------------------------------------------------+ |
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--| | PERRDTb : Parity ERRor DeTected | |
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--| | SERRSIb : System ERRor SIgnaled | |
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--| | TABORTSIb : Target ABORT SIgnaled | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--| +-----------------------------------------------+ |
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--| | REVISIONID (r) Revision ID register | |
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--| +-----------------------------------------------+-----------------------+ |
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--| | Identifies a device revision. | |
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--| +-----------------------------------------------------------------------+ |
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--| +-----------------------------------------------+ |
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--| | CLASSCODE (r) CLASS CODE register | |
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--| +-----------------------------------------------+-----------------------+ |
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--| | Identifies the generic funtion of the device. | |
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--| +-----------------------------------------------------------------------+ |
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--| +-----------------------------------------------+ |
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--| | HEADERTYPE (r) Header Type register | |
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--| +-----------------------------------------------+-----------------------+ |
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--| | Identifies the layout of the second part of the predefined header. | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--| +-----------------------------------------------+ |
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--| | BAR0 (r/w) Base AddRess 0 register | |
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--| +-----------------------------------------------+-----------------------+ |
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--| | BAR032MBb(6..0) | -- | (31-24) |
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--| +-----------------------------------------------------------------------+ |
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--| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--| +-----------------------------------------------+ |
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--| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | |
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--| +-----------------------------------------------+-----------------------+ |
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--| | Identifies vendor of add-in board or subsystem. | |
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--| | SUBSYSTEMVIDr : subsystemvID (generic) | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--| +-----------------------------------------------+ |
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--| | SUBSYSTEMID (r) SUBSYSTEM ID register | |
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--| +-----------------------------------------------+-----------------------+ |
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--| | Vendor specific. | |
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--| | SUBSYTEMIDr : subsytemID (generic) | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--| +-----------------------------------------------+ |
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--| | INTLINE (r/w) INTerrupt LINE register | |
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--| +-----------------------------------------------+-----------------------+ |
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--| | INTLINEr(7..0) | (7..0) |
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--| +-----------------------------------------------------------------------+ |
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--| | Interrupt Line routing information | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--| +-----------------------------------------------+ |
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--| | INTPIN (r) INTerrupt PIN register | |
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--| +-----------------------------------------------+-----------------------+ |
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--| | Tells which interrupt pin the device uses: 01=INTA | |
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--| +-----------------------------------------------------------------------+ |
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--| |
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--+-------------------------------------------------------------------------------------------------+
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--+-----------------------------------------------------------------+
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--| |
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--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
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--| |
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--| This source file may be used and distributed without |
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--| restriction provided that this copyright statement is not |
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--| removed from the file and that any derivative work contains |
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--| the original copyright notice and the associated disclaimer. |
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--| |
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--| This source file is free software; you can redistribute it |
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--| and/or modify it under the terms of the GNU Lesser General |
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--| Public License as published by the Free Software Foundation; |
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--| either version 2.1 of the License, or (at your option) any |
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--| later version. |
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--| |
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--| This source is distributed in the hope that it will be |
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--| useful, but WITHOUT ANY WARRANTY; without even the implied |
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--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
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--| PURPOSE. See the GNU Lesser General Public License for more |
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--| details. |
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--| |
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--| You should have received a copy of the GNU Lesser General |
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--| Public License along with this source; if not, download it |
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--| from http://www.opencores.org/lgpl.shtml |
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--| |
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--+-----------------------------------------------------------------+
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--+-----------------------------------------------------------------------------+
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--| LIBRARIES |
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--+-----------------------------------------------------------------------------+
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library ieee;
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use ieee.std_logic_1164.all;
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library onalib;
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use onalib.onapackage.all;
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--+-----------------------------------------------------------------------------+
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--| ENTITY |
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--+-----------------------------------------------------------------------------+
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entity pciregs is
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generic (
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vendorID : std_logic_vector(15 downto 0);
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deviceID : std_logic_vector(15 downto 0);
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revisionID : std_logic_vector(7 downto 0);
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subsystemID : std_logic_vector(15 downto 0);
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subsystemvID : std_logic_vector(15 downto 0);
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classcodeID : std_logic_vector(23 downto 0);
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BARS : string := "1BARMEM"
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);
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port (
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-- General
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clk_i : in std_logic;
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rst_i : in std_logic;
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--
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adr_i : in std_logic_vector(5 downto 0);
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cbe_i : in std_logic_vector(3 downto 0);
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dat_i : in std_logic_vector(31 downto 0);
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dat_o : out std_logic_vector(31 downto 0);
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--
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wrcfg_i : in std_logic;
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rdcfg_i : in std_logic;
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perr_i : in std_logic;
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serr_i : in std_logic;
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tabort_i : in std_logic;
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--
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bar0_o : out std_logic_vector(31 downto 9);
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perrEN_o : out std_logic;
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serrEN_o : out std_logic;
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memEN_o : out std_logic;
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ioEN_o : out std_logic
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);
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end pciregs;
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architecture rtl of pciregs is
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--+-----------------------------------------------------------------------------+
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--| COMPONENTS |
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--+-----------------------------------------------------------------------------+
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--+-----------------------------------------------------------------------------+
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--| CONSTANTS |
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--+-----------------------------------------------------------------------------+
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--constant CLASSCODEr : std_logic_vector(23 downto 0) := X"068000"; -- Bridge-OtherBridgeDevice
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constant CLASSCODEr : std_logic_vector(23 downto 0) := classcodeID;
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constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81...
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constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00";
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constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed
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constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID;
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constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID;
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constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID;
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constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID;
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constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA#
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--+-----------------------------------------------------------------------------+
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--| SIGNALS |
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--+-----------------------------------------------------------------------------+
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signal dataout : std_logic_vector(31 downto 0);
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signal tabortPFS : std_logic;
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signal serrPFS : std_logic;
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signal perrPFS : std_logic;
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signal adrSTCMD : std_logic;
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signal adrBAR0 : std_logic;
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signal adrINT : std_logic;
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signal we0CMD : std_logic;
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signal we1CMD : std_logic;
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signal we3ST : std_logic;
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signal we3BAR0 : std_logic;
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signal we0INT : std_logic;
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signal we1INT : std_logic;
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signal st11SEN : std_logic;
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signal st11REN : std_logic;
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signal st14SEN : std_logic;
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signal st14REN : std_logic;
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signal st15SEN : std_logic;
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signal st15REN : std_logic;
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--+---------------------------------------------------------+
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--| CONFIGURATION SPACE REGISTERS |
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| 265 |
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--+---------------------------------------------------------+
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| 267 |
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-- INTERRUPT LINE register
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signal INTLINEr : std_logic_vector(7 downto 0);
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-- COMMAND register bits
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signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit)
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signal IOSPACEENb : std_logic; -- IO SPACE ENable (bit)
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signal PERRENb : std_logic; -- Parity ERRor ENable (bit)
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signal SERRENb : std_logic; -- SERR ENable (bit)
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-- STATUS register bits
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--signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits)
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signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit)
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signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit)
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signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit)
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-- BAR0 register bits
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signal BAR0b : std_logic_vector(31 downto 0);
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begin
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--+-----------------------------------------+
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--| BAR0 32MBytes Memory Space |
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--+-----------------------------------------+
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barmem_g: if (BARS="1BARMEM") generate
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BAR0b(24 downto 0) <= (others => '0');
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end generate;
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| 292 |
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--+-----------------------------------------+
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--| BAR0 512Bytes Io Space |
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--+-----------------------------------------+
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bario_g: if (BARS="1BARIO") generate
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BAR0b(31 downto 16) <= (others => '0');
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BAR0b(8 downto 1) <= (others => '0');
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BAR0b(0) <= '1';
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end generate;
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--+-------------------------------------------------------------------------+
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--| Component instances |
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--+-------------------------------------------------------------------------+
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u1: pfs port map ( clk => clk_i, rst => rst_i, a => tabort_i, y => tabortPFS );
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u2: pfs port map ( clk => clk_i, rst => rst_i, a => serr_i, y => serrPFS );
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u3: pfs port map ( clk => clk_i, rst => rst_i, a => perr_i, y => perrPFS );
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| 308 |
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| 309 |
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| 310 |
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--+-------------------------------------------------------------------------+
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| 311 |
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--| Registers Address Decoder |
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--+-------------------------------------------------------------------------+
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|
|
adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0';
|
| 315 |
|
|
adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0';
|
| 316 |
|
|
adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0';
|
| 317 |
|
|
|
| 318 |
|
|
|
| 319 |
|
|
--+-------------------------------------------------------------------------+
|
| 320 |
|
|
--| WRITE ENABLE REGISTERS |
|
| 321 |
|
|
--+-------------------------------------------------------------------------+
|
| 322 |
|
|
|
| 323 |
|
|
--+-----------------------------------------+
|
| 324 |
|
|
--| Write Enable Registers |
|
| 325 |
|
|
--+-----------------------------------------+
|
| 326 |
|
|
|
| 327 |
|
|
we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0));
|
| 328 |
|
|
we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1));
|
| 329 |
|
|
--we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2));
|
| 330 |
|
|
we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3));
|
| 331 |
|
|
--we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2));
|
| 332 |
|
|
we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3));
|
| 333 |
|
|
we0INT <= adrINT and wrcfg_i and (not cbe_i(0));
|
| 334 |
|
|
--we1INT <= adrINT and wrcfg_i and (not cbe_i(1));
|
| 335 |
|
|
|
| 336 |
|
|
--+-----------------------------------------+
|
| 337 |
|
|
--| Set Enable & Reset Enable bits |
|
| 338 |
|
|
--+-----------------------------------------+
|
| 339 |
|
|
st11SEN <= tabortPFS;
|
| 340 |
|
|
st11REN <= we3ST and dat_i(27);
|
| 341 |
|
|
st14SEN <= serrPFS;
|
| 342 |
|
|
st14REN <= we3ST and dat_i(30);
|
| 343 |
|
|
st15SEN <= perrPFS;
|
| 344 |
|
|
st15REN <= we3ST and dat_i(31);
|
| 345 |
|
|
|
| 346 |
|
|
|
| 347 |
|
|
--+-------------------------------------------------------------------------+
|
| 348 |
|
|
--| WRITE REGISTERS |
|
| 349 |
|
|
--+-------------------------------------------------------------------------+
|
| 350 |
|
|
|
| 351 |
|
|
--+---------------------------------------------------------+
|
| 352 |
|
|
--| COMMAND REGISTER Write |
|
| 353 |
|
|
--+---------------------------------------------------------+
|
| 354 |
|
|
|
| 355 |
|
|
REGCMDWR: process( clk_i, rst_i, we0CMD, we1CMD, dat_i )
|
| 356 |
|
|
begin
|
| 357 |
|
|
if( rst_i = '1' ) then
|
| 358 |
|
|
IOSPACEENb <= '0';
|
| 359 |
|
|
MEMSPACEENb <= '0';
|
| 360 |
|
|
PERRENb <= '0';
|
| 361 |
|
|
SERRENb <= '0';
|
| 362 |
|
|
elsif( rising_edge( clk_i ) ) then
|
| 363 |
|
|
|
| 364 |
|
|
-- Byte 0
|
| 365 |
|
|
if( we0CMD = '1' ) then
|
| 366 |
|
|
IOSPACEENb <= dat_i(0);
|
| 367 |
|
|
MEMSPACEENb <= dat_i(1);
|
| 368 |
|
|
PERRENb <= dat_i(6);
|
| 369 |
|
|
end if;
|
| 370 |
|
|
|
| 371 |
|
|
-- Byte 1
|
| 372 |
|
|
if( we1CMD = '1' ) then
|
| 373 |
|
|
SERRENb <= dat_i(8);
|
| 374 |
|
|
end if;
|
| 375 |
|
|
|
| 376 |
|
|
end if;
|
| 377 |
|
|
|
| 378 |
|
|
end process REGCMDWR;
|
| 379 |
|
|
|
| 380 |
|
|
|
| 381 |
|
|
--+---------------------------------------------------------+
|
| 382 |
|
|
--| STATUS REGISTER WRITE (Reset only) |
|
| 383 |
|
|
--+---------------------------------------------------------+
|
| 384 |
|
|
|
| 385 |
|
|
REGSTWR: process( clk_i, rst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN )
|
| 386 |
|
|
begin
|
| 387 |
|
|
|
| 388 |
|
|
if( rst_i = '1' ) then
|
| 389 |
|
|
TABORTSIb <= '0';
|
| 390 |
|
|
SERRSIb <= '0';
|
| 391 |
|
|
PERRDTb <= '0';
|
| 392 |
|
|
elsif( rising_edge( clk_i ) ) then
|
| 393 |
|
|
|
| 394 |
|
|
-- TarGet ABORT SIgnaling bit
|
| 395 |
|
|
if( st11SEN = '1' ) then
|
| 396 |
|
|
TABORTSIb <= '1';
|
| 397 |
|
|
elsif ( st11REN = '1' ) then
|
| 398 |
|
|
TABORTSIb <= '0';
|
| 399 |
|
|
end if;
|
| 400 |
|
|
|
| 401 |
|
|
-- System ERRor SIgnaling bit
|
| 402 |
|
|
if( st14SEN = '1' ) then
|
| 403 |
|
|
SERRSIb <= '1';
|
| 404 |
|
|
elsif ( st14REN = '1' ) then
|
| 405 |
|
|
SERRSIb <= '0';
|
| 406 |
|
|
end if;
|
| 407 |
|
|
|
| 408 |
|
|
-- Parity ERRor DEtected bit
|
| 409 |
|
|
if( st15SEN = '1' ) then
|
| 410 |
|
|
PERRDTb <= '1';
|
| 411 |
|
|
elsif ( st15REN = '1' ) then
|
| 412 |
|
|
PERRDTb <= '0';
|
| 413 |
|
|
end if;
|
| 414 |
|
|
|
| 415 |
|
|
end if;
|
| 416 |
|
|
|
| 417 |
|
|
end process REGSTWR;
|
| 418 |
|
|
|
| 419 |
|
|
|
| 420 |
|
|
--+---------------------------------------------------------+
|
| 421 |
|
|
--| INTERRUPT REGISTER Write |
|
| 422 |
|
|
--+---------------------------------------------------------+
|
| 423 |
|
|
|
| 424 |
|
|
REGINTWR: process( clk_i, rst_i, we0INT, dat_i )
|
| 425 |
|
|
begin
|
| 426 |
|
|
|
| 427 |
|
|
if( rst_i = '1' ) then
|
| 428 |
|
|
INTLINEr <= ( others => '0' );
|
| 429 |
|
|
elsif( rising_edge( clk_i ) ) then
|
| 430 |
|
|
-- Byte 0
|
| 431 |
|
|
if( we0INT = '1' ) then
|
| 432 |
|
|
INTLINEr <= dat_i(7 downto 0);
|
| 433 |
|
|
end if;
|
| 434 |
|
|
end if;
|
| 435 |
|
|
end process REGINTWR;
|
| 436 |
|
|
|
| 437 |
|
|
|
| 438 |
|
|
--+---------------------------------------------------------+
|
| 439 |
|
|
--| BAR0 32MBytes MEM address space (bits 31-25) |
|
| 440 |
|
|
--+---------------------------------------------------------+
|
| 441 |
|
|
rbarmem_g: if (BARS="1BARMEM") generate
|
| 442 |
|
|
RBAR0MEMWR: process( clk_i, rst_i, we3BAR0, dat_i )
|
| 443 |
|
|
begin
|
| 444 |
|
|
if( rst_i = '1' ) then
|
| 445 |
|
|
BAR0b(31 downto 25) <= ( others => '0' );
|
| 446 |
|
|
elsif( rising_edge( clk_i ) ) then
|
| 447 |
|
|
-- Byte 3
|
| 448 |
|
|
if( we3BAR0 = '1' ) then
|
| 449 |
|
|
BAR0b(31 downto 25) <= dat_i(31 downto 25);
|
| 450 |
|
|
end if;
|
| 451 |
|
|
end if;
|
| 452 |
|
|
end process RBAR0MEMWR;
|
| 453 |
|
|
end generate;
|
| 454 |
|
|
|
| 455 |
|
|
--+---------------------------------------------------------+
|
| 456 |
|
|
--| BAR0 512Bytes IO address space (bits 15-9) |
|
| 457 |
|
|
--+---------------------------------------------------------+
|
| 458 |
|
|
rbario_g: if (BARS="1BARIO") generate
|
| 459 |
|
|
RBAR0IOWR: process( clk_i, rst_i, we3BAR0, dat_i )
|
| 460 |
|
|
begin
|
| 461 |
|
|
if( rst_i = '1' ) then
|
| 462 |
|
|
BAR0b(15 downto 9) <= ( others => '0' );
|
| 463 |
|
|
elsif( rising_edge( clk_i ) ) then
|
| 464 |
|
|
-- Byte 3
|
| 465 |
|
|
if( we3BAR0 = '1' ) then
|
| 466 |
|
|
BAR0b(15 downto 9) <= dat_i(15 downto 9);
|
| 467 |
|
|
end if;
|
| 468 |
|
|
end if;
|
| 469 |
|
|
end process RBAR0IOWR;
|
| 470 |
|
|
end generate;
|
| 471 |
|
|
|
| 472 |
|
|
|
| 473 |
|
|
|
| 474 |
|
|
--+-------------------------------------------------------------------------+
|
| 475 |
|
|
--| Registers MUX (READ) |
|
| 476 |
|
|
--+-------------------------------------------------------------------------+
|
| 477 |
|
|
RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, IOSPACEENb, BAR0b,
|
| 478 |
|
|
INTLINEr, rdcfg_i )
|
| 479 |
|
|
begin
|
| 480 |
|
|
|
| 481 |
|
|
if ( rdcfg_i = '1' ) then
|
| 482 |
|
|
|
| 483 |
|
|
case adr_i is
|
| 484 |
|
|
|
| 485 |
|
|
when b"000000" =>
|
| 486 |
|
|
dataout <= DEVICEIDr & VENDORIDr;
|
| 487 |
|
|
when b"000001" =>
|
| 488 |
|
|
dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" &
|
| 489 |
|
|
b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & IOSPACEENb;
|
| 490 |
|
|
when b"000010" =>
|
| 491 |
|
|
dataout <= CLASSCODEr & REVISIONIDr;
|
| 492 |
|
|
when b"000100" =>
|
| 493 |
|
|
dataout <= BAR0b;
|
| 494 |
|
|
when b"001011" =>
|
| 495 |
|
|
dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr;
|
| 496 |
|
|
when b"001111" =>
|
| 497 |
|
|
dataout <= b"0000000000000000" & INTPINr & INTLINEr;
|
| 498 |
|
|
when others =>
|
| 499 |
|
|
dataout <= ( others => '0' );
|
| 500 |
|
|
|
| 501 |
|
|
end case;
|
| 502 |
|
|
|
| 503 |
|
|
else
|
| 504 |
|
|
|
| 505 |
|
|
dataout <= ( others => '0' );
|
| 506 |
|
|
|
| 507 |
|
|
end if;
|
| 508 |
|
|
|
| 509 |
|
|
end process RRMUX;
|
| 510 |
|
|
|
| 511 |
|
|
dat_o <= dataout;
|
| 512 |
|
|
|
| 513 |
|
|
|
| 514 |
|
|
--+-------------------------------------------------------------------------+
|
| 515 |
|
|
--| BAR0 & COMMAND REGS bits outputs |
|
| 516 |
|
|
--+-------------------------------------------------------------------------+
|
| 517 |
|
|
|
| 518 |
|
|
bar0_o <= BAR0b(31 downto 9);
|
| 519 |
|
|
perrEN_o <= PERRENb;
|
| 520 |
|
|
serrEN_o <= SERRENb;
|
| 521 |
|
|
memEN_o <= MEMSPACEENb;
|
| 522 |
|
|
ioEN_o <= IOSPACEENb;
|
| 523 |
|
|
|
| 524 |
|
|
|
| 525 |
|
|
end rtl;
|
