Subversion Repositories pci_mini

# ----------------------------------------------------

# Timing constrains sample for the pci_mini IP-core

# ----------------------------------------------------

# Synopsys, Inc. constraint file

# filename

# Written on Wed Apr 13 17:34:51 2011

# by Synplify Pro, D-2009.12A Scope Editor

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#  The user has to change the signal names here to the

#  names used in the application's toplevel file.

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# Collections

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# Clocks

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define_clock   {extPCICLK} -name {extPCICLK}  -freq 33 -clockgroup default_clkgroup_2

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# Clock to Clock

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define_clock_delay  -rise {extPCICLK} -rise {safeclock} -false

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# Inputs/Outputs

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define_input_delay               {extPCI_serr}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_input_delay               {extPCI_perr}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_input_delay               {extPCI_idsel}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_input_delay               {extPCI_stop}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_input_delay               {extPCI_devsel}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_input_delay               {extPCI_trdy}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_input_delay               {extPCI_irdy}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_input_delay               {extPCI_frame}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_input_delay               {extPCI_par}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_input_delay               {extPCI_cbe[3:0]}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_input_delay               {extPCI_AD[31:0]}  23.0 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_output_delay              {extPCI_serr}  22.00 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_output_delay              {extPCI_perr}  22.00 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_output_delay              {extPCI_stop}  22.00 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_output_delay              {extPCI_devsel}  22.00 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_output_delay              {extPCI_trdy}  22.00 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_output_delay              {extPCI_par}  22.00 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

define_output_delay              {extPCI_AD[31:0]}  22.00 -improve 0.00 -route 0.00 -ref {extPCICLK:r}

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# Registers

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# Delay Paths

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# Attributes

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# I/O Standards

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# Compile Points

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# Other

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