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dsmv |
[Project]
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| 2 |
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Current Flow=Multivendor
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| 3 |
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VCS=0
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version=3
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Current Config=compile
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[Configurations]
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compile=sp605_lx45t_wishbone
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[Library]
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sp605_lx45t_wishbone=.\sp605_lx45t_wishbone.LIB
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38 |
dsmv |
sp605_lx45t_wishbone_post_synthesis=.\sp605_lx45t_wishbone_post_synthesis\sp605_lx45t_wishbone_post_synthesis.lib
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2 |
dsmv |
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| 14 |
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[Settings]
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| 15 |
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AccessRead=0
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| 16 |
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AccessReadWrite=0
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| 17 |
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AccessACCB=0
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| 18 |
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AccessACCR=0
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| 19 |
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AccessReadWriteSLP=0
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| 20 |
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AccessReadTopLevel=1
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| 21 |
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DisableC=1
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| 22 |
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ENABLE_ADV_DATAFLOW=0
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38 |
dsmv |
SYNTH_TOOL=MV_XST132
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IMPL_TOOL=MV_ISE132
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2 |
dsmv |
CSYNTH_TOOL=
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PHYSSYNTH_TOOL=
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FLOW_TYPE=HDL
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| 28 |
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LANGUAGE=VHDL
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| 29 |
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FLOWTOOLS=IMPL_WITH_SYNTH
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| 30 |
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ON_SERVERFARM_SYNTH=0
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ON_SERVERFARM_IMPL=0
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| 32 |
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ON_SERVERFARM_SIM=0
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| 33 |
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DVM_DISPLAY=NO
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REFRESH_FLOW=1
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38 |
dsmv |
FAMILY=Xilinx13x SPARTAN6
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2 |
dsmv |
RUN_MODE_SYNTH=0
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38 |
dsmv |
VerilogDirsChanged=0
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2 |
dsmv |
WireDelay=2
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10 |
dsmv |
NoTchkMsg=1
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| 40 |
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NoTimingChecks=1
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2 |
dsmv |
HESPrepare=0
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| 42 |
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EnableXtrace=0
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| 43 |
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SplitNetVectors=0
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| 44 |
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StackMemorySize=32
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| 45 |
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RetvalMemorySize=32
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| 46 |
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VsimAdditionalOptions=-relax
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| 47 |
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ReportAssertionsActivations=0
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| 48 |
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TrackAssertionFailures=1
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| 49 |
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ReportAssertionsFailures=1
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| 50 |
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AssertionFailureLimit=0
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| 51 |
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AssertionFailureAction=Continue
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| 52 |
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TrackAssertionPasses=1
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| 53 |
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ReportAssertionPasses=0
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| 54 |
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AssertionPassLimit=0
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| 55 |
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ReportUnfinishedAssertions=1
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| 56 |
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TrackCoverMatches=1
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| 57 |
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ReportCoverMatches=1
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| 58 |
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CoverAction=Continue
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| 59 |
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ReportDroppedCoverEvaluations=0
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| 60 |
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ReportActivatedCoverEvaluations=0
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| 61 |
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fileopeninsrc=1
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fileopenfolder=E:\prog\ds_dma_project\sp605_lx45t_wishbone
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10 |
dsmv |
DisableVitalMsg=1
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| 64 |
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VitalAccel=1
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| 65 |
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VitalGlitches=1
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| 66 |
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DisableIEEEWarnings=1
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38 |
dsmv |
SYNTH_STATUS=warnings
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| 68 |
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IMPL_STATUS=warnings
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PHYSSYNTH_STATUS=none
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PCBINTERFACE_STATUS=NONE
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| 71 |
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FUNCTIONAL_SIMULATION_STATUS=
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| 72 |
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POSTSYNTHESIS_SIMULATION_STATUS=
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| 73 |
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TIMING_SIMULATION_STATUS=
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| 74 |
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FUNC_LIB=sp605_lx45t_wishbone
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POST_LIB=sp605_lx45t_wishbone_post_synthesis
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RUN_MODE_IMPL=0
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| 77 |
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LAST_IMPL_STATUS=warnings
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2 |
dsmv |
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| 79 |
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[LocalVerilogSets]
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| 80 |
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EnableSLP=1
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| 81 |
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EnableDebug=1
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| 82 |
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VerilogLanguage=4
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| 83 |
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Strict=0
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| 84 |
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Strict2001=
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| 85 |
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SystemVerilog3=
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| 86 |
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StrictLRMMode=
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| 87 |
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VerilogNoSpecify=0
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| 88 |
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WarningPrnLevel=1
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| 89 |
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ErrorOutputLimit=0
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| 90 |
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OptimizationLevel=2
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| 91 |
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ProtectLevel=0
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| 92 |
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AdditionalOptions=
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| 93 |
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MonitoringOfEventsUDP=0
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| 94 |
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DisablePulseError=0
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| 95 |
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HasInitialRegsValue=0
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| 96 |
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InitialRegsValue=X
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| 97 |
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| 98 |
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[LocalVhdlSets]
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| 99 |
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CompileWithDebug=1
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| 100 |
10 |
dsmv |
DisableVHDL87Key=0
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| 101 |
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EnableVHDL93Key=0
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| 102 |
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EnableVHDL2002Key=1
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| 103 |
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EnableVHDL2006Key=0
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| 104 |
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EnableVHDL2008Key=0
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| 105 |
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NetlistCompilation=1
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| 106 |
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Syntax RelaxLRM=0
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| 107 |
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MaxErrorsKey=100
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| 108 |
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OptimizationLevel=3
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| 109 |
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DisableRangeChecks=0
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| 110 |
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ProtectLevel=0
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| 111 |
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AdditionalOptions=
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| 112 |
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IncrementalCompilation=0
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| 113 |
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ReorderOnFirstRebuild=1
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| 114 |
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ElaborationAfterCompilation=0
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| 115 |
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PrintErrWarnOnly=0
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| 116 |
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GenMultiplatformLib=0
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| 117 |
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VhdlChangeEvalAsynchronous=0
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| 118 |
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VhdlDisableAssertionsProcessing=0
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| 119 |
2 |
dsmv |
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| 120 |
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[$LibMap$]
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sp605_lx45t_wishbone=.
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| 122 |
38 |
dsmv |
Active_lib=SPARTAN6
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| 123 |
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xilinxun=SPARTAN6
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| 124 |
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UnlinkedDesignLibrary=SPARTAN6
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| 125 |
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DESIGNS=SPARTAN6
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2 |
dsmv |
|
| 127 |
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[IMPLEMENTATION_XILINX12]
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| 128 |
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impl_opt(dont_run_translate)=0
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| 129 |
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impl_opt(dont_run_map)=0
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| 130 |
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impl_opt(dont_run_place)=0
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| 131 |
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impl_opt(dont_run_trace)=0
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| 132 |
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impl_opt(dont_run_simulation)=0
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| 133 |
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impl_opt(dont_run_fit)=0
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| 134 |
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impl_opt(dont_run_bitgen)=1
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| 135 |
38 |
dsmv |
impl_opt(use_partitions_in_flow)=0
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| 136 |
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impl_opt(partitions_file)=synthesis\xpartition.pxml
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| 137 |
2 |
dsmv |
|
| 138 |
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[HierarchyViewer]
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| 139 |
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SortInfo=u
|
| 140 |
16 |
dsmv |
HierarchyInformation=stend_sp605_wishbone|stend_sp605_wishbone|0
|
| 141 |
2 |
dsmv |
ShowHide=ShowTopLevel
|
| 142 |
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Selected=
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| 143 |
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| 144 |
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[DefineMacro]
|
| 145 |
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Global=
|
| 146 |
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| 147 |
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[Folders]
|
| 148 |
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Name3=Makefiles
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| 149 |
16 |
dsmv |
Directory3=e:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
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| 150 |
2 |
dsmv |
Extension3=mak
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| 151 |
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Name4=Memory
|
| 152 |
16 |
dsmv |
Directory4=e:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\src
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| 153 |
2 |
dsmv |
Extension4=mem;mif;hex
|
| 154 |
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Name5=Dll Libraries
|
| 155 |
16 |
dsmv |
Directory5=e:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
|
| 156 |
2 |
dsmv |
Extension5=dll
|
| 157 |
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Name6=PDF
|
| 158 |
16 |
dsmv |
Directory6=e:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
|
| 159 |
2 |
dsmv |
Extension6=pdf
|
| 160 |
|
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Name7=HTML
|
| 161 |
16 |
dsmv |
Directory7=e:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
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| 162 |
2 |
dsmv |
Extension7=
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| 163 |
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| 164 |
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[Groups]
|
| 165 |
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pcie_src=1
|
| 166 |
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pcie_src\components=1
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| 167 |
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pcie_src\components\block_main=1
|
| 168 |
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pcie_src\components\coregen=1
|
| 169 |
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pcie_src\components\pcie_core=1
|
| 170 |
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pcie_src\components\rtl=1
|
| 171 |
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pcie_src\pcie_core64_m1=1
|
| 172 |
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pcie_src\pcie_core64_m1\pcie_ctrl=1
|
| 173 |
|
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pcie_src\pcie_core64_m1\pcie_fifo_ext=1
|
| 174 |
|
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pcie_src\pcie_core64_m1\source=0
|
| 175 |
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pcie_src\pcie_core64_m1\source_s6=1
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| 176 |
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pcie_src\pcie_core64_m1\source_virtex6=1
|
| 177 |
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pcie_src\pcie_core64_m1\top=1
|
| 178 |
|
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pcie_src\pcie_sim=1
|
| 179 |
|
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pcie_src\pcie_sim\dsport=1
|
| 180 |
|
|
pcie_src\pcie_sim\sim=1
|
| 181 |
|
|
testbench=1
|
| 182 |
|
|
testbench\modelsim=1
|
| 183 |
|
|
testbench\modelsim\zz_do=1
|
| 184 |
4 |
dsmv |
testbench\modelsim\required_tests=1
|
| 185 |
|
|
testbench\modelsim\required_tests\test0=1
|
| 186 |
|
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testbench\modelsim\required_tests\test0\zz_do=1
|
| 187 |
|
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testbench\ahdl=1
|
| 188 |
2 |
dsmv |
top=1
|
| 189 |
|
|
wishbone=1
|
| 190 |
|
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wishbone\block_test_check=1
|
| 191 |
|
|
wishbone\block_test_generate=1
|
| 192 |
|
|
wishbone\cross=1
|
| 193 |
|
|
wishbone\doc=1
|
| 194 |
|
|
wishbone\coregen=1
|
| 195 |
|
|
wishbone\testbecnh=1
|
| 196 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl=1
|
| 197 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim=1
|
| 198 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do=1
|
| 199 |
|
|
wishbone\testbecnh\dev_test_check=1
|
| 200 |
|
|
wishbone\testbecnh\dev_test_check\sim=1
|
| 201 |
|
|
wishbone\testbecnh\dev_test_check\sim\zz_do=1
|
| 202 |
|
|
wishbone\testbecnh\dev_test_gen=1
|
| 203 |
|
|
wishbone\testbecnh\dev_test_gen\sim=1
|
| 204 |
|
|
wishbone\testbecnh\dev_test_gen\sim\zz_do=1
|
| 205 |
|
|
wishbone\testbecnh\dev_wb_cross=1
|
| 206 |
|
|
wishbone\testbecnh\dev_wb_cross\sim=1
|
| 207 |
|
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
|
| 208 |
10 |
dsmv |
testbench\log=1
|
| 209 |
38 |
dsmv |
post-synthesis=1
|
| 210 |
|
|
DESIGN_STATUS=1
|
| 211 |
|
|
DESIGN_STATUS\2013_07_26_01_18=1
|
| 212 |
2 |
dsmv |
|
| 213 |
10 |
dsmv |
[Verilog Library]
|
| 214 |
|
|
ovi_unimacro=
|
| 215 |
|
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ovi_unisim=
|
| 216 |
|
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ovi_xilinxcorelib=
|
| 217 |
|
|
|
| 218 |
38 |
dsmv |
[SYNTHESIS]
|
| 219 |
|
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TOPLEVEL=sp605_lx45t_wishbone
|
| 220 |
|
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FAMILY=Xilinx13x SPARTAN6
|
| 221 |
|
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DEVICE=6slx45tfgg484
|
| 222 |
|
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SPEED=-3
|
| 223 |
|
|
OBSOLETE_ALIASES=1
|
| 224 |
|
|
FILTER_MESSAGES=
|
| 225 |
|
|
FSM_ENCODE=
|
| 226 |
|
|
PACK_IO_REGISTERS=Auto
|
| 227 |
|
|
SIMOUTFORM=1
|
| 228 |
|
|
AUTO_CLOSE_GUI=0
|
| 229 |
|
|
USE_DEF_UCF_FILE=1
|
| 230 |
|
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UCF_FILENAME=
|
| 231 |
|
|
LSO_FILENAME=
|
| 232 |
|
|
HDL_INI_FILENAME=
|
| 233 |
|
|
XST_INCLUDE_PATH=src
|
| 234 |
|
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CORES_SEARCH_DIR=
|
| 235 |
|
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OTHER_COMMAND_LINE_OPT=
|
| 236 |
|
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XST_WORK_DIR=synthesis\xst
|
| 237 |
|
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PARTITIONS_FILE=
|
| 238 |
|
|
Show_OptimizationGoalCombo=Speed
|
| 239 |
|
|
Show_OptimizationEffortCombo=Normal
|
| 240 |
|
|
Show_KeepHierarchyFPGA=Yes
|
| 241 |
|
|
Show_Timing_Constraint=0
|
| 242 |
|
|
Show_FSM_Encoding_Algorithm=Auto
|
| 243 |
|
|
Show_MuxExtractionCombo=Yes
|
| 244 |
|
|
Show_Resource_Sharing=1
|
| 245 |
|
|
Show_Rom_Extraction=1
|
| 246 |
|
|
Show_Ram_Extraction=1
|
| 247 |
|
|
Show_RamStyleCombo=Auto
|
| 248 |
|
|
Show_Shift_Register_Extraction=1
|
| 249 |
|
|
Show_Add_IO_Buffer=1
|
| 250 |
|
|
Show_Equivalent_Register_Removal=0
|
| 251 |
|
|
Show_Max_Fanout=1000000
|
| 252 |
|
|
Show_Register_Duplication=0
|
| 253 |
|
|
Show_Register_Balancing=No
|
| 254 |
|
|
Show_Pack_IO_Registers_Into_IOBs=Auto
|
| 255 |
|
|
Show_Macro_Preserve=1
|
| 256 |
|
|
Show_Xor_Preserve=1
|
| 257 |
|
|
Show_WysiwygCombo=None
|
| 258 |
|
|
Show_Case_Implementation_Style=None
|
| 259 |
|
|
Show_Global_Optimalization_Goal=AllClockNets
|
| 260 |
|
|
Show_JobDescription=SynthesisTask
|
| 261 |
|
|
Show_IncludeInputFiles=*.*
|
| 262 |
|
|
Show_ExcludeInputFiles=log*.*:implement*.*
|
| 263 |
|
|
Show_UseSynthesisConstraintsFile=1
|
| 264 |
|
|
Show_CrossClockAnalysis=0
|
| 265 |
|
|
Show_HierarchySeparator=/
|
| 266 |
|
|
Show_BusDelimiter=<>
|
| 267 |
|
|
Show_GenerateRtlSchematic=Yes
|
| 268 |
|
|
Show_CaseVhdl=Maintain
|
| 269 |
|
|
Show_Verilog2001=1
|
| 270 |
|
|
Show_RomStyle=Auto
|
| 271 |
|
|
Show_ReadCores=1
|
| 272 |
|
|
Show_MaxNoBufgs16=0
|
| 273 |
|
|
Show_OptimizeInstantiatedPrimitives=0
|
| 274 |
|
|
Show_MoveFirstFlipFlopStage=
|
| 275 |
|
|
Show_MoveLastFlipFlopStage=
|
| 276 |
|
|
Show_FSMStyle=LUT
|
| 277 |
|
|
Show_SimulationOutputFormat=1
|
| 278 |
|
|
Show_KeepHierarchyCPLD=Yes
|
| 279 |
|
|
Show_SafeImplementation=No
|
| 280 |
|
|
Show_UseClockEnable=Auto
|
| 281 |
|
|
Show_UseSynchronousSet=Auto
|
| 282 |
|
|
Show_UseSynchronousReset=Auto
|
| 283 |
|
|
Show_FilterMessages=0
|
| 284 |
|
|
Show_DspUtilizationRatio=100
|
| 285 |
|
|
Show_LUT_FF_PairsUtilizationRatio=100
|
| 286 |
|
|
Show_PowerReduction=0
|
| 287 |
|
|
Show_BRAMUtilizationRatio=100
|
| 288 |
|
|
Show_AutomaticBRAMPacking=0
|
| 289 |
|
|
Show_AsynchronousToSynchronous=0
|
| 290 |
|
|
Show_NetlistHierarchy=As Optimized
|
| 291 |
|
|
Show_LUTCombining=Auto
|
| 292 |
|
|
Show_ReduceControlSets=Auto
|
| 293 |
|
|
Show_UseIseWithPartitions=0
|
| 294 |
|
|
Show_GenerateIseWithPartitions=1
|
| 295 |
|
|
Show_Add_Special_Library_Sources=1
|
| 296 |
|
|
Show_UseDSPBlock_S6_V6=Auto
|
| 297 |
|
|
Show_ShiftRegisterMinimumSize=2
|
| 298 |
|
|
Show_OptimizationEffortCombo_Fast=High
|
| 299 |
|
|
RAM_STYLE=Auto
|
| 300 |
|
|
ROM_STYLE=Auto
|
| 301 |
|
|
MUX_STYLE=Auto
|
| 302 |
|
|
MOVE_FIRST_FF_STAGE=1
|
| 303 |
|
|
MOVE_LAST_FF_STAGE=1
|
| 304 |
|
|
JOB_DESCRIPTION=SynthesisTask
|
| 305 |
|
|
SERVERFARM_INCLUDE_INPUT_FILES=*.*
|
| 306 |
|
|
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
|
| 307 |
|
|
JOB_SFM_RESOURCE=
|
| 308 |
|
|
LAST_RUN=1374786428
|
| 309 |
|
|
OUTPUT_NETLIST=synthesis\sp605_lx45t_wishbone.ngc
|
| 310 |
|
|
OUTPUT_SIMUL_NETLIST=synthesis\sp605_lx45t_wishbone.vhd
|
| 311 |
|
|
|
| 312 |
|
|
[PHYS_SYNTHESIS]
|
| 313 |
|
|
FAMILY=Xilinx13x SPARTAN6
|
| 314 |
|
|
DEVICE=6slx45tfgg484
|
| 315 |
|
|
SPEED=-3
|
| 316 |
|
|
SCRIPTS_COPIED=0
|
| 317 |
|
|
IN_DESIGN=synthesis\sp605_lx45t_wishbone.ngc
|
| 318 |
|
|
OUT_DESIGN=
|
| 319 |
|
|
IN_CONSTRAINT=
|
| 320 |
|
|
OUT_CONSTRAINT=
|
| 321 |
|
|
REPORT=
|
| 322 |
|
|
|
| 323 |
|
|
[IMPLEMENTATION]
|
| 324 |
|
|
FLOW_STEPS_RESET=0
|
| 325 |
|
|
FAMILY=Xilinx13x SPARTAN6
|
| 326 |
|
|
DEVICE=6slx45tfgg484
|
| 327 |
|
|
SPEED=-3
|
| 328 |
|
|
NETLIST=synthesis\sp605_lx45t_wishbone.ngc
|
| 329 |
|
|
IS_BAT_MODE=0
|
| 330 |
|
|
BAT_FILE=
|
| 331 |
|
|
UCF=src\top\sp605_lx45t_wishbone.ucf
|
| 332 |
|
|
DEF_UCF=2
|
| 333 |
|
|
OLD_FAMILY=Xilinx13x SPARTAN6
|
| 334 |
|
|
wasChanged_Change_Device_Speed=0
|
| 335 |
|
|
wasChanged_Change_Device_Speed_To=0
|
| 336 |
|
|
wasChanged_Change_Device_Speed_To2=1
|
| 337 |
|
|
Place_And_Route_Mode_old_value=Route Only
|
| 338 |
|
|
JOB_DESCRIPTION=ImplementationTask
|
| 339 |
|
|
SERVERFARM_INCLUDE_INPUT_FILES=*.*
|
| 340 |
|
|
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*
|
| 341 |
|
|
JOB_SFM_RESOURCE=
|
| 342 |
|
|
SYNTH_TOOL_RESET=0
|
| 343 |
|
|
LAST_RUN=1374786709
|
| 344 |
|
|
|
| 345 |
|
|
[IMPLEMENTATION_XILINX13]
|
| 346 |
|
|
impl_opt(dont_run_translate)=0
|
| 347 |
|
|
impl_opt(dont_run_map)=0
|
| 348 |
|
|
impl_opt(dont_run_place)=0
|
| 349 |
|
|
impl_opt(dont_run_trace)=0
|
| 350 |
|
|
impl_opt(dont_run_simulation)=1
|
| 351 |
|
|
impl_opt(dont_run_fit)=0
|
| 352 |
|
|
impl_opt(dont_run_bitgen)=0
|
| 353 |
|
|
Macro_Search_Path={src\wishbone\coregen} {src\pcie_src\components\coregen}
|
| 354 |
|
|
impl_opt(partitions_file)=
|
| 355 |
|
|
impl_opt(use_partitions_file)=0
|
| 356 |
|
|
impl_opt(smart_guide_file)=
|
| 357 |
|
|
impl_opt(use_smart_guide)=0
|
| 358 |
|
|
impl_opt(edif_str)=synthesis\sp605_lx45t_wishbone.ngc
|
| 359 |
|
|
impl_opt(_family_sel)=Xilinx13x SPARTAN6
|
| 360 |
|
|
impl_opt(_device_sel)=6slx45tfgg484
|
| 361 |
|
|
impl_opt(_speed_sel)=-3
|
| 362 |
|
|
impl_opt(Effort_Level)=Standard
|
| 363 |
|
|
impl_opt(netlist_format)=1
|
| 364 |
|
|
impl_opt(auto_close)=0
|
| 365 |
|
|
impl_opt(override_existing_project)=1
|
| 366 |
|
|
impl_opt(bat_file_name)=
|
| 367 |
|
|
impl_opt(is_bat_mode)=0
|
| 368 |
|
|
impl_opt(def_ucf)=Custom constraint file
|
| 369 |
|
|
impl_opt(ucf_str)=src\top\sp605_lx45t_wishbone.ucf
|
| 370 |
|
|
impl_opt(version_sel)=ver1
|
| 371 |
|
|
impl_opt(revision_sel)=rev1
|
| 372 |
|
|
impl_opt(insert_pads)=0
|
| 373 |
|
|
impl_opt(Pack_IO_Registers_Latches)=For Inputs and Outputs
|
| 374 |
|
|
impl_opt(ignore_rloc_constraints)=1
|
| 375 |
|
|
impl_opt(create_detailed_report)=0
|
| 376 |
|
|
impl_opt(ngdbuild_file_str)=
|
| 377 |
|
|
impl_opt(use_ngdbuild_file)=0
|
| 378 |
|
|
impl_opt(map_file_str)=
|
| 379 |
|
|
impl_opt(use_map_file)=0
|
| 380 |
|
|
impl_opt(par_file_str)=
|
| 381 |
|
|
impl_opt(use_par_file)=0
|
| 382 |
|
|
impl_opt(trace_file_str)=
|
| 383 |
|
|
impl_opt(use_trace_file)=0
|
| 384 |
|
|
impl_opt(netgen_file_str)=
|
| 385 |
|
|
impl_opt(use_netgen_file)=0
|
| 386 |
|
|
impl_opt(bitgen_file_str)=
|
| 387 |
|
|
impl_opt(use_bitgen_file)=0
|
| 388 |
|
|
impl_opt(Allow_Unmatched_LOC_Constraint)=1
|
| 389 |
|
|
impl_opt(Show_Trim_Unconnected_Signals)=1
|
| 390 |
|
|
impl_opt(Place_And_Route_Mode)=Route Only
|
| 391 |
|
|
impl_opt(Show_Generate_Multiple_Hierarchical_Netlist_Files)=0
|
| 392 |
|
|
impl_opt(Show_Bring_Out_Global_Trisate_Net_As_Ports)=
|
| 393 |
|
|
impl_opt(Use_Show_Bring_Out_Global_Trisate_Net_As_Ports)=0
|
| 394 |
|
|
impl_opt(Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=
|
| 395 |
|
|
impl_opt(Use_Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=0
|
| 396 |
|
|
impl_opt(Show_Generate_Testbench_File)=UUT
|
| 397 |
|
|
impl_opt(Use_Show_Generate_Testbench_File)=0
|
| 398 |
|
|
impl_opt(Netlist_Translation_Type)=Timestamp
|
| 399 |
|
|
impl_opt(Allow_Unexpanded_Blocks)=0
|
| 400 |
|
|
impl_opt(Other_Ngdbuild_Options)=
|
| 401 |
|
|
impl_opt(Map_Effort_Level)=High
|
| 402 |
|
|
impl_opt(Allow_Logic_Opt_Across_Hier)=1
|
| 403 |
|
|
impl_opt(Use_Rloc_Constraints)=Yes
|
| 404 |
|
|
impl_opt(Show_Map_Slice_Logic_Into_Unused_Blocks)=0
|
| 405 |
|
|
impl_opt(Other_Map_Options)=
|
| 406 |
|
|
impl_opt(Extra_Effort)=None
|
| 407 |
|
|
impl_opt(Retain_Hiearchy)=1
|
| 408 |
|
|
impl_opt(Change_Device_Speed)=3
|
| 409 |
|
|
impl_opt(Tristate_Configuration_Pulsee)=0
|
| 410 |
|
|
impl_opt(Reset_Configuration_Pulsee)=100
|
| 411 |
|
|
impl_opt(Generate_Architecture_Only)=0
|
| 412 |
|
|
impl_opt(Include_Uselib_Directive)=0
|
| 413 |
|
|
impl_opt(Do_Not_Escape_Signal)=0
|
| 414 |
|
|
impl_opt(Other_Netgen_Command)=
|
| 415 |
|
|
impl_opt(Show_Other_Place_Route_Command)=
|
| 416 |
|
|
impl_opt(Use_Rules_File_For_Nelist)=
|
| 417 |
|
|
impl_opt(Path_Used_In_Sdf)=implement
|
| 418 |
|
|
impl_opt(Insert_ChipScope_Core)=0
|
| 419 |
|
|
impl_opt(Run_ChipScope_Core_Inserter_GUI)=1
|
| 420 |
|
|
impl_opt(ChipScope_Core_Inserter_Project_File)=synthesis\sp605_lx45t_wishbone.cdc
|
| 421 |
|
|
impl_opt(_use_filter_messages)=0
|
| 422 |
|
|
impl_opt(_filter_messages)=
|
| 423 |
|
|
impl_opt(AdvMap_Extra_Effort)=None
|
| 424 |
|
|
impl_opt(Map_Starting_Placer_Cost_Table)=1
|
| 425 |
|
|
impl_opt(Show_Register_Duplication)=0
|
| 426 |
|
|
impl_opt(Include_Function_In_Verilog_File)=1
|
| 427 |
|
|
impl_opt(Include_Simprim_Models_In_Verilog_File)=0
|
| 428 |
|
|
impl_opt(Show_Equivalent_Register_Removal)=1
|
| 429 |
|
|
impl_opt(run_design_rules_checker)=1
|
| 430 |
|
|
impl_opt(create_bit_file)=1
|
| 431 |
|
|
impl_opt(create_binary_config_file)=0
|
| 432 |
|
|
impl_opt(create_ascii_config_file)=0
|
| 433 |
|
|
impl_opt(create_ieee_1532_config_file_fpga)=0
|
| 434 |
|
|
impl_opt(enable_bitstream_compression)=1
|
| 435 |
|
|
impl_opt(enable_debugging_of_serial_mode_bitstream)=0
|
| 436 |
|
|
impl_opt(enable_cyclic_redundancy_checking)=1
|
| 437 |
|
|
impl_opt(other_bitgen_command_line_options)=
|
| 438 |
|
|
impl_opt(security)=Enable Readback and Reconfiguration
|
| 439 |
|
|
impl_opt(create_readback_data_files)=0
|
| 440 |
|
|
impl_opt(allow_selectmap_pins_to_persist)=0
|
| 441 |
|
|
impl_opt(create_logic_allocation_file)=0
|
| 442 |
|
|
impl_opt(create_mask_file)=0
|
| 443 |
|
|
impl_opt(encrypt_bitstream)=0
|
| 444 |
|
|
impl_opt(key_0)=
|
| 445 |
|
|
impl_opt(input_encryption_key_file)=
|
| 446 |
|
|
impl_opt(starting_cbc_value)=
|
| 447 |
|
|
impl_opt(fpga_start_up_clock)=CCLK
|
| 448 |
|
|
impl_opt(enable_internal_done_pipe)=0
|
| 449 |
|
|
impl_opt(done_output_events)=4
|
| 450 |
|
|
impl_opt(enable_outputs)=5
|
| 451 |
|
|
impl_opt(release_write_enable)=6
|
| 452 |
|
|
impl_opt(drive_done_pin_high)=1
|
| 453 |
|
|
impl_opt(configuration_rate)=2
|
| 454 |
|
|
impl_opt(configuration_pin_program)=Pull Up
|
| 455 |
|
|
impl_opt(configuration_pin_done)=Pull Up
|
| 456 |
|
|
impl_opt(jtag_pin_tck)=Pull Up
|
| 457 |
|
|
impl_opt(jtag_pin_tdi)=Pull Up
|
| 458 |
|
|
impl_opt(jtag_pin_tdo)=Pull Up
|
| 459 |
|
|
impl_opt(jtag_pin_tms)=Pull Up
|
| 460 |
|
|
impl_opt(unused_iob_pins)=Pull Up
|
| 461 |
|
|
impl_opt(userid_code)=0xFFFFFFFF
|
| 462 |
|
|
impl_opt(merge_netlists_before_insertion)=1
|
| 463 |
|
|
impl_opt(chipscope_bat_file_str)=
|
| 464 |
|
|
impl_opt(use_chipscope_bat_file)=0
|
| 465 |
|
|
impl_opt(Rename_Top_Level_Architecture_to)=Structure
|
| 466 |
|
|
impl_opt(Rename_Top_Level_Entity_to)=
|
| 467 |
|
|
impl_opt(Rename_Top_Level_Module_to)=
|
| 468 |
|
|
impl_opt(Combinatorial_Logic_Optimization)=1
|
| 469 |
|
|
impl_opt(Generate_Asynchronous_Delay_Report)=0
|
| 470 |
|
|
impl_opt(Generate_Clock_Region_Report)=0
|
| 471 |
|
|
impl_opt(Power_Reduction_Par)=0
|
| 472 |
|
|
impl_opt(Enable_Incremental_Design_Flow)=0
|
| 473 |
|
|
impl_opt(Run_Guided_Incremental_Design_Flow)=0
|
| 474 |
|
|
impl_opt(Report_Type)=Verbose report
|
| 475 |
|
|
impl_opt(Number_of_items_in_Error_Verbose_Report)=3
|
| 476 |
|
|
impl_opt(Perform_Advanced_Analysis)=0
|
| 477 |
|
|
impl_opt(Change_Device_Speed_To)=3
|
| 478 |
|
|
impl_opt(Report_Uncovered_Paths)=
|
| 479 |
|
|
impl_opt(Report_Fastest_Path_in_Each_Constraint)=1
|
| 480 |
|
|
impl_opt(post_map_file_str)=
|
| 481 |
|
|
impl_opt(use_post_map_file)=0
|
| 482 |
|
|
impl_opt(Report_Type2)=Error report
|
| 483 |
|
|
impl_opt(Number_of_items_in_Error_Verbose_Report2)=3
|
| 484 |
|
|
impl_opt(Perform_Advanced_Analysis2)=0
|
| 485 |
|
|
impl_opt(Change_Device_Speed_To2)=3
|
| 486 |
|
|
impl_opt(Report_Uncovered_Paths2)=
|
| 487 |
|
|
impl_opt(Report_Fastest_Path_in_Each_Constraint2)=1
|
| 488 |
|
|
impl_opt(Stamp_Timing_Model_Filename)=
|
| 489 |
|
|
impl_opt(Constraints_Interaction_Report_File2)=
|
| 490 |
|
|
impl_opt(dont_run_post_map_trace)=1
|
| 491 |
|
|
impl_opt(automatically_insert_glbl_module)=1
|
| 492 |
|
|
impl_opt(maximum_compression)=0
|
| 493 |
|
|
impl_opt(Output_Extended_Identifiers)=0
|
| 494 |
|
|
impl_opt(enable_suspend_wake_global_set_reset)=0
|
| 495 |
|
|
impl_opt(drive_awake_pin_during_suspend_wake_sequence)=0
|
| 496 |
|
|
impl_opt(wakeup_control)=Startup Clock
|
| 497 |
|
|
impl_opt(gwe_cycle_during_suspend_wakeup_sequence)=5
|
| 498 |
|
|
impl_opt(gts_cycle_during_suspend_wakeup_sequence)=4
|
| 499 |
|
|
impl_opt(ChipScope_Overwrite_Project_File)=0
|
| 500 |
|
|
impl_opt(insert_buffers_to_prevent_pulse_swallowing)=1
|
| 501 |
|
|
impl_opt(Report_Paths_By_Endpoint)=3
|
| 502 |
|
|
impl_opt(Generate_Datasheet_Section)=1
|
| 503 |
|
|
impl_opt(Generate_Timegroups_Section)=0
|
| 504 |
|
|
impl_opt(Constraints_Interaction_Report_File)=
|
| 505 |
|
|
impl_opt(Ignore_User_Timing_Constraints_Map)=0
|
| 506 |
|
|
impl_opt(Power_Activity_File_Map)=
|
| 507 |
|
|
impl_opt(Ignore_User_Timing_Constraints_Par)=0
|
| 508 |
|
|
impl_opt(Timing_Mode_Par)=Performance Evaluation
|
| 509 |
|
|
impl_opt(Power_Activity_File_Par)=
|
| 510 |
|
|
impl_opt(Report_Paths_By_Endpoint2)=3
|
| 511 |
|
|
impl_opt(Generate_Datasheet_Section2)=1
|
| 512 |
|
|
impl_opt(Generate_Timegroups_Section2)=0
|
| 513 |
|
|
impl_opt(retry_configuration_if_crc_error_occurs)=0
|
| 514 |
|
|
impl_opt(place_multiboot_settings_into_bitstream)=0
|
| 515 |
|
|
impl_opt(multiboot_starting_address_for_next_configuration)=0x00000000
|
| 516 |
|
|
impl_opt(multiboot_use_new_mode_for_next_configuration)=1
|
| 517 |
|
|
impl_opt(multiboot_next_configuration_mode)=001
|
| 518 |
|
|
impl_opt(Timing_Mode_Map_Virtex5)=Performance Evaluation
|
| 519 |
|
|
impl_opt(LUT_Combining)=Auto
|
| 520 |
|
|
impl_opt(Global_Optimization_Virtex5)=Off
|
| 521 |
|
|
impl_opt(Enable_Multi_Threading_Map)=Off
|
| 522 |
|
|
impl_opt(enable_external_master_clock)=0
|
| 523 |
|
|
impl_opt(setup_external_master_clock_division)=1
|
| 524 |
|
|
impl_opt(set_spi_configuration_bus_width)=1
|
| 525 |
|
|
impl_opt(multiboot_starting_address_for_golden_configuration)=0x00000000
|
| 526 |
|
|
impl_opt(multiboot_user_defined_register_for_failsafe_scheme)=0x0000
|
| 527 |
|
|
impl_opt(wait_for_dcm_and_pll_lock)=NoWait
|
| 528 |
|
|
impl_opt(enable_multi_pin_wake_up_suspend_mode)=0
|
| 529 |
|
|
impl_opt(mask_pins_for_multi_pin_wake_up_suspend_mode)=0x00
|
| 530 |
|
|
impl_opt(encrypt_key_select)=BBRAM
|
| 531 |
|
|
impl_opt(Watchdog_Timer_Value_Spartan6)=0xFFFF
|
| 532 |
|
|
impl_opt(Allow_Unmatched_Timing_Group_Constraints)=0
|
| 533 |
|
|
impl_opt(Extra_Cost_Tables)=0
|
| 534 |
|
|
impl_opt(Enable_Multi_Threading_Par)=Off
|
| 535 |
|
|
impl_opt(Power_Reduction_Map_Virtex6)=Off
|
| 536 |
|
|
impl_opt(Register_Ordering)=4
|
| 537 |
|
|
|
| 538 |
|
|
[PCB_INTERFACE]
|
| 539 |
|
|
FAMILY=
|
| 540 |
|
|
|
| 541 |
2 |
dsmv |
[Files]
|
| 542 |
|
|
pcie_src\components\block_main/block_pe_main.vhd=-1
|
| 543 |
|
|
pcie_src\components\coregen/ctrl_fifo64x34fw.ngc=-1
|
| 544 |
|
|
pcie_src\components\coregen/ctrl_fifo64x34fw.vhd=-1
|
| 545 |
|
|
pcie_src\components\coregen/ctrl_fifo64x34fw.xco=-1
|
| 546 |
|
|
pcie_src\components\coregen/ctrl_fifo64x37st.ngc=-1
|
| 547 |
|
|
pcie_src\components\coregen/ctrl_fifo64x37st.vhd=-1
|
| 548 |
|
|
pcie_src\components\coregen/ctrl_fifo64x37st.xco=-1
|
| 549 |
|
|
pcie_src\components\coregen/ctrl_fifo64x67fw.ngc=-1
|
| 550 |
|
|
pcie_src\components\coregen/ctrl_fifo64x67fw.vhd=-1
|
| 551 |
|
|
pcie_src\components\coregen/ctrl_fifo64x67fw.xco=-1
|
| 552 |
|
|
pcie_src\components\coregen/ctrl_fifo64x70st.ngc=-1
|
| 553 |
|
|
pcie_src\components\coregen/ctrl_fifo64x70st.vhd=-1
|
| 554 |
|
|
pcie_src\components\coregen/ctrl_fifo64x70st.xco=-1
|
| 555 |
|
|
pcie_src\components\coregen/ctrl_fifo512x64st_v0.ngc=-1
|
| 556 |
|
|
pcie_src\components\coregen/ctrl_fifo512x64st_v0.vhd=-1
|
| 557 |
|
|
pcie_src\components\coregen/ctrl_fifo512x64st_v0.xco=-1
|
| 558 |
|
|
pcie_src\components\coregen/read.me=-1
|
| 559 |
|
|
pcie_src\components\pcie_core/pcie_core64_m2.vhd=-1
|
| 560 |
|
|
pcie_src\components\pcie_core/pcie_core64_m5.vhd=-1
|
| 561 |
|
|
pcie_src\components\pcie_core/pcie_core64_m7.vhd=-1
|
| 562 |
|
|
pcie_src\components\pcie_core/pcie_core64_wishbone.vhd=-1
|
| 563 |
38 |
dsmv |
pcie_src\components\pcie_core/pcie_core64_wishbone_m8.vhd=-1
|
| 564 |
2 |
dsmv |
pcie_src\components\rtl/host_pkg.vhd=-1
|
| 565 |
|
|
pcie_src\components\rtl/core64_pb_transaction.vhd=-1
|
| 566 |
|
|
pcie_src\components\rtl/ctrl_ram16_v1.vhd=-1
|
| 567 |
|
|
pcie_src\components\rtl/core64_pb_wishbone.vhd=-1
|
| 568 |
|
|
pcie_src\components\rtl/core64_pb_wishbone_ctrl.v=-1
|
| 569 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_type_pkg.vhd=-1
|
| 570 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_interrupt.vhd=-1
|
| 571 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_pb_disp.vhd=-1
|
| 572 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_reg_access.vhd=-1
|
| 573 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine.vhd=-1
|
| 574 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine_m2.vhd=-1
|
| 575 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine_m4.vhd=-1
|
| 576 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine.vhd=-1
|
| 577 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine_m2.vhd=-1
|
| 578 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine_m4.vhd=-1
|
| 579 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_dma_adr.vhd=-1
|
| 580 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_dma_ext_cmd.vhd=-1
|
| 581 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ext_descriptor.vhd=-1
|
| 582 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_main.vhd=-1
|
| 583 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ram_cmd_pb.vhd=-1
|
| 584 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ram_cmd.vhd=-1
|
| 585 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ext_ram.vhd=-1
|
| 586 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/block_pe_fifo_ext.vhd=-1
|
| 587 |
|
|
pcie_src\pcie_core64_m1\source/bram_common.v=-1
|
| 588 |
|
|
pcie_src\pcie_core64_m1\source/cfg_wr_enable.v=-1
|
| 589 |
|
|
pcie_src\pcie_core64_m1\source/cmm_decoder.v=-1
|
| 590 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_cnt_en.v=-1
|
| 591 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_cnt_nfl_en.v=-1
|
| 592 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_cor.v=-1
|
| 593 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_cpl.v=-1
|
| 594 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_ftl.v=-1
|
| 595 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_nfl.v=-1
|
| 596 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_ram4x26.v=-1
|
| 597 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_ram8x26.v=-1
|
| 598 |
|
|
pcie_src\pcie_core64_m1\source/cmm_intr.v=-1
|
| 599 |
|
|
pcie_src\pcie_core64_m1\source/ctrl_pcie_x8.v=-1
|
| 600 |
|
|
pcie_src\pcie_core64_m1\source/ctrl_pcie_x8.xco=-1
|
| 601 |
|
|
pcie_src\pcie_core64_m1\source/extend_clk.v=-1
|
| 602 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf.v=-1
|
| 603 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_arb.v=-1
|
| 604 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_err.v=-1
|
| 605 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_mgmt.v=-1
|
| 606 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_pwr.v=-1
|
| 607 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_if.v=-1
|
| 608 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll.v=-1
|
| 609 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_arb.v=-1
|
| 610 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_credit.v=-1
|
| 611 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_oqbqfifo.v=-1
|
| 612 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_tx.v=-1
|
| 613 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_tx_arb.v=-1
|
| 614 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_plus_ll_rx.v=-1
|
| 615 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_plus_ll_tx.v=-1
|
| 616 |
|
|
pcie_src\pcie_core64_m1\source/pcie_clocking.v=-1
|
| 617 |
|
|
pcie_src\pcie_core64_m1\source/pcie_ep.v=-1
|
| 618 |
|
|
pcie_src\pcie_core64_m1\source/pcie_gtx_wrapper.v=-1
|
| 619 |
|
|
pcie_src\pcie_core64_m1\source/pcie_gt_wrapper.v=-1
|
| 620 |
|
|
pcie_src\pcie_core64_m1\source/pcie_gt_wrapper_top.v=-1
|
| 621 |
|
|
pcie_src\pcie_core64_m1\source/pcie_mim_wrapper.v=-1
|
| 622 |
|
|
pcie_src\pcie_core64_m1\source/pcie_reset_logic.v=-1
|
| 623 |
|
|
pcie_src\pcie_core64_m1\source/pcie_soft_int.v=-1
|
| 624 |
|
|
pcie_src\pcie_core64_m1\source/pcie_top.v=-1
|
| 625 |
|
|
pcie_src\pcie_core64_m1\source/prod_fixes.v=-1
|
| 626 |
|
|
pcie_src\pcie_core64_m1\source/sync_fifo.v=-1
|
| 627 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk.v=-1
|
| 628 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk_bar.v=-1
|
| 629 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk_mal.v=-1
|
| 630 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk_pwr_mgmt.v=-1
|
| 631 |
|
|
pcie_src\pcie_core64_m1\source/tx_sync_gtp.v=-1
|
| 632 |
|
|
pcie_src\pcie_core64_m1\source/tx_sync_gtx.v=-1
|
| 633 |
|
|
pcie_src\pcie_core64_m1\source/use_newinterrupt.v=-1
|
| 634 |
|
|
pcie_src\pcie_core64_m1\source_s6/cl_s6pcie_m2.vhd=-1
|
| 635 |
|
|
pcie_src\pcie_core64_m1\source_s6/gtpa1_dual_wrapper.vhd=-1
|
| 636 |
|
|
pcie_src\pcie_core64_m1\source_s6/gtpa1_dual_wrapper_tile.vhd=-1
|
| 637 |
|
|
pcie_src\pcie_core64_m1\source_s6/pcie_brams_s6.vhd=-1
|
| 638 |
|
|
pcie_src\pcie_core64_m1\source_s6/pcie_bram_s6.vhd=-1
|
| 639 |
|
|
pcie_src\pcie_core64_m1\source_s6/pcie_bram_top_s6.vhd=-1
|
| 640 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_rx.vhd=-1
|
| 641 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_rx_null_gen.vhd=-1
|
| 642 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_rx_pipeline.vhd=-1
|
| 643 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_top.vhd=-1
|
| 644 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_tx.vhd=-1
|
| 645 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_tx_pipeline.vhd=-1
|
| 646 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_tx_thrtl_ctl.vhd=-1
|
| 647 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/cl_v6pcie_m1.vhd=-1
|
| 648 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/cl_v6pcie_x4.vhd=-1
|
| 649 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/cl_v6pcie_x4.xco=-1
|
| 650 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd=-1
|
| 651 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_rx_valid_filter_v6.vhd=-1
|
| 652 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_tx_sync_rate_v6.vhd=-1
|
| 653 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_wrapper_v6.vhd=-1
|
| 654 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_2_0_v6.vhd=-1
|
| 655 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_brams_v6.vhd=-1
|
| 656 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_bram_top_v6.vhd=-1
|
| 657 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_bram_v6.vhd=-1
|
| 658 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_clocking_v6.vhd=-1
|
| 659 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_gtx_v6.vhd=-1
|
| 660 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_pipe_lane_v6.vhd=-1
|
| 661 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_pipe_misc_v6.vhd=-1
|
| 662 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_pipe_v6.vhd=-1
|
| 663 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_reset_delay_v6.vhd=-1
|
| 664 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_upconfig_fix_3451_v6.vhd=-1
|
| 665 |
|
|
pcie_src\pcie_core64_m1\top/pcie_core64_m1.vhd=-1
|
| 666 |
|
|
pcie_src\pcie_core64_m1\top/pcie_core64_m4.vhd=-1
|
| 667 |
|
|
pcie_src\pcie_core64_m1\top/pcie_core64_m6.vhd=-1
|
| 668 |
|
|
pcie_src\pcie_sim\dsport/glbl.v=-1
|
| 669 |
|
|
pcie_src\pcie_sim\dsport/pcie_2_0_rport_v6.vhd=-1
|
| 670 |
|
|
pcie_src\pcie_sim\dsport/pcie_2_0_v6_rp.vhd=-1
|
| 671 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_cfg.vhd=-1
|
| 672 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_pl.vhd=-1
|
| 673 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_rx_m2.vhd=-1
|
| 674 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_tx_m2.vhd=-1
|
| 675 |
|
|
pcie_src\pcie_sim\dsport/test_interface.vhd=-1
|
| 676 |
|
|
pcie_src\pcie_sim\dsport/xilinx_pcie_rport_m2.vhd=-1
|
| 677 |
|
|
pcie_src\pcie_sim\sim/block_pkg.vhd=-1
|
| 678 |
|
|
pcie_src\pcie_sim\sim/cmd_sim_pkg.vhd=-1
|
| 679 |
|
|
pcie_src\pcie_sim\sim/root_memory_pkg.vhd=-1
|
| 680 |
|
|
pcie_src\pcie_sim\sim/trd_pcie_pkg.vhd=-1
|
| 681 |
4 |
dsmv |
testbench/wb_block_pkg.vhd=-1
|
| 682 |
|
|
testbench/test_pkg.vhd=-1
|
| 683 |
2 |
dsmv |
testbench/stend_sp605_wishbone.vhd=-1
|
| 684 |
|
|
testbench\modelsim/delete.bat=-1
|
| 685 |
|
|
testbench\modelsim/start.bat=-1
|
| 686 |
|
|
testbench\modelsim/wave.do=-1
|
| 687 |
|
|
testbench\modelsim\zz_do/delete.do=-1
|
| 688 |
|
|
testbench\modelsim\zz_do/setup_sim.do=-1
|
| 689 |
|
|
testbench\modelsim\required_tests/SciTE.session=-1
|
| 690 |
|
|
testbench\modelsim\required_tests\test0/block_check_wb_burst_slave_0.v=-1
|
| 691 |
|
|
testbench\modelsim\required_tests\test0/delete.bat=-1
|
| 692 |
|
|
testbench\modelsim\required_tests\test0/read.me=-1
|
| 693 |
|
|
testbench\modelsim\required_tests\test0/start.bat=-1
|
| 694 |
|
|
testbench\modelsim\required_tests\test0/wave.do=-1
|
| 695 |
|
|
testbench\modelsim\required_tests\test0\zz_do/delete.do=-1
|
| 696 |
|
|
testbench\modelsim\required_tests\test0\zz_do/setup_sim.do=-1
|
| 697 |
4 |
dsmv |
testbench\ahdl/test_gen.awf=-1
|
| 698 |
|
|
testbench\ahdl/pb_wishbone.awf=-1
|
| 699 |
|
|
testbench\ahdl/rx.awf=-1
|
| 700 |
|
|
testbench\ahdl/tx.awf=-1
|
| 701 |
10 |
dsmv |
testbench\ahdl/run_ahdl.tcl=-1
|
| 702 |
38 |
dsmv |
testbench\log/console_test_adm_read_8kb.log=-1
|
| 703 |
|
|
testbench\log/console_test_dsc_incorrect.log=-1
|
| 704 |
|
|
testbench\log/console_test_read 4 kB.log=-1
|
| 705 |
|
|
testbench\log/console_test_read_4kB.log=-1
|
| 706 |
|
|
testbench\log/file_id_0.log=-1
|
| 707 |
|
|
testbench\log/file_id_1.log=-1
|
| 708 |
|
|
testbench\log/file_id_2.log=-1
|
| 709 |
|
|
testbench\log/global_tc_summary.log=-1
|
| 710 |
2 |
dsmv |
top/sp605_lx45t_wishbone.ucf=-1
|
| 711 |
|
|
top/sp605_lx45t_wishbone_sopc_wb.vhd=-1
|
| 712 |
|
|
top/sp605_lx45t_wishbone.vhd=-1
|
| 713 |
|
|
wishbone\block_test_check/block_check_wb_pkg.vhd=-1
|
| 714 |
|
|
wishbone\block_test_check/block_check_wb_burst_slave.v=-1
|
| 715 |
|
|
wishbone\block_test_check/block_check_wb_config_slave.vhd=-1
|
| 716 |
|
|
wishbone\block_test_check/cl_test_check.vhd=-1
|
| 717 |
|
|
wishbone\block_test_check/block_test_check_wb.vhd=-1
|
| 718 |
|
|
wishbone\block_test_generate/block_generate_wb_burst_slave.v=-1
|
| 719 |
|
|
wishbone\block_test_generate/block_generate_wb_config_slave.vhd=-1
|
| 720 |
|
|
wishbone\block_test_generate/block_generate_wb_pkg.vhd=-1
|
| 721 |
|
|
wishbone\block_test_generate/cl_test_generate.vhd=-1
|
| 722 |
|
|
wishbone\block_test_generate/block_test_generate_wb.vhd=-1
|
| 723 |
|
|
wishbone\cross/read.me=-1
|
| 724 |
|
|
wishbone\cross/wb_conmax_arb.v=-1
|
| 725 |
|
|
wishbone\cross/wb_conmax_defines.v=-1
|
| 726 |
|
|
wishbone\cross/wb_conmax_master_if.v=-1
|
| 727 |
|
|
wishbone\cross/wb_conmax_msel.v=-1
|
| 728 |
|
|
wishbone\cross/wb_conmax_pri_dec.v=-1
|
| 729 |
|
|
wishbone\cross/wb_conmax_pri_enc.v=-1
|
| 730 |
|
|
wishbone\cross/wb_conmax_rf.v=-1
|
| 731 |
|
|
wishbone\cross/wb_conmax_slave_if.v=-1
|
| 732 |
|
|
wishbone\cross/wb_conmax_top.v=-1
|
| 733 |
|
|
wishbone\cross/wb_conmax_top_pkg.vhd=-1
|
| 734 |
|
|
wishbone\doc/block_test_generate.htm=-1
|
| 735 |
|
|
wishbone\doc/style.css=-1
|
| 736 |
|
|
wishbone\doc/block_test_check.htm=-1
|
| 737 |
|
|
wishbone\doc/wishbonbe_test.htm=-1
|
| 738 |
|
|
wishbone\coregen/ctrl_fifo1024x64_st_v1.ngc=-1
|
| 739 |
|
|
wishbone\coregen/ctrl_fifo1024x64_st_v1.vhd=-1
|
| 740 |
|
|
wishbone\coregen/ctrl_fifo1024x64_st_v1.xco=-1
|
| 741 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl/SciTE.session=-1
|
| 742 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/delete.bat=-1
|
| 743 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/ds_dma_pb_if.v=-1
|
| 744 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/start.bat=-1
|
| 745 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/tb.v=-1
|
| 746 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/wave.do=-1
|
| 747 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/wb_simple_ram_slave_if.v=-1
|
| 748 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/wb_slave_if.v=-1
|
| 749 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do/delete.do=-1
|
| 750 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do/setup_sim.do=-1
|
| 751 |
|
|
wishbone\testbecnh\dev_test_check/SciTE.session=-1
|
| 752 |
|
|
wishbone\testbecnh\dev_test_check\sim/delete.bat=-1
|
| 753 |
|
|
wishbone\testbecnh\dev_test_check\sim/ds_dma_test_check_burst_master_if.v=-1
|
| 754 |
|
|
wishbone\testbecnh\dev_test_check\sim/ds_dma_test_check_burst_master_if.vPreview=-1
|
| 755 |
|
|
wishbone\testbecnh\dev_test_check\sim/start.bat=-1
|
| 756 |
|
|
wishbone\testbecnh\dev_test_check\sim/tb.v=-1
|
| 757 |
|
|
wishbone\testbecnh\dev_test_check\sim/wave.do=-1
|
| 758 |
|
|
wishbone\testbecnh\dev_test_check\sim\zz_do/delete.do=-1
|
| 759 |
|
|
wishbone\testbecnh\dev_test_check\sim\zz_do/setup_sim.do=-1
|
| 760 |
|
|
wishbone\testbecnh\dev_test_gen/SciTE.session=-1
|
| 761 |
|
|
wishbone\testbecnh\dev_test_gen\sim/delete.bat=-1
|
| 762 |
|
|
wishbone\testbecnh\dev_test_gen\sim/ds_dma_test_gen_burst_master_if.v=-1
|
| 763 |
|
|
wishbone\testbecnh\dev_test_gen\sim/start.bat=-1
|
| 764 |
|
|
wishbone\testbecnh\dev_test_gen\sim/tb.v=-1
|
| 765 |
|
|
wishbone\testbecnh\dev_test_gen\sim/wave.do=-1
|
| 766 |
|
|
wishbone\testbecnh\dev_test_gen\sim\zz_do/delete.do=-1
|
| 767 |
|
|
wishbone\testbecnh\dev_test_gen\sim\zz_do/setup_sim.do=-1
|
| 768 |
|
|
wishbone\testbecnh\dev_wb_cross/SciTE.session=-1
|
| 769 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/delete.bat=-1
|
| 770 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/start.bat=-1
|
| 771 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/tb.v=-1
|
| 772 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wave.do=-1
|
| 773 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wb_intf.sv=-1
|
| 774 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wb_tb_simple_master.sv=-1
|
| 775 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wb_tb_simple_ram_slave.v=-1
|
| 776 |
|
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do/delete.do=-1
|
| 777 |
|
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do/setup_sim.do=-1
|
| 778 |
38 |
dsmv |
post-synthesis/..\..\synthesis\sp605_lx45t_wishbone.vhd=-1
|
| 779 |
|
|
DESIGN_STATUS\2013_07_26_01_18/ComputerInformation.txt=-1
|
| 780 |
|
|
DESIGN_STATUS\2013_07_26_01_18/DesignInformation.txt=-1
|
| 781 |
|
|
DESIGN_STATUS\2013_07_26_01_18/DesignFiles.txt=-1
|
| 782 |
|
|
DESIGN_STATUS\2013_07_26_01_18/LibrariesList.txt=-1
|
| 783 |
|
|
DESIGN_STATUS\2013_07_26_01_18/synthesis_synthesis.dfml=-1
|
| 784 |
|
|
DESIGN_STATUS\2013_07_26_01_18/implement_ver1_rev1_implementation.dfml=-1
|
| 785 |
2 |
dsmv |
|
| 786 |
|
|
[Files.Data]
|
| 787 |
|
|
.\src\pcie_src\components\block_main\block_pe_main.vhd=VHDL Source Code
|
| 788 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.ngc=External File
|
| 789 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.vhd=VHDL Source Code
|
| 790 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x34fw.xco=External File
|
| 791 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x37st.ngc=External File
|
| 792 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x37st.vhd=VHDL Source Code
|
| 793 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x37st.xco=External File
|
| 794 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.ngc=External File
|
| 795 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.vhd=VHDL Source Code
|
| 796 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x67fw.xco=External File
|
| 797 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x70st.ngc=External File
|
| 798 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x70st.vhd=VHDL Source Code
|
| 799 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo64x70st.xco=External File
|
| 800 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.ngc=External File
|
| 801 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.vhd=VHDL Source Code
|
| 802 |
|
|
.\src\pcie_src\components\coregen\ctrl_fifo512x64st_v0.xco=External File
|
| 803 |
|
|
.\src\pcie_src\components\coregen\read.me=External File
|
| 804 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_m2.vhd=VHDL Source Code
|
| 805 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_m5.vhd=VHDL Source Code
|
| 806 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_m7.vhd=VHDL Source Code
|
| 807 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_wishbone.vhd=VHDL Source Code
|
| 808 |
38 |
dsmv |
.\src\pcie_src\components\pcie_core\pcie_core64_wishbone_m8.vhd=VHDL Source Code
|
| 809 |
2 |
dsmv |
.\src\pcie_src\components\rtl\host_pkg.vhd=VHDL Source Code
|
| 810 |
|
|
.\src\pcie_src\components\rtl\core64_pb_transaction.vhd=VHDL Source Code
|
| 811 |
|
|
.\src\pcie_src\components\rtl\ctrl_ram16_v1.vhd=VHDL Source Code
|
| 812 |
|
|
.\src\pcie_src\components\rtl\core64_pb_wishbone.vhd=VHDL Source Code
|
| 813 |
|
|
.\src\pcie_src\components\rtl\core64_pb_wishbone_ctrl.v=Verilog Source Code
|
| 814 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_type_pkg.vhd=VHDL Source Code
|
| 815 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_interrupt.vhd=VHDL Source Code
|
| 816 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_pb_disp.vhd=VHDL Source Code
|
| 817 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_reg_access.vhd=VHDL Source Code
|
| 818 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine.vhd=VHDL Source Code
|
| 819 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine_m2.vhd=VHDL Source Code
|
| 820 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine_m4.vhd=VHDL Source Code
|
| 821 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine.vhd=VHDL Source Code
|
| 822 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine_m2.vhd=VHDL Source Code
|
| 823 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine_m4.vhd=VHDL Source Code
|
| 824 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_dma_adr.vhd=VHDL Source Code
|
| 825 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_dma_ext_cmd.vhd=VHDL Source Code
|
| 826 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ext_descriptor.vhd=VHDL Source Code
|
| 827 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_main.vhd=VHDL Source Code
|
| 828 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ram_cmd_pb.vhd=VHDL Source Code
|
| 829 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ram_cmd.vhd=VHDL Source Code
|
| 830 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ext_ram.vhd=VHDL Source Code
|
| 831 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\block_pe_fifo_ext.vhd=VHDL Source Code
|
| 832 |
|
|
.\src\pcie_src\pcie_core64_m1\source\bram_common.v=Verilog Source Code
|
| 833 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cfg_wr_enable.v=Verilog Source Code
|
| 834 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_decoder.v=Verilog Source Code
|
| 835 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cnt_en.v=Verilog Source Code
|
| 836 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cnt_nfl_en.v=Verilog Source Code
|
| 837 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cor.v=Verilog Source Code
|
| 838 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cpl.v=Verilog Source Code
|
| 839 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ftl.v=Verilog Source Code
|
| 840 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_nfl.v=Verilog Source Code
|
| 841 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ram4x26.v=Verilog Source Code
|
| 842 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ram8x26.v=Verilog Source Code
|
| 843 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_intr.v=Verilog Source Code
|
| 844 |
|
|
.\src\pcie_src\pcie_core64_m1\source\ctrl_pcie_x8.v=Verilog Source Code
|
| 845 |
|
|
.\src\pcie_src\pcie_core64_m1\source\ctrl_pcie_x8.xco=External File
|
| 846 |
|
|
.\src\pcie_src\pcie_core64_m1\source\extend_clk.v=Verilog Source Code
|
| 847 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf.v=Verilog Source Code
|
| 848 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_arb.v=Verilog Source Code
|
| 849 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_err.v=Verilog Source Code
|
| 850 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_mgmt.v=Verilog Source Code
|
| 851 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_pwr.v=Verilog Source Code
|
| 852 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_if.v=Verilog Source Code
|
| 853 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll.v=Verilog Source Code
|
| 854 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_arb.v=Verilog Source Code
|
| 855 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_credit.v=Verilog Source Code
|
| 856 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_oqbqfifo.v=Verilog Source Code
|
| 857 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_tx.v=Verilog Source Code
|
| 858 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_tx_arb.v=Verilog Source Code
|
| 859 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_plus_ll_rx.v=Verilog Source Code
|
| 860 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_plus_ll_tx.v=Verilog Source Code
|
| 861 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_clocking.v=Verilog Source Code
|
| 862 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_ep.v=Verilog Source Code
|
| 863 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_gtx_wrapper.v=Verilog Source Code
|
| 864 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_gt_wrapper.v=Verilog Source Code
|
| 865 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_gt_wrapper_top.v=Verilog Source Code
|
| 866 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_mim_wrapper.v=Verilog Source Code
|
| 867 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_reset_logic.v=Verilog Source Code
|
| 868 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_soft_int.v=Verilog Source Code
|
| 869 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_top.v=Verilog Source Code
|
| 870 |
|
|
.\src\pcie_src\pcie_core64_m1\source\prod_fixes.v=Verilog Source Code
|
| 871 |
|
|
.\src\pcie_src\pcie_core64_m1\source\sync_fifo.v=Verilog Source Code
|
| 872 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk.v=Verilog Source Code
|
| 873 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_bar.v=Verilog Source Code
|
| 874 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_mal.v=Verilog Source Code
|
| 875 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_pwr_mgmt.v=Verilog Source Code
|
| 876 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tx_sync_gtp.v=Verilog Source Code
|
| 877 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tx_sync_gtx.v=Verilog Source Code
|
| 878 |
|
|
.\src\pcie_src\pcie_core64_m1\source\use_newinterrupt.v=Verilog Source Code
|
| 879 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\cl_s6pcie_m2.vhd=VHDL Source Code
|
| 880 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\gtpa1_dual_wrapper.vhd=VHDL Source Code
|
| 881 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\gtpa1_dual_wrapper_tile.vhd=VHDL Source Code
|
| 882 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\pcie_brams_s6.vhd=VHDL Source Code
|
| 883 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\pcie_bram_s6.vhd=VHDL Source Code
|
| 884 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\pcie_bram_top_s6.vhd=VHDL Source Code
|
| 885 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx.vhd=VHDL Source Code
|
| 886 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx_null_gen.vhd=VHDL Source Code
|
| 887 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx_pipeline.vhd=VHDL Source Code
|
| 888 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_top.vhd=VHDL Source Code
|
| 889 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx.vhd=VHDL Source Code
|
| 890 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx_pipeline.vhd=VHDL Source Code
|
| 891 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx_thrtl_ctl.vhd=VHDL Source Code
|
| 892 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_m1.vhd=VHDL Source Code
|
| 893 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_x4.vhd=VHDL Source Code
|
| 894 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_x4.xco=External File
|
| 895 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_drp_chanalign_fix_3752_v6.vhd=VHDL Source Code
|
| 896 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_rx_valid_filter_v6.vhd=VHDL Source Code
|
| 897 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_tx_sync_rate_v6.vhd=VHDL Source Code
|
| 898 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_wrapper_v6.vhd=VHDL Source Code
|
| 899 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_2_0_v6.vhd=VHDL Source Code
|
| 900 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_brams_v6.vhd=VHDL Source Code
|
| 901 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_bram_top_v6.vhd=VHDL Source Code
|
| 902 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_bram_v6.vhd=VHDL Source Code
|
| 903 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_clocking_v6.vhd=VHDL Source Code
|
| 904 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_gtx_v6.vhd=VHDL Source Code
|
| 905 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_lane_v6.vhd=VHDL Source Code
|
| 906 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_misc_v6.vhd=VHDL Source Code
|
| 907 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_v6.vhd=VHDL Source Code
|
| 908 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_reset_delay_v6.vhd=VHDL Source Code
|
| 909 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_upconfig_fix_3451_v6.vhd=VHDL Source Code
|
| 910 |
|
|
.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m1.vhd=VHDL Source Code
|
| 911 |
|
|
.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m4.vhd=VHDL Source Code
|
| 912 |
|
|
.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m6.vhd=VHDL Source Code
|
| 913 |
|
|
.\src\pcie_src\pcie_sim\dsport\glbl.v=Verilog Source Code
|
| 914 |
|
|
.\src\pcie_src\pcie_sim\dsport\pcie_2_0_rport_v6.vhd=VHDL Source Code
|
| 915 |
|
|
.\src\pcie_src\pcie_sim\dsport\pcie_2_0_v6_rp.vhd=VHDL Source Code
|
| 916 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_cfg.vhd=VHDL Source Code
|
| 917 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_pl.vhd=VHDL Source Code
|
| 918 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_rx_m2.vhd=VHDL Source Code
|
| 919 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_tx_m2.vhd=VHDL Source Code
|
| 920 |
|
|
.\src\pcie_src\pcie_sim\dsport\test_interface.vhd=VHDL Source Code
|
| 921 |
|
|
.\src\pcie_src\pcie_sim\dsport\xilinx_pcie_rport_m2.vhd=VHDL Source Code
|
| 922 |
|
|
.\src\pcie_src\pcie_sim\sim\block_pkg.vhd=VHDL Source Code
|
| 923 |
|
|
.\src\pcie_src\pcie_sim\sim\cmd_sim_pkg.vhd=VHDL Source Code
|
| 924 |
|
|
.\src\pcie_src\pcie_sim\sim\root_memory_pkg.vhd=VHDL Source Code
|
| 925 |
|
|
.\src\pcie_src\pcie_sim\sim\trd_pcie_pkg.vhd=VHDL Source Code
|
| 926 |
4 |
dsmv |
.\src\testbench\wb_block_pkg.vhd=VHDL Source Code
|
| 927 |
|
|
.\src\testbench\test_pkg.vhd=VHDL Source Code
|
| 928 |
2 |
dsmv |
.\src\testbench\stend_sp605_wishbone.vhd=VHDL Source Code
|
| 929 |
|
|
.\src\testbench\modelsim\delete.bat=External File
|
| 930 |
|
|
.\src\testbench\modelsim\start.bat=External File
|
| 931 |
|
|
.\src\testbench\modelsim\wave.do=Macro
|
| 932 |
|
|
.\src\testbench\modelsim\zz_do\delete.do=Macro
|
| 933 |
|
|
.\src\testbench\modelsim\zz_do\setup_sim.do=Macro
|
| 934 |
|
|
.\src\testbench\modelsim\required_tests\SciTE.session=External File
|
| 935 |
|
|
.\src\testbench\modelsim\required_tests\test0\block_check_wb_burst_slave_0.v=Verilog Source Code
|
| 936 |
|
|
.\src\testbench\modelsim\required_tests\test0\delete.bat=External File
|
| 937 |
|
|
.\src\testbench\modelsim\required_tests\test0\read.me=External File
|
| 938 |
|
|
.\src\testbench\modelsim\required_tests\test0\start.bat=External File
|
| 939 |
|
|
.\src\testbench\modelsim\required_tests\test0\wave.do=Macro
|
| 940 |
|
|
.\src\testbench\modelsim\required_tests\test0\zz_do\delete.do=Macro
|
| 941 |
|
|
.\src\testbench\modelsim\required_tests\test0\zz_do\setup_sim.do=Macro
|
| 942 |
4 |
dsmv |
.\src\testbench\ahdl\test_gen.awf=Waveform File
|
| 943 |
|
|
.\src\testbench\ahdl\pb_wishbone.awf=Waveform File
|
| 944 |
|
|
.\src\testbench\ahdl\rx.awf=Waveform File
|
| 945 |
|
|
.\src\testbench\ahdl\tx.awf=Waveform File
|
| 946 |
10 |
dsmv |
.\src\testbench\ahdl\run_ahdl.tcl=Tcl Script
|
| 947 |
38 |
dsmv |
.\src\testbench\log\console_test_adm_read_8kb.log=Text File
|
| 948 |
|
|
.\src\testbench\log\console_test_dsc_incorrect.log=Text File
|
| 949 |
|
|
.\src\testbench\log\console_test_read 4 kB.log=Text File
|
| 950 |
|
|
.\src\testbench\log\console_test_read_4kB.log=Text File
|
| 951 |
|
|
.\src\testbench\log\file_id_0.log=Text File
|
| 952 |
|
|
.\src\testbench\log\file_id_1.log=Text File
|
| 953 |
|
|
.\src\testbench\log\file_id_2.log=Text File
|
| 954 |
|
|
.\src\testbench\log\global_tc_summary.log=Text File
|
| 955 |
2 |
dsmv |
.\src\top\sp605_lx45t_wishbone.ucf=External File
|
| 956 |
|
|
.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd=VHDL Source Code
|
| 957 |
|
|
.\src\top\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
| 958 |
|
|
.\src\wishbone\block_test_check\block_check_wb_pkg.vhd=VHDL Source Code
|
| 959 |
|
|
.\src\wishbone\block_test_check\block_check_wb_burst_slave.v=Verilog Source Code
|
| 960 |
|
|
.\src\wishbone\block_test_check\block_check_wb_config_slave.vhd=VHDL Source Code
|
| 961 |
|
|
.\src\wishbone\block_test_check\cl_test_check.vhd=VHDL Source Code
|
| 962 |
|
|
.\src\wishbone\block_test_check\block_test_check_wb.vhd=VHDL Source Code
|
| 963 |
|
|
.\src\wishbone\block_test_generate\block_generate_wb_burst_slave.v=Verilog Source Code
|
| 964 |
|
|
.\src\wishbone\block_test_generate\block_generate_wb_config_slave.vhd=VHDL Source Code
|
| 965 |
|
|
.\src\wishbone\block_test_generate\block_generate_wb_pkg.vhd=VHDL Source Code
|
| 966 |
|
|
.\src\wishbone\block_test_generate\cl_test_generate.vhd=VHDL Source Code
|
| 967 |
|
|
.\src\wishbone\block_test_generate\block_test_generate_wb.vhd=VHDL Source Code
|
| 968 |
|
|
.\src\wishbone\cross\read.me=External File
|
| 969 |
|
|
.\src\wishbone\cross\wb_conmax_arb.v=Verilog Source Code
|
| 970 |
|
|
.\src\wishbone\cross\wb_conmax_defines.v=Verilog Source Code
|
| 971 |
|
|
.\src\wishbone\cross\wb_conmax_master_if.v=Verilog Source Code
|
| 972 |
|
|
.\src\wishbone\cross\wb_conmax_msel.v=Verilog Source Code
|
| 973 |
|
|
.\src\wishbone\cross\wb_conmax_pri_dec.v=Verilog Source Code
|
| 974 |
|
|
.\src\wishbone\cross\wb_conmax_pri_enc.v=Verilog Source Code
|
| 975 |
|
|
.\src\wishbone\cross\wb_conmax_rf.v=Verilog Source Code
|
| 976 |
|
|
.\src\wishbone\cross\wb_conmax_slave_if.v=Verilog Source Code
|
| 977 |
|
|
.\src\wishbone\cross\wb_conmax_top.v=Verilog Source Code
|
| 978 |
|
|
.\src\wishbone\cross\wb_conmax_top_pkg.vhd=VHDL Source Code
|
| 979 |
|
|
.\src\wishbone\doc\block_test_generate.htm=HTML Document
|
| 980 |
|
|
.\src\wishbone\doc\style.css=External File
|
| 981 |
|
|
.\src\wishbone\doc\block_test_check.htm=HTML Document
|
| 982 |
|
|
.\src\wishbone\doc\wishbonbe_test.htm=HTML Document
|
| 983 |
|
|
.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.ngc=External File
|
| 984 |
|
|
.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.vhd=VHDL Source Code
|
| 985 |
|
|
.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.xco=External File
|
| 986 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\SciTE.session=External File
|
| 987 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\delete.bat=External File
|
| 988 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\ds_dma_pb_if.v=Verilog Source Code
|
| 989 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\start.bat=External File
|
| 990 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\tb.v=Verilog Source Code
|
| 991 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wave.do=Macro
|
| 992 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wb_simple_ram_slave_if.v=Verilog Source Code
|
| 993 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wb_slave_if.v=Verilog Source Code
|
| 994 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do\delete.do=Macro
|
| 995 |
|
|
.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do\setup_sim.do=Macro
|
| 996 |
|
|
.\src\wishbone\testbecnh\dev_test_check\SciTE.session=External File
|
| 997 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\delete.bat=External File
|
| 998 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\ds_dma_test_check_burst_master_if.v=Verilog Source Code
|
| 999 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\ds_dma_test_check_burst_master_if.vPreview=External File
|
| 1000 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\start.bat=External File
|
| 1001 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\tb.v=Verilog Source Code
|
| 1002 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\wave.do=Macro
|
| 1003 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\zz_do\delete.do=Macro
|
| 1004 |
|
|
.\src\wishbone\testbecnh\dev_test_check\sim\zz_do\setup_sim.do=Macro
|
| 1005 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\SciTE.session=External File
|
| 1006 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\delete.bat=External File
|
| 1007 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\ds_dma_test_gen_burst_master_if.v=Verilog Source Code
|
| 1008 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\start.bat=External File
|
| 1009 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\tb.v=Verilog Source Code
|
| 1010 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\wave.do=Macro
|
| 1011 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\zz_do\delete.do=Macro
|
| 1012 |
|
|
.\src\wishbone\testbecnh\dev_test_gen\sim\zz_do\setup_sim.do=Macro
|
| 1013 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\SciTE.session=External File
|
| 1014 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\delete.bat=External File
|
| 1015 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\start.bat=External File
|
| 1016 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\tb.v=Verilog Source Code
|
| 1017 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wave.do=Macro
|
| 1018 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_intf.sv=SystemVerilog Source Code
|
| 1019 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_master.sv=SystemVerilog Source Code
|
| 1020 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_ram_slave.v=Verilog Source Code
|
| 1021 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\delete.do=Macro
|
| 1022 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\setup_sim.do=Macro
|
| 1023 |
38 |
dsmv |
.\synthesis\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
| 1024 |
|
|
.\src\DESIGN_STATUS\2013_07_26_01_18\ComputerInformation.txt=Text File
|
| 1025 |
|
|
.\src\DESIGN_STATUS\2013_07_26_01_18\DesignInformation.txt=Text File
|
| 1026 |
|
|
.\src\DESIGN_STATUS\2013_07_26_01_18\DesignFiles.txt=Text File
|
| 1027 |
|
|
.\src\DESIGN_STATUS\2013_07_26_01_18\LibrariesList.txt=Text File
|
| 1028 |
|
|
.\src\DESIGN_STATUS\2013_07_26_01_18\synthesis_synthesis.dfml=Text File
|
| 1029 |
|
|
.\src\DESIGN_STATUS\2013_07_26_01_18\implement_ver1_rev1_implementation.dfml=Text File
|
| 1030 |
10 |
dsmv |
|
