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[/] [pcie_mini/] [trunk/] [main_sources/] [xilinx_pcie2wb.vhd] - Blame information for rev 4

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1 2 buenos 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer: Istvan Nagy, buenos@freemail.hu
4 
--
5 3 buenos 
-- Create Date:    05/30/2010
6 
-- Modify date:    04/26/2011
7 2 buenos 
-- Design Name:    pcie_mini
8 
-- Module Name:    xilinx_pcie2wb - Behavioral
9 4 buenos 
-- Version:        1.2
10 2 buenos 
-- Project Name:
11 4 buenos 
-- Target Devices: Xilinx Series-5/6/7 FPGAs (This code is tested on Spartan-6 XC6SLX45T)
12 2 buenos 
-- Tool versions: ISE-DS 12.1
13 
-- Description:
14 
--  PCI-express endpoint block, transaction layer logic and back-end logic. The main
15 
--  purpose of this file is to make a useable back-end interface and handle flow control
16 
--  for the xilinx auto-generated PCIe endpoint IP.
17 
--  The PCIe endpoint implements one 256MByte memory BAR (Base Address Register).
18 
--  This 256MBytes size is set up in the core config, and also hardcoded in this
19 
--  file (search for: "256MBytes").
20 
--  This 1 BAR is implemented as a Wishbone master interface with byte addressing,
21 
--  where address [x:2] shows DWORD address, while sel[3:0] decodes the 2 LSBs.
22 
--  ADDRESSES ARE BYTE ADDRESSES.
23 
--  The lower address bits are usually zero, so the slave (MCB) has to select bytes based
24 
--  on the byte select signals: sel[3:0]. The output address of the core contails the 2
25 
--  LSBs as well. The core was only tested with 32-bit accesses, byte-wide might work or not.
26 
--  The TLP logic is capable of handling up to 1k bytes (256 DWORDs) payload data in a
27 
--  single PCIe transaction, and can handle only one request at a time. If a new request
28 
--  is arriving while processing the previous one (e.g. getting the data from a wishbone
29 
--  read), then the state machine will not process it immediately, or it will hang. So
30 
--  the user software has to wait for the previous read completion before issueing a new
31 
--  request. The multiple DWORDs are handled separately by the WB statemachine.
32 
--  Performance: WishBone bus: 62.5MHz, 32bit, 2clk/access -> 125MBytes/sec. The maximum
33 
--  data throughput can be achieved when using the maximum data payload (block).
34 
--  The core uses INTA wirtual wire to signal interrupts.
35 
--
36 
-- x1 PCIe, legacy endpoint, uses a 100MHz ref clock. The generated core had to
37 
-- be edited manually to support 100MHz, as per Xilinx AR#33761.
38 
--
39 
-- Dependencies: The CoreGenerator's configured PCIe core is included.
40 
--  If we generate a new pcie endpoint, then copy the new files from the source
41 
--  directory into the project's directory, and copy the generic section of the "pcie"
42 
--  from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
43 4 buenos 
--
44 
-- Device Type Migration:
45 
--  This core should work on any Xilinx Series-5/6/7 FPGAs, but at now it runs on XC6SLX45T.
46 
--  For a new device (not an XC6SLX45T) we have to regenerate the Coregenerator cores,
47 
--  replace all BUFIO2/MGT/BUFG/BRAM (and other) to the chosen device's appropriate resources,
48 
--  in both the VHDL and the UCF sources. Also in the UCF the BUFIO2 and MGT placements
49 
--  will have to be re-specified with the appropriate resources/locations. The coregenerator
50 
--  will have to be set up to generate cores with the same parameters and ports as they are
51 
--  used here (to be useable as a drop-in replacement). Some resources are instantiated as
52 
--  part of the Coregen cores, so they will be chosen by Coregen appropriately, we just need
53 
--  to adjust their LOC placement constraints in the UCF file.
54 
--
55 
-- Coregenerator parameters:
56 
--  PCIe-EP: Name=pcie, Type=LegacyPCIe-EP, BAR0=mem/256MB, BAR1+=off, ROM=off, Max Payload=512Bytes,
57 
--           ASPM-L1=off, SlotCLK=off, IRQ=INTA, DeviceSpecInit=off, D1/D2=on, PME_from=D0,
58 
--           Set D0 power (4W), DSN=enabled, PCI_ConfSp=off, PCIe_Extended_ConfSp=off,
59 
--           no_scram =off, Xil_Refboard=None, RefClkFreq=125MHz, TranscLoc/Ch="leave default".
60 
--  Blockram: Name=blk_mem_gen_v4_1, Type=SimpleDpRAM, WriteEn=off, Algor=MinArea,
61 
--            WriteWidth=32, WriteDepth=512, Ena=AlwaysEnabled, ReadWidth=32, RegisterPorttB=off
62 
--            LoadInitFile=off, Fill=off, UseRSTB=off.
63 
--
64 2 buenos 
-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
65 
--
66 
-- Revision:
67 
-- Revision 0.01 - File Created
68 
 
69 
--
70 
----------------------------------------------------------------------------------
71 
library IEEE;
72 
use IEEE.STD_LOGIC_1164.ALL;
73 
use IEEE.STD_LOGIC_ARITH.ALL;
74 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
75 
 
76 
-- Uncomment the following library declaration if instantiating
77 
-- any Xilinx primitives in this code.
78 
library UNISIM;
79 
use UNISIM.VComponents.all;
80 
 
81 
 
82 
 
83 
entity xilinx_pcie2wb is
84 
    Port ( --FPGA PINS(EXTERNAL):
85 
                         pci_exp_txp             : out std_logic;
86 
                         pci_exp_txn             : out std_logic;
87 
                         pci_exp_rxp             : in  std_logic;
88 
                         pci_exp_rxn             : in  std_logic;
89 
                         sys_clk_n                 : in  std_logic;
90 
                         sys_clk_p                 : in  std_logic;
91 
                         sys_reset_n             : in  std_logic;
92 
                         --ON CHIP PORTS:
93 
                         --DATA BUS for BAR0 (wishbone):
94 
                         pcie_bar0_wb_data_o : out std_logic_vector(31 downto 0);
95 
                         pcie_bar0_wb_data_i : in std_logic_vector(31 downto 0);
96 
                         pcie_bar0_wb_addr_o : out std_logic_vector(27 downto 0);
97 
                         pcie_bar0_wb_cyc_o : out std_logic;
98 
                         pcie_bar0_wb_stb_o : out std_logic;
99 
                         pcie_bar0_wb_wr_o : out std_logic;
100 
                         pcie_bar0_wb_ack_i : in std_logic;
101 
                         pcie_bar0_wb_clk_o : out std_logic; --62.5MHz
102 
                         pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0);
103 
                         --OTHER:
104 
                         pcie_irq : in std_logic;
105 
                         pcie_resetout  : out std_logic --active high
106 
                        );
107 
end xilinx_pcie2wb;
108 
 
109 
 
110 
 
111 
 
112 
architecture Behavioral of xilinx_pcie2wb is
113 
 
114 
 
115 
 
116 
 
117 
   -- Internal Signals ------------------------------------------------------------
118 
        --SIGNAL dummy : std_logic_vector(15 downto 0); --write data bus
119 
        SIGNAL          cfg_do  :               std_logic_vector(31     downto  0);
120 
        SIGNAL          cfg_rd_wr_done_n        :               std_logic;
121 
        SIGNAL          cfg_dwaddr      :               std_logic_vector(9      downto  0);
122 
        SIGNAL          cfg_rd_en_n     :               std_logic;
123 
        SIGNAL          cfg_err_ur_n    :               std_logic;
124 
        SIGNAL          cfg_err_cor_n   :               std_logic;
125 
        SIGNAL          cfg_err_ecrc_n  :               std_logic;
126 
        SIGNAL          cfg_err_cpl_timeout_n   :               std_logic;
127 
        SIGNAL          cfg_err_cpl_abort_n     :               std_logic;
128 
        SIGNAL          cfg_err_posted_n        :               std_logic;
129 
        SIGNAL          cfg_err_locked_n        :               std_logic;
130 
        SIGNAL          cfg_err_tlp_cpl_header  :               std_logic_vector(47     downto  0);
131 
        SIGNAL          cfg_err_cpl_rdy_n       :               std_logic;
132 
        SIGNAL          cfg_interrupt_n :               std_logic;
133 
        SIGNAL          cfg_interrupt_rdy_n     :               std_logic;
134 
        SIGNAL          cfg_interrupt_assert_n  :               std_logic;
135 
        SIGNAL          cfg_interrupt_do        :               std_logic_vector(7      downto  0);
136 
        SIGNAL          cfg_interrupt_di        :               std_logic_vector(7      downto  0);
137 
        SIGNAL          cfg_interrupt_mmenable  :               std_logic_vector(2      downto  0);
138 
        SIGNAL          cfg_interrupt_msienable :               std_logic;
139 
        SIGNAL          cfg_turnoff_ok_n        :               std_logic;
140 
        SIGNAL          cfg_to_turnoff_n        :               std_logic;
141 
        SIGNAL          cfg_pm_wake_n   :               std_logic;
142 
        SIGNAL          cfg_pcie_link_state_n   :               std_logic_vector(2      downto  0);
143 
        SIGNAL          cfg_trn_pending_n       :               std_logic;
144 
        SIGNAL          cfg_dsn :               std_logic_vector(63     downto  0);
145 
        SIGNAL          cfg_bus_number  :               std_logic_vector(7      downto  0);
146 
        SIGNAL          cfg_device_number       :               std_logic_vector(4      downto  0);
147 
        SIGNAL          cfg_function_number     :               std_logic_vector(2      downto  0);
148 
        SIGNAL          cfg_status      :               std_logic_vector(15     downto  0);
149 
        SIGNAL          cfg_command     :               std_logic_vector(15     downto  0);
150 
        SIGNAL          cfg_dstatus     :               std_logic_vector(15     downto  0);
151 
        SIGNAL          cfg_dcommand    :               std_logic_vector(15     downto  0);
152 
        SIGNAL          cfg_lstatus     :               std_logic_vector(15     downto  0);
153 
        SIGNAL          cfg_lcommand    :               std_logic_vector(15     downto  0);
154 
    -- System Interface
155 
        SIGNAL      sys_clk                 :   std_logic;
156 
        SIGNAL      trn_clk                 :  std_logic;
157 
        SIGNAL      trn_reset_n             :  std_logic;
158 
        SIGNAL      received_hot_reset      :  std_logic;
159 
    -- Transaction (TRN) Interface
160 
        SIGNAL      trn_lnk_up_n            :  std_logic;
161 
        --      data interface Tx
162 
        SIGNAL          trn_td  :               std_logic_vector(31     downto  0);
163 
        SIGNAL          trn_tsof_n      :               std_logic;
164 
        SIGNAL          trn_teof_n      :               std_logic;
165 
        SIGNAL          trn_tsrc_rdy_n  :               std_logic;
166 
        SIGNAL          trn_tdst_rdy_n  :               std_logic;
167 
        SIGNAL          trn_terr_drop_n :               std_logic;
168 
        SIGNAL          trn_tsrc_dsc_n  :               std_logic;
169 
        SIGNAL          trn_terrfwd_n   :               std_logic;
170 
        SIGNAL          trn_tbuf_av     :               std_logic_vector(5      downto  0);
171 
        SIGNAL          trn_tstr_n      :               std_logic;
172 
        SIGNAL          trn_tcfg_req_n  :               std_logic;
173 
        SIGNAL          trn_tcfg_gnt_n  :               std_logic;
174 
        --      data interface Rx
175 
        SIGNAL          trn_rd  :               std_logic_vector(31     downto  0);
176 
        SIGNAL          trn_rsof_n      :               std_logic;
177 
        SIGNAL          trn_reof_n      :               std_logic;
178 
        SIGNAL          trn_rsrc_rdy_n  :               std_logic;
179 
        SIGNAL          trn_rsrc_dsc_n  :               std_logic;
180 
        SIGNAL          trn_rdst_rdy_n  :               std_logic;
181 
        SIGNAL          trn_rerrfwd_n   :               std_logic;
182 
        SIGNAL          trn_rnp_ok_n    :               std_logic;
183 
        SIGNAL          trn_rbar_hit_n  :               std_logic_vector(6      downto  0);
184 
        -- flow control
185 
        SIGNAL          trn_fc_sel      :               std_logic_vector(2      downto  0);
186 
        SIGNAL          trn_fc_nph      :               std_logic_vector(7      downto  0);
187 
        SIGNAL          trn_fc_npd      :               std_logic_vector(11     downto  0);
188 
        SIGNAL          trn_fc_ph       :               std_logic_vector(7      downto  0);
189 
        SIGNAL          trn_fc_pd       :               std_logic_vector(11     downto  0);
190 
        SIGNAL          trn_fc_cplh     :               std_logic_vector(7      downto  0);
191 
        SIGNAL          trn_fc_cpld     :               std_logic_vector(11     downto  0);
192 
 
193 
        SIGNAL   start_read_wb0 :               std_logic;
194 
        SIGNAL   start_write_wb0        :               std_logic;
195 
        SIGNAL   wb_transaction_complete        :               std_logic;
196 
        SIGNAL   pcie_bar0_wb_data_i_latched    :               std_logic_vector(31     downto  0);
197 
        SIGNAL   pcie_bar0_wb_data_o_feed       :               std_logic_vector(31     downto  0);
198 
        SIGNAL   pcie_bar0_wb_addr_o_feed       :               std_logic_vector(27     downto  0);
199 
        SIGNAL   pcie_bar0_wb_sel_o_feed        :               std_logic_vector(3      downto  0);
200 
        SIGNAL   start_read_wb1 :               std_logic;
201 
        SIGNAL   start_write_wb1        :               std_logic;
202 
        SIGNAL   rd_data_ready_wb1      :               std_logic;
203 
 
204 
    SIGNAL   pcie_just_received_a_new_tlp      :  std_logic  ;
205 
    SIGNAL   pcie_start_reading_rx_tlp      :  std_logic  ;
206 
    SIGNAL   pcie_there_is_a_new_tlp_to_transmit      :  std_logic  ;
207 
    SIGNAL   rxtlp_decodedaddress      :  std_logic_vector(31 downto 0);
208 
    SIGNAL   tlp_payloadsize_dwords      :  std_logic_vector(7 downto 0);
209 
    SIGNAL   rxtlp_firstdw_be      :  std_logic_vector(3 downto 0);
210 
    SIGNAL   rxtlp_lastdw_be      :  std_logic_vector(3 downto 0);
211 
    SIGNAL   rxtlp_requesterid      :  std_logic_vector(15 downto 0);
212 
    SIGNAL   tlp_state      :  std_logic_vector(7 downto 0);
213 
    SIGNAL   tlp_state_copy      :  std_logic_vector(7 downto 0);
214 
    SIGNAL   rxtlp_data_0      :  std_logic_vector(31 downto 0);
215 
    SIGNAL   rxtlp_data_1      :  std_logic_vector(31 downto 0);
216 
    SIGNAL   rxtlp_data_2      :  std_logic_vector(31 downto 0);
217 
    SIGNAL   rxtlp_data_3      :  std_logic_vector(31 downto 0);
218 
    SIGNAL   rxtlp_data_4      :  std_logic_vector(31 downto 0);
219 
    SIGNAL   rxtlp_data_5      :  std_logic_vector(31 downto 0);
220 
    SIGNAL   rxtlp_data_6      :  std_logic_vector(31 downto 0);
221 
    SIGNAL   rxtlp_data_7      :  std_logic_vector(31 downto 0);
222 
    SIGNAL   txtlp_data_0      :  std_logic_vector(31 downto 0);
223 
    SIGNAL   txtlp_data_1      :  std_logic_vector(31 downto 0);
224 
    SIGNAL   txtlp_data_2      :  std_logic_vector(31 downto 0);
225 
    SIGNAL   txtlp_data_3      :  std_logic_vector(31 downto 0);
226 
    SIGNAL   txtlp_data_4      :  std_logic_vector(31 downto 0);
227 
    SIGNAL   txtlp_data_5      :  std_logic_vector(31 downto 0);
228 
    SIGNAL   txtlp_data_6      :  std_logic_vector(31 downto 0);
229 
    SIGNAL   txtlp_data_7      :  std_logic_vector(31 downto 0);
230 
    SIGNAL   pcie_tlp_tx_complete       :  std_logic;
231 
 
232 
         SIGNAL  pcieirq_state    :  std_logic_vector(7 downto 0);
233 
         SIGNAL  txtrn_counter   :  std_logic_vector(7 downto 0);
234 
         SIGNAL  trn_rx_counter   :  std_logic_vector(7 downto 0);
235 
         SIGNAL cfg_completer_id  :  std_logic_vector(15 downto 0);
236 
         SIGNAL wb0_state :   std_logic_vector(7 downto 0);
237 
         SIGNAL epif_tx_state :   std_logic_vector(7 downto 0);
238 
         SIGNAL epif_rx_state :   std_logic_vector(7 downto 0);
239 
         SIGNAL bit10 :   std_logic_vector(1 downto 0);
240 
 
241 
  SIGNAL bram_rxtlp_we : std_logic_vector(0 downto 0);
242 
  SIGNAL bram_rxtlp_writeaddress : std_logic_vector(31 downto 0);
243 
  SIGNAL bram_rxtlp_writedata : std_logic_vector(31 downto 0);
244 
  SIGNAL bram_rxtlp_readaddress : std_logic_vector(31 downto 0);
245 
  SIGNAL bram_rxtlp_readdata : std_logic_vector(31 downto 0);
246 
  SIGNAL bram_txtlp_we : std_logic_vector(0 downto 0);
247 
  SIGNAL bram_txtlp_writeaddress : std_logic_vector(8 downto 0);
248 
  SIGNAL bram_txtlp_writedata : std_logic_vector(31 downto 0);
249 
  SIGNAL bram_txtlp_readaddress : std_logic_vector(31 downto 0);
250 
  SIGNAL bram_txtlp_readdata : std_logic_vector(31 downto 0);
251 
 
252 
  SIGNAL tlp_datacount :   std_logic_vector(7 downto 0);
253 
  --SIGNAL bram_rxtlp_firstdata_address : std_logic_vector(8 downto 0);
254 
  SIGNAL rxtlp_header_dw1 : std_logic_vector(31 downto 0);
255 
  SIGNAL rxtlp_header_dw2 : std_logic_vector(31 downto 0);
256 
  SIGNAL rxtlp_header_dw3 : std_logic_vector(31 downto 0);
257 
  SIGNAL rxtlp_header_dw4 : std_logic_vector(31 downto 0);
258 
  SIGNAL flag1 :      std_logic;
259 
  SIGNAL rxdw1_23_0  : std_logic_vector(23 downto 0);
260 
  SIGNAL pcie_rxtlp_tag  : std_logic_vector(7 downto 0);
261 
  SIGNAL pciewb_localreset_n :      std_logic;
262 
  SIGNAL cfg_interrupt_assert_n_1 :      std_logic;
263 
  SIGNAL trn_tsrc_rdy_n_1 :      std_logic;
264 
  SIGNAL trn_tsof_n1 :      std_logic;
265 3 buenos 
  SIGNAL rcompl_bytecount_field  : std_logic_vector(9 downto 0);
266 
  SIGNAL rxstm_readytoroll :      std_logic;
267 
  SIGNAL tlpstm_isin_idle :      std_logic;
268 4 buenos 
  SIGNAL pcierx_detected :  std_logic;
269 
  SIGNAL pcierx_detect_ff_clear :  std_logic;
270 2 buenos 
 
271 
 
272 
 
273 
 
274 
        -- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
275 
 
276 
  --this is the pcie endpoint core from coregenerator.
277 
        --Core name: Xilinx Spartan-6 Integrated
278 
        --Block for PCI Express
279 
        --Version: 1.2
280 
        --Release Date: September 16, 2009. ISE DS 11.4
281 
  component pcie is
282 
  generic (
283 
    TL_TX_RAM_RADDR_LATENCY           : integer    := 0;
284 
    TL_TX_RAM_RDATA_LATENCY           : integer    := 2;
285 
    TL_RX_RAM_RADDR_LATENCY           : integer    := 0;
286 
    TL_RX_RAM_RDATA_LATENCY           : integer    := 2;
287 
    TL_RX_RAM_WRITE_LATENCY           : integer    := 0;
288 
    VC0_TX_LASTPACKET                 : integer    := 14;
289 
    VC0_RX_RAM_LIMIT                  : bit_vector := x"7FF";
290 
    VC0_TOTAL_CREDITS_PH              : integer    := 32;
291 
    VC0_TOTAL_CREDITS_PD              : integer    := 211;
292 
    VC0_TOTAL_CREDITS_NPH             : integer    := 8;
293 
    VC0_TOTAL_CREDITS_CH              : integer    := 40;
294 
    VC0_TOTAL_CREDITS_CD              : integer    := 211;
295 
    VC0_CPL_INFINITE                  : boolean    := TRUE;
296 
    BAR0                              : bit_vector := x"F0000000";
297 
    BAR1                              : bit_vector := x"00000000";
298 
    BAR2                              : bit_vector := x"00000000";
299 
    BAR3                              : bit_vector := x"00000000";
300 
    BAR4                              : bit_vector := x"00000000";
301 
    BAR5                              : bit_vector := x"00000000";
302 
    EXPANSION_ROM                     : bit_vector := "0000000000000000000000";
303 
    DISABLE_BAR_FILTERING             : boolean    := FALSE;
304 
    DISABLE_ID_CHECK                  : boolean    := FALSE;
305 
    TL_TFC_DISABLE                    : boolean    := FALSE;
306 
    TL_TX_CHECKS_DISABLE              : boolean    := FALSE;
307 
    USR_CFG                           : boolean    := FALSE;
308 
    USR_EXT_CFG                       : boolean    := FALSE;
309 
    DEV_CAP_MAX_PAYLOAD_SUPPORTED     : integer    := 2;
310 
    CLASS_CODE                        : bit_vector := x"068000";
311 
    CARDBUS_CIS_POINTER               : bit_vector := x"00000000";
312 
    PCIE_CAP_CAPABILITY_VERSION       : bit_vector := x"1";
313 
    PCIE_CAP_DEVICE_PORT_TYPE         : bit_vector := x"1";
314 
    PCIE_CAP_SLOT_IMPLEMENTED         : boolean    := FALSE;
315 
    PCIE_CAP_INT_MSG_NUM              : bit_vector := "00000";
316 
    DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer    := 0;
317 
    DEV_CAP_EXT_TAG_SUPPORTED         : boolean    := FALSE;
318 
    DEV_CAP_ENDPOINT_L0S_LATENCY      : integer    := 7;
319 
    DEV_CAP_ENDPOINT_L1_LATENCY       : integer    := 7;
320 
    SLOT_CAP_ATT_BUTTON_PRESENT       : boolean    := FALSE;
321 
    SLOT_CAP_ATT_INDICATOR_PRESENT    : boolean    := FALSE;
322 
    SLOT_CAP_POWER_INDICATOR_PRESENT  : boolean    := FALSE;
323 
    DEV_CAP_ROLE_BASED_ERROR          : boolean    := TRUE;
324 
    LINK_CAP_ASPM_SUPPORT             : integer    := 1;
325 
    LINK_CAP_L0S_EXIT_LATENCY         : integer    := 7;
326 
    LINK_CAP_L1_EXIT_LATENCY          : integer    := 7;
327 
    LL_ACK_TIMEOUT                    : bit_vector := x"0204";
328 
    LL_ACK_TIMEOUT_EN                 : boolean    := FALSE;
329 
    LL_REPLAY_TIMEOUT                 : bit_vector := x"0204";
330 
    LL_REPLAY_TIMEOUT_EN              : boolean    := FALSE;
331 
    MSI_CAP_MULTIMSGCAP               : integer    := 0;
332 
    MSI_CAP_MULTIMSG_EXTENSION        : integer    := 0;
333 
    LINK_STATUS_SLOT_CLOCK_CONFIG     : boolean    := FALSE;
334 
    PLM_AUTO_CONFIG                   : boolean    := FALSE;
335 
    FAST_TRAIN                        : boolean    := FALSE;
336 
    ENABLE_RX_TD_ECRC_TRIM            : boolean    := FALSE;
337 
    DISABLE_SCRAMBLING                : boolean    := FALSE;
338 
    PM_CAP_VERSION                    : integer    := 3;
339 
    PM_CAP_PME_CLOCK                  : boolean    := FALSE;
340 
    PM_CAP_DSI                        : boolean    := FALSE;
341 
    PM_CAP_AUXCURRENT                 : integer    := 0;
342 
    PM_CAP_D1SUPPORT                  : boolean    := TRUE;
343 
    PM_CAP_D2SUPPORT                  : boolean    := TRUE;
344 
    PM_CAP_PMESUPPORT                 : bit_vector := x"0F";
345 
    PM_DATA0                          : bit_vector := x"04";
346 
    PM_DATA_SCALE0                    : bit_vector := x"0";
347 
    PM_DATA1                          : bit_vector := x"00";
348 
    PM_DATA_SCALE1                    : bit_vector := x"0";
349 
    PM_DATA2                          : bit_vector := x"00";
350 
    PM_DATA_SCALE2                    : bit_vector := x"0";
351 
    PM_DATA3                          : bit_vector := x"00";
352 
    PM_DATA_SCALE3                    : bit_vector := x"0";
353 
    PM_DATA4                          : bit_vector := x"04";
354 
    PM_DATA_SCALE4                    : bit_vector := x"0";
355 
    PM_DATA5                          : bit_vector := x"00";
356 
    PM_DATA_SCALE5                    : bit_vector := x"0";
357 
    PM_DATA6                          : bit_vector := x"00";
358 
    PM_DATA_SCALE6                    : bit_vector := x"0";
359 
    PM_DATA7                          : bit_vector := x"00";
360 
    PM_DATA_SCALE7                    : bit_vector := x"0";
361 
    PCIE_GENERIC                      : bit_vector := "000011101111";
362 
    GTP_SEL                           : integer    := 0;
363 
    CFG_VEN_ID                        : std_logic_vector(15 downto 0) := x"10EE";
364 
    CFG_DEV_ID                        : std_logic_vector(15 downto 0) := x"ABCD";
365 
    CFG_REV_ID                        : std_logic_vector(7 downto 0)  := x"00";
366 
    CFG_SUBSYS_VEN_ID                 : std_logic_vector(15 downto 0) := x"10EE";
367 
    CFG_SUBSYS_ID                     : std_logic_vector(15 downto 0) := x"1234";
368 
    REF_CLK_FREQ                      : integer    := 0
369 
  );
370 
  port (
371 
    -- PCI Express Fabric Interface
372 
    pci_exp_txp             : out std_logic;
373 
    pci_exp_txn             : out std_logic;
374 
    pci_exp_rxp             : in  std_logic;
375 
    pci_exp_rxn             : in  std_logic;
376 
 
377 
    -- Transaction (TRN) Interface
378 
    trn_lnk_up_n            : out std_logic;
379 
 
380 
    -- Tx
381 
    trn_td                  : in  std_logic_vector(31 downto 0);
382 
    trn_tsof_n              : in  std_logic;
383 
    trn_teof_n              : in  std_logic;
384 
    trn_tsrc_rdy_n          : in  std_logic;
385 
    trn_tdst_rdy_n          : out std_logic;
386 
    trn_terr_drop_n         : out std_logic;
387 
    trn_tsrc_dsc_n          : in  std_logic;
388 
    trn_terrfwd_n           : in  std_logic;
389 
    trn_tbuf_av             : out std_logic_vector(5 downto 0);
390 
    trn_tstr_n              : in  std_logic;
391 
    trn_tcfg_req_n          : out std_logic;
392 
    trn_tcfg_gnt_n          : in  std_logic;
393 
 
394 
    -- Rx
395 
    trn_rd                  : out std_logic_vector(31 downto 0);
396 
    trn_rsof_n              : out std_logic;
397 
    trn_reof_n              : out std_logic;
398 
    trn_rsrc_rdy_n          : out std_logic;
399 
    trn_rsrc_dsc_n          : out std_logic;
400 
    trn_rdst_rdy_n          : in  std_logic;
401 
    trn_rerrfwd_n           : out std_logic;
402 
    trn_rnp_ok_n            : in  std_logic;
403 
    trn_rbar_hit_n          : out std_logic_vector(6 downto 0);
404 
    trn_fc_sel              : in  std_logic_vector(2 downto 0);
405 
    trn_fc_nph              : out std_logic_vector(7 downto 0);
406 
    trn_fc_npd              : out std_logic_vector(11 downto 0);
407 
    trn_fc_ph               : out std_logic_vector(7 downto 0);
408 
    trn_fc_pd               : out std_logic_vector(11 downto 0);
409 
    trn_fc_cplh             : out std_logic_vector(7 downto 0);
410 
    trn_fc_cpld             : out std_logic_vector(11 downto 0);
411 
 
412 
    -- Host (CFG) Interface
413 
    cfg_do                  : out std_logic_vector(31 downto 0);
414 
    cfg_rd_wr_done_n        : out std_logic;
415 
    cfg_dwaddr              : in  std_logic_vector(9 downto 0);
416 
    cfg_rd_en_n             : in  std_logic;
417 
    cfg_err_ur_n            : in  std_logic;
418 
    cfg_err_cor_n           : in  std_logic;
419 
    cfg_err_ecrc_n          : in  std_logic;
420 
    cfg_err_cpl_timeout_n   : in  std_logic;
421 
    cfg_err_cpl_abort_n     : in  std_logic;
422 
    cfg_err_posted_n        : in  std_logic;
423 
    cfg_err_locked_n        : in  std_logic;
424 
    cfg_err_tlp_cpl_header  : in  std_logic_vector(47 downto 0);
425 
    cfg_err_cpl_rdy_n       : out std_logic;
426 
    cfg_interrupt_n         : in  std_logic;
427 
    cfg_interrupt_rdy_n     : out std_logic;
428 
    cfg_interrupt_assert_n  : in  std_logic;
429 
    cfg_interrupt_do        : out std_logic_vector(7 downto 0);
430 
    cfg_interrupt_di        : in  std_logic_vector(7 downto 0);
431 
    cfg_interrupt_mmenable  : out std_logic_vector(2 downto 0);
432 
    cfg_interrupt_msienable : out std_logic;
433 
    cfg_turnoff_ok_n        : in  std_logic;
434 
    cfg_to_turnoff_n        : out std_logic;
435 
    cfg_pm_wake_n           : in  std_logic;
436 
    cfg_pcie_link_state_n   : out std_logic_vector(2 downto 0);
437 
    cfg_trn_pending_n       : in  std_logic;
438 
    cfg_dsn                 : in  std_logic_vector(63 downto 0);
439 
    cfg_bus_number          : out std_logic_vector(7 downto 0);
440 
    cfg_device_number       : out std_logic_vector(4 downto 0);
441 
    cfg_function_number     : out std_logic_vector(2 downto 0);
442 
    cfg_status              : out std_logic_vector(15 downto 0);
443 
    cfg_command             : out std_logic_vector(15 downto 0);
444 
    cfg_dstatus             : out std_logic_vector(15 downto 0);
445 
    cfg_dcommand            : out std_logic_vector(15 downto 0);
446 
    cfg_lstatus             : out std_logic_vector(15 downto 0);
447 
    cfg_lcommand            : out std_logic_vector(15 downto 0);
448 
 
449 
    -- System Interface
450 
    sys_clk                 : in  std_logic;
451 
    sys_reset_n             : in  std_logic;
452 
    trn_clk                 : out std_logic;
453 
    trn_reset_n             : out std_logic;
454 
    received_hot_reset      : out std_logic
455 
    );
456 
  end component pcie;
457 
 
458 
        COMPONENT blk_mem_gen_v4_1
459 
        PORT(
460 
                clka : IN std_logic;
461 
                wea : IN std_logic_vector(0 to 0);
462 
                addra : IN std_logic_vector(8 downto 0);
463 
                dina : IN std_logic_vector(31 downto 0);
464 
                clkb : IN std_logic;
465 
                addrb : IN std_logic_vector(8 downto 0);
466 
                doutb : OUT std_logic_vector(31 downto 0)
467 
                );
468 
        END COMPONENT;
469 
 
470 
 
471 
 
472 
---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
473 
--attribute keep_hierarchy : string;
474 
--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes";
475 
 
476 
 
477 
 
478 
-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
479 
begin
480 
 
481 
 
482 
cfg_turnoff_ok_n <= '1';
483 
 
484 
        -- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
485 
 
486 
 
487 
        -- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
488 
 
489 
  inst_pcie : pcie
490 
  port map (
491 
    pci_exp_txp             => pci_exp_txp,
492 
    pci_exp_txn             => pci_exp_txn,
493 
    pci_exp_rxp             => pci_exp_rxp,
494 
    pci_exp_rxn             => pci_exp_rxn,
495 
    trn_lnk_up_n            => trn_lnk_up_n,
496 
    trn_td                  => trn_td,                   -- Bus [31 : 0]
497 
    trn_tsof_n              => trn_tsof_n,
498 
    trn_teof_n              => trn_teof_n,
499 
    trn_tsrc_rdy_n          => trn_tsrc_rdy_n,
500 
    trn_tdst_rdy_n          => trn_tdst_rdy_n,
501 
    trn_terr_drop_n         => trn_terr_drop_n,
502 
    trn_tsrc_dsc_n          => trn_tsrc_dsc_n,
503 
    trn_terrfwd_n           => trn_terrfwd_n,
504 
    trn_tbuf_av             => trn_tbuf_av,              -- Bus [31 : 0]
505 
    trn_tstr_n              => trn_tstr_n,
506 
    trn_tcfg_req_n          => trn_tcfg_req_n,
507 
    trn_tcfg_gnt_n          => trn_tcfg_gnt_n,
508 
    trn_rd                  => trn_rd,                   -- Bus [31 : 0]
509 
    trn_rsof_n              => trn_rsof_n,
510 
    trn_reof_n              => trn_reof_n,
511 
    trn_rsrc_rdy_n          => trn_rsrc_rdy_n,
512 
    trn_rsrc_dsc_n          => trn_rsrc_dsc_n,
513 
    trn_rdst_rdy_n          => trn_rdst_rdy_n,
514 
    trn_rerrfwd_n           => trn_rerrfwd_n,
515 
    trn_rnp_ok_n            => trn_rnp_ok_n,
516 
    trn_rbar_hit_n          => trn_rbar_hit_n,           -- Bus [31 : 0]
517 
    trn_fc_sel              => trn_fc_sel,               -- Bus [31 : 0]
518 
    trn_fc_nph              => trn_fc_nph,               -- Bus [31 : 0]
519 
    trn_fc_npd              => trn_fc_npd,               -- Bus [31 : 0]
520 
    trn_fc_ph               => trn_fc_ph,                -- Bus [31 : 0]
521 
    trn_fc_pd               => trn_fc_pd,                -- Bus [31 : 0]
522 
    trn_fc_cplh             => trn_fc_cplh,              -- Bus [31 : 0]
523 
    trn_fc_cpld             => trn_fc_cpld,              -- Bus [31 : 0]
524 
    cfg_do                  => cfg_do,                   -- Bus [31 : 0]
525 
    cfg_rd_wr_done_n        => cfg_rd_wr_done_n,
526 
    cfg_dwaddr              => cfg_dwaddr,               -- Bus [31 : 0]
527 
    cfg_rd_en_n             => cfg_rd_en_n,
528 
    cfg_err_ur_n            => cfg_err_ur_n,
529 
    cfg_err_cor_n           => cfg_err_cor_n,
530 
    cfg_err_ecrc_n          => cfg_err_ecrc_n,
531 
    cfg_err_cpl_timeout_n   => cfg_err_cpl_timeout_n,
532 
    cfg_err_cpl_abort_n     => cfg_err_cpl_abort_n,
533 
    cfg_err_posted_n        => cfg_err_posted_n,
534 
    cfg_err_locked_n        => cfg_err_locked_n,
535 
    cfg_err_tlp_cpl_header  => cfg_err_tlp_cpl_header,   -- Bus [31 : 0]
536 
    cfg_err_cpl_rdy_n       => cfg_err_cpl_rdy_n,
537 
    cfg_interrupt_n         => cfg_interrupt_n,
538 
    cfg_interrupt_rdy_n     => cfg_interrupt_rdy_n,
539 
    cfg_interrupt_assert_n  => cfg_interrupt_assert_n,
540 
    cfg_interrupt_do        => cfg_interrupt_do,         -- Bus [31 : 0]
541 
    cfg_interrupt_di        => cfg_interrupt_di,         -- Bus [31 : 0]
542 
    cfg_interrupt_mmenable  => cfg_interrupt_mmenable,   -- Bus [31 : 0]
543 
    cfg_interrupt_msienable => cfg_interrupt_msienable,
544 
    cfg_turnoff_ok_n        => cfg_turnoff_ok_n,
545 
    cfg_to_turnoff_n        => cfg_to_turnoff_n,
546 
    cfg_pm_wake_n           => cfg_pm_wake_n,
547 
    cfg_pcie_link_state_n   => cfg_pcie_link_state_n,    -- Bus [31 : 0]
548 
    cfg_trn_pending_n       => cfg_trn_pending_n,
549 
    cfg_dsn                 => cfg_dsn,                  -- Bus [31 : 0]
550 
    cfg_bus_number          => cfg_bus_number,           -- Bus [31 : 0]
551 
    cfg_device_number       => cfg_device_number,        -- Bus [31 : 0]
552 
    cfg_function_number     => cfg_function_number,      -- Bus [31 : 0]
553 
    cfg_status              => cfg_status,               -- Bus [31 : 0]
554 
    cfg_command             => cfg_command,              -- Bus [31 : 0]
555 
    cfg_dstatus             => cfg_dstatus,              -- Bus [31 : 0]
556 
    cfg_dcommand            => cfg_dcommand,             -- Bus [31 : 0]
557 
    cfg_lstatus             => cfg_lstatus,              -- Bus [31 : 0]
558 
    cfg_lcommand            => cfg_lcommand,             -- Bus [31 : 0]
559 
    sys_clk                 => sys_clk,
560 
    sys_reset_n             => sys_reset_n,
561 
    trn_clk                 => trn_clk,
562 
    trn_reset_n             => trn_reset_n,
563 
    received_hot_reset      => received_hot_reset
564 
  );
565 
 
566 
        --block ram for RX TLP:
567 
        Inst_bram_rxtlp: blk_mem_gen_v4_1 PORT MAP(
568 
                clka => trn_clk,
569 
                wea => bram_rxtlp_we,
570 
                addra => bram_rxtlp_writeaddress(8 downto 0),
571 
                dina => bram_rxtlp_writedata,
572 
                clkb => trn_clk,
573 
                addrb => bram_rxtlp_readaddress(8 downto 0),
574 
                doutb => bram_rxtlp_readdata
575 
        );
576 
 
577 
        --block ram for TX TLP:
578 
        Inst_bram_txtlp: blk_mem_gen_v4_1 PORT MAP(
579 
                clka => trn_clk,
580 
                wea => bram_txtlp_we,
581 
                addra => bram_txtlp_writeaddress(8 downto 0),
582 
                dina => bram_txtlp_writedata,
583 
                clkb => trn_clk,
584 
                addrb => bram_txtlp_readaddress(8 downto 0),
585 
                doutb => bram_txtlp_readdata
586 
        );
587 
 
588 
 
589 
 
590 
 
591 
 
592 
        -- MAIN LOGIC: ---------------------------------------------------------------------------------------------
593 
 
594 
 
595 
 
596 
        --System Signals:--------------------------------
597 
 
598 
  --Clock Input Buffer for differential system clock
599 
   IBUFDS_inst : IBUFDS
600 
   generic map (
601 
      DIFF_TERM => TRUE, -- Differential Termination
602 
      IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
603 
      IOSTANDARD => "DEFAULT")
604 
   port map (
605 
      O => sys_clk,  -- Buffer output
606 
      I => sys_clk_p,  -- Diff_p buffer input (connect directly to top-level port)
607 
      IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port)
608 
   );
609 
 
610 
  --wishbone clock output:
611 
  pcie_bar0_wb_clk_o <= trn_clk;
612 
  --pcie_bar1_wb_clk_o <= trn_clk;
613 
 
614 
 
615 
  --use one of these for resetting logic in this file:
616 
    pciewb_localreset_n <= sys_reset_n; --dont wait for the PCIE-EP to finish its init.
617 
    --pciewb_localreset_n <= trn_reset_n;
618 
         --pciewb_localreset_n <= trn_reset_n and (not trn_lnk_up_n) and (not received_hot_reset);
619 
  --reset to the core:
620 
  --sys_reset_n comes from toplevel directly to the core. same name
621 
  --reset output to other cores:
622 
  pcie_resetout <= not pciewb_localreset_n;
623 
 
624 
  --trn_lnk_up_n    --not used.
625 
 
626 
 
627 
  --pcie ep ip config port: ----------------------------------------------------------
628 
 
629 
   --trn_fc_sel             <= "000";
630 
 
631 
  trn_rnp_ok_n           <= '0';
632 
  --trn_terrfwd_n          <= '1';
633 
 
634 
  --trn_tcfg_gnt_n         <= '0';
635 
 
636 
  cfg_err_cor_n          <= '1';
637 
  cfg_err_ur_n           <= '1';
638 
  cfg_err_ecrc_n         <= '1';
639 
  cfg_err_cpl_timeout_n  <= '1';
640 
  cfg_err_cpl_abort_n    <= '1';
641 
  cfg_err_posted_n       <= '0';
642 
  cfg_err_locked_n       <= '1';
643 
  cfg_pm_wake_n          <= '1';
644 
  cfg_trn_pending_n      <= '1';
645 
 
646 
  --trn_tstr_n             <= '0';
647 
  --cfg_interrupt_assert_n <= '1'; --used in a process at the bottom of this file
648 
  --cfg_interrupt_n        <= '1';
649 
  --cfg_interrupt_di       <= x"00"; --intA used
650 
 
651 
  cfg_err_tlp_cpl_header <= (OTHERS => '0');
652 
  cfg_dwaddr             <= (OTHERS => '0');
653 
  cfg_rd_en_n            <= '1';
654 
  --serial number:
655 
  cfg_dsn                <= (OTHERS => '0');
656 
 
657 
 -- AT THE BOTTOM OF THIS FILE:
658 
 --      --some fix values:
659 
 --      trn_tsrc_dsc_n <= '1'; --no errors on trn bus
660 
 --      trn_tstr_n <= '0'; --pipelining (0= link may begin before the entire packet has been written)
661 
 --      trn_tcfg_gnt_n <= '0'; --no tlp priorities
662 
 --      trn_terrfwd_n <= '1'; --no errors on trn
663 
 --      --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
664 
 
665 
 
666 
 
667 
  --use this in read completion packets:
668 
  cfg_completer_id       <= cfg_bus_number & cfg_device_number & cfg_function_number;
669 
 
670 
 
671 
 
672 
 
673 
 
674 
 
675 
        -- WISBONE BACK-end INTERFACE ----------------------------------------------------
676 
 
677 
    --main state machine: set states, capture inputs, set addr/data outputs
678 
         --minimum 2 clock cycles / transaction. writes are posted, reads have wait states.
679 
    process (pciewb_localreset_n, trn_clk, wb0_state, start_read_wb0, start_write_wb0,
680 
                                pcie_bar0_wb_addr_o_feed, pcie_bar0_wb_data_o_feed, pcie_bar0_wb_sel_o_feed)
681 
    begin
682 
    if (pciewb_localreset_n='0') then
683 
       wb0_state <= "00000000";
684 
       wb_transaction_complete <= '0';
685 
                 pcie_bar0_wb_addr_o <= "0000000000000000000000000000";
686 
                 pcie_bar0_wb_sel_o <= "0000";
687 
                 pcie_bar0_wb_data_o <= "00000000000000000000000000000000";
688 
                 wb_transaction_complete <='0';
689 
    else
690 
      if (trn_clk'event and trn_clk = '1') then
691 
                case ( wb0_state ) is
692 
 
693 
                --********** IDLE STATE  **********
694 
                when "00000000" =>   --state 0
695 
                    wb_transaction_complete <='0';
696 3 buenos 
                                                  pcie_bar0_wb_sel_o <= pcie_bar0_wb_sel_o_feed;
697 2 buenos 
                                                  pcie_bar0_wb_addr_o <= pcie_bar0_wb_addr_o_feed;
698 
                                                  if (start_read_wb0 ='1') then --go to read
699 
                                                    wb0_state <= "00000001";
700 
                                                  elsif (start_write_wb0 ='1') then --go to write
701 
                                                    wb0_state <= "00000010";
702 
                                                         --no endian swap: pcie_bar0_wb_data_o <= pcie_bar0_wb_data_o_feed;
703 
                                                    pcie_bar0_wb_data_o (7 downto 0) <= pcie_bar0_wb_data_o_feed(31 downto 24); --swap endianism
704 
                                                    pcie_bar0_wb_data_o (15 downto 8) <= pcie_bar0_wb_data_o_feed(23 downto 16); --swap endianism
705 
                                                    pcie_bar0_wb_data_o (23 downto 16) <= pcie_bar0_wb_data_o_feed(15 downto 8); --swap endianism
706 
                                                    pcie_bar0_wb_data_o (31 downto 24) <= pcie_bar0_wb_data_o_feed(7 downto 0); --swap endianism
707 
                                                  end if;
708 
 
709 
                --********** READ STATE **********
710 
                                         --set the outputs,
711 
                                         --if ACK asserted, sample the data input
712 
                                         --The hold requirements are oversatisfyed by going back to idle, and by the fact that the slave uses the cyc/stb/wr strobes synchronously.
713 
                when "00000001" =>   --state 1
714 
                    if (pcie_bar0_wb_ack_i='1') then
715 
                                                    --no endian swap: pcie_bar0_wb_data_i_latched <= pcie_bar0_wb_data_i; --sample the incoming data
716 
                                                    pcie_bar0_wb_data_i_latched (7 downto 0) <= pcie_bar0_wb_data_i(31 downto 24); --swap endianism
717 
                                                    pcie_bar0_wb_data_i_latched (15 downto 8) <= pcie_bar0_wb_data_i(23 downto 16); --swap endianism
718 
                                                    pcie_bar0_wb_data_i_latched (23 downto 16) <= pcie_bar0_wb_data_i(15 downto 8); --swap endianism
719 
                                                    pcie_bar0_wb_data_i_latched (31 downto 24) <= pcie_bar0_wb_data_i(7 downto 0); --swap endianism
720 
                                                         wb_transaction_complete <='1'; --signalling ready, but only for one clock cycle
721 
                                                         wb0_state <= "00000000"; --go to state 0
722 
                                                  else
723 
                                                         wb_transaction_complete <='0';
724 
                                                  end if;
725 
 
726 
                --********** WRITE STATE **********
727 
                                         --if ACK asserted, go back to idle
728 
                                         --The hold requirements are oversatisfyed by waiting for ACK to remove write data
729 
                when "00000010" =>   --state 2
730 
                    if (pcie_bar0_wb_ack_i='1') then
731 
                                                         wb0_state <= "00000000"; --go to state 0
732 
                                                         wb_transaction_complete <='1';
733 
                                                  else
734 
                                                     wb_transaction_complete <='0';
735 
                                                  end if;
736 
 
737 
                when others => --error
738 
                      wb0_state <= "00000000"; --go to state 0
739 
                end case;
740 
       end if;
741 
    end if;
742 
    end process;
743 
    --sync control on wb-control signals:
744 
    process (pciewb_localreset_n, wb0_state)
745 
    begin
746 
    if (pciewb_localreset_n='0') then
747 
                pcie_bar0_wb_cyc_o  <= '0';
748 
                pcie_bar0_wb_stb_o  <= '0';
749 
                pcie_bar0_wb_wr_o  <= '0';
750 
    else
751 
      if (wb0_state = "00000000") then --idle
752 
                        pcie_bar0_wb_cyc_o  <= '0';
753 
                        pcie_bar0_wb_stb_o  <= '0';
754 
                        pcie_bar0_wb_wr_o  <= '0';
755 
      elsif (wb0_state = "00000001") then --read
756 
                        pcie_bar0_wb_cyc_o  <= '1';
757 
                        pcie_bar0_wb_stb_o  <= '1';
758 
                        pcie_bar0_wb_wr_o  <= '0';
759 
      elsif (wb0_state = "00000010") then --write
760 
                        pcie_bar0_wb_cyc_o  <= '1';
761 
                        pcie_bar0_wb_stb_o  <= '1';
762 
                        pcie_bar0_wb_wr_o  <= '1';
763 
                else
764 
                        pcie_bar0_wb_cyc_o  <= '0';
765 
                        pcie_bar0_wb_stb_o  <= '0';
766 
                        pcie_bar0_wb_wr_o  <= '0';
767 
                end if;
768 
    end if;
769 
    end process;
770 
 
771 
 
772 
 
773 
 
774 
 
775 
 
776 
 
777 
 
778 
        -- INTERFACE TO THE PCIE-EP IP --------------------------------------------------------
779 
        --trn_clk and trn_reset_n are the same as the pcie_resetout and pcie_bar0_wb_clk_o,
780 
        --so it is not a clock domain crossing.
781 
 
782 
 
783 
        -- TX: INTERFACE TO THE PCIE-EP: TRANSMIT TLP PACKETS:-----
784 
        --Read completion is 3DW header. This core only transmits read completion or Unbsupported request packets.
785 
    process (pciewb_localreset_n, trn_clk, epif_tx_state, bram_txtlp_readdata , bram_txtlp_readaddress,
786 
                                pcie_there_is_a_new_tlp_to_transmit, tlp_payloadsize_dwords, txtrn_counter)
787 
    begin
788 
    if (pciewb_localreset_n='0') then
789 
      epif_tx_state <= "00000000";
790 
      trn_tsrc_rdy_n_1 <='1';
791 
                trn_tsof_n1 <= '1';
792 
                trn_teof_n <= '1';
793 
                trn_td <= (OTHERS => '0');
794 
                pcie_tlp_tx_complete <= '0';
795 
                txtrn_counter <= "00000001";
796 
                bram_txtlp_readaddress <= (OTHERS => '0');
797 
    else
798 
      if (trn_clk'event and trn_clk = '1') then
799 
                case ( epif_tx_state ) is
800 
 
801 
                --********** idle STATE  **********
802 
                when "00000000" =>   --state 0
803 
                    --if there is a new TLP assembled and the EP is ready,
804 
                                                  --start the tx-trn bus transaction.
805 
                                                  if (pcie_there_is_a_new_tlp_to_transmit='1') then
806 
                                                    epif_tx_state <= "00000001"; --next state
807 
                                                  end if;
808 
                    trn_tsrc_rdy_n_1 <='1';
809 
                                                  trn_tsof_n1 <= '1';
810 
                                                  trn_teof_n <= '1';
811 
                                                  trn_td <= (OTHERS => '0');
812 
                                                  pcie_tlp_tx_complete <= '0';
813 
                                                  txtrn_counter <= "00000001";
814 
                                                  bram_txtlp_readaddress <= (OTHERS => '0');
815 
 
816 
                --********** ready-wait STATE  **********
817 
                when "00000001" =>   --state 1
818 
                    --if there is a new TLP assembled and the EP is ready,
819 
                                                  --start the tx-trn bus transaction.
820 
                                                  if (trn_tdst_rdy_n='0') then
821 
                                                    epif_tx_state <= "00000010"; --next state
822 
                                                  end if;
823 
                    trn_tsrc_rdy_n_1 <='1';
824 
                                                  trn_tsof_n1 <= '1';
825 
                                                  trn_teof_n <= '1';
826 
                                                  trn_td <= (OTHERS => '0');
827 
                                                  pcie_tlp_tx_complete <= '0';
828 
                                                  txtrn_counter <= "00000001";
829 
                                                  bram_txtlp_readaddress <= (OTHERS => '0');
830 
 
831 
                --********** transfer STATE **********
832 
                when "00000010" =>   --state 2
833 
                    trn_tsrc_rdy_n_1 <='0';
834 
                                                  trn_td <= bram_txtlp_readdata;
835 
                                                  if (trn_tdst_rdy_n='0') then
836 
                                                    txtrn_counter <= txtrn_counter +1;
837 
                                                         bram_txtlp_readaddress <= bram_txtlp_readaddress +1;
838 
                                                  end if;
839 
                                                  if (txtrn_counter = "00000010") then
840 
                                                    trn_tsof_n1 <= '0'; --start
841 
                                                  else
842 
                                                    trn_tsof_n1 <= '1';
843 
                                                  end if;
844 
                                                  --test number of dwords:
845 
                                                  if (txtrn_counter = tlp_payloadsize_dwords +4) then -- "+3" is the header and "+1" is for the delay
846 
                                                  --this is the last dword, next clk is next state
847 
                                                         epif_tx_state <= "00000000"; --back to idle, since finished
848 
                                                    trn_teof_n <= '0'; --end
849 
                                                    pcie_tlp_tx_complete <= '1'; --assert for 1 clk
850 
                                                  else
851 
                                                    trn_teof_n <= '1'; --not end yet
852 
                                                    pcie_tlp_tx_complete <= '0'; --not complete yet
853 
                                                  end if;
854 
 
855 
                when others => --error
856 
                    epif_tx_state <= "00000000"; --back to idle
857 
                    trn_tsrc_rdy_n_1 <='1';
858 
                                                  trn_tsof_n1 <= '1';
859 
                                                  trn_teof_n <= '1';
860 
                                                  trn_td <= (OTHERS => '0');
861 
                                                  pcie_tlp_tx_complete <= '0';
862 
                                                  txtrn_counter <= "00000001";
863 
 
864 
                end case;
865 
       end if;
866 
    end if;
867 
    end process;
868 
 
869 
        --this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
870 
        trn_tsrc_rdy_n <= trn_tsrc_rdy_n_1 or (not pciewb_localreset_n);
871 
        trn_tsof_n <= trn_tsof_n1 or (not pciewb_localreset_n);
872 
 
873 
 
874 
 
875 
         --some fix values:
876 
         trn_tsrc_dsc_n <= '1'; --no errors on trn bus
877 
         trn_tstr_n <= '0'; --pipelining
878 
         trn_tcfg_gnt_n <= '0'; --no tlp priorities
879 
         trn_terrfwd_n <= '1'; --no errors on trn
880 
         --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
881 
 
882 
 
883 
 
884 
 
885 
 
886 
        -- RX: INTERFACE TO THE PCIE-EP: GET thereceived TLP PACKETS:- ----
887 3 buenos 
    process (pciewb_localreset_n, trn_clk, epif_rx_state, tlp_state, trn_rx_counter,
888 
                                bram_rxtlp_writeaddress, rxstm_readytoroll, trn_rsof_n, tlpstm_isin_idle, trn_rdst_rdy_n)
889 2 buenos 
    begin
890 
    if (pciewb_localreset_n='0') then
891 
                 pcie_just_received_a_new_tlp <= '0';
892 
                 epif_rx_state  <= "00000000";
893 
                 trn_rdst_rdy_n <= '1';
894 
                 trn_rx_counter <= (OTHERS => '0');
895 
                 bram_rxtlp_we <= "0";
896 
                 bram_rxtlp_writeaddress <= (OTHERS => '0');
897 
                 bram_rxtlp_writedata  <= (OTHERS => '0');
898 3 buenos 
                 rxstm_readytoroll <= '0';
899 2 buenos 
    else
900 
      if (trn_clk'event and trn_clk = '1') then
901 
 
902 
                case ( epif_rx_state ) is
903 
 
904 
                --********** idle STATE  **********
905 
                when "00000000" =>   --state 0
906 
                                                  pcie_just_received_a_new_tlp <= '0';
907 3 buenos 
                                                  bram_rxtlp_writedata  <= trn_rd;
908 
                                                  if (trn_rsrc_rdy_n='0' and trn_rsof_n='0' and tlpstm_isin_idle = '1' and trn_rdst_rdy_n='0') then
909 2 buenos 
                                                    trn_rx_counter <= trn_rx_counter +1;
910 
                                                         bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
911 
                                                         epif_rx_state <= "00000001";
912 
                                                  else
913 
                                                    trn_rx_counter <= (OTHERS => '0');
914 
                                                         bram_rxtlp_writeaddress  <= (OTHERS => '0');
915 3 buenos 
                                                  end if;
916 
                                                  --destination ready:
917 
                                                  if (tlpstm_isin_idle = '1')then
918 
                                                          trn_rdst_rdy_n <= '0';
919 
                                                  else
920 
                                                          trn_rdst_rdy_n <= '1';
921 
                                                  end if;
922 
                                                  --write into buffer:
923 
                                                  if (trn_rsrc_rdy_n='0' and trn_rsof_n='0' and tlpstm_isin_idle = '1') then
924 
                                                         bram_rxtlp_we <= "1";
925 
                                                         rxstm_readytoroll <= '1';
926 
                                                  else
927 2 buenos 
                                                         bram_rxtlp_we <= "0";
928 3 buenos 
                                                         rxstm_readytoroll <= '0';
929 2 buenos 
                                                  end if;
930 
 
931 
                --********** read STATE **********
932 
                when "00000001" =>   --state 1
933 3 buenos 
                                                  rxstm_readytoroll <= '0';
934 2 buenos 
                                                  if (trn_reof_n ='0') then --last dw
935 
                                                    epif_rx_state <= "00000010"; --for the next clk cycle
936 3 buenos 
                                                         trn_rdst_rdy_n <= '1'; --ok, dont send more yet
937 2 buenos 
                                                  end if;
938 
                                                  if (trn_rsrc_rdy_n='0') then --only act if the EP was ready
939 
                                                          trn_rx_counter <= trn_rx_counter +1;
940 
                                                          bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
941 
                                                          bram_rxtlp_writedata  <= trn_rd;
942 
                                                  end if;
943 
                                                  --in an early stage of this transfer, the scheduler can already
944 
                                                  --start working on the data, this way its pipelined, so the latency is lower.
945 
                                                  if (trn_rx_counter = "00000010") then
946 
                                                   pcie_just_received_a_new_tlp <= '1';--assert for one clk only
947 
                                                  else
948 
                                                   pcie_just_received_a_new_tlp <= '0';
949 
                                                  end if;
950 
 
951 
                --********** finished filling up RX TLP STATE **********
952 
                when "00000010" =>   --state 2
953 
                                                  epif_rx_state <= "00000000";
954 
                                                  trn_rx_counter <= (OTHERS => '0');
955 
 
956 
                when others => --error
957 
                      epif_rx_state <= "00000000"; --go to state 0
958 
                end case;
959 
       end if;
960 
    end if;
961 
    end process;
962 
 
963 
         --fixed connections:
964 
         --trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
965 
         --not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
966 
 
967 4 buenos 
        --RX detection flip-flop
968 
        process (pciewb_localreset_n, trn_clk)
969 
        begin
970 
        if (pciewb_localreset_n='0') then
971 
                pcierx_detected <= '0';
972 
        else
973 
                if (trn_clk'event and trn_clk = '1') then
974 
                        if (pcie_just_received_a_new_tlp ='1') then
975 
                          pcierx_detected <= '1';
976 
                        elsif (pcierx_detect_ff_clear ='1') then
977 
                          pcierx_detected <= '0';
978 
                        end if;
979 
                end if;
980 
        end if;
981 
        end process;
982 
 
983 2 buenos 
 
984 
 
985 
 
986 
        -- flow control: INTERFACE TO THE PCIE-EP: - ----
987 
        --not used. pcie-ep provides information about credit status.
988 
        --unconnected: trn_fc_nph, trn_fc_npd, trn_fc_ph, trn_fc_pd, trn_fc_cplh, trn_fc_cpld
989 
        trn_fc_sel <= "000";
990 
 
991 
 
992 
 
993 
 
994 
 
995 4 buenos 
 
996 2 buenos 
        -- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
997 
        -- --- ALSO TLP PACKET PROCESSING.
998 
        --Theory of operation:
999 
        --RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle),
1000 
        --then store it (pcie_received_tlp), decode it (to figure out if its read request,
1001 
        --posted write or non-supported request), then assert a flag (start_write_wb0 or
1002 
        --start_read_wb0)to initiate a wishbone cycle.
1003 
        --TX: At the completion of a wishbone read, the wishbone statemachine asserts the
1004 
        --wb_transaction_complete flag, so we can assemble the TX TLP packet (pcie_to_transmit_tlp)
1005 
        --and assert the flag named pcie_there_is_a_new_tlp_to_transmit. This packet will be
1006 
        --a read completion packet on the PCIe link.
1007 
        --
1008 
        --This core can handle 1...8 DWORD accesses in one request (max 256bit payload ),
1009 
        --and can handle only one request at a time. If a new request is arriving while
1010 
        --processing the previous one (e.g. getting the data from a wishbone read), then
1011 
        --the state machine will not process it immediately, or it will hang. So the user
1012 
        --software has to wait for the previous read completion before issueing a new request.
1013 
        --The multiple DWORDs are handled separately by the WB statemachine.
1014 
   --Performance: WishBone bus: 62.5MHz, 32bit, 3clk/access -> 83MBytes/sec
1015 
        --
1016 
        --TLP decoding:
1017 
        --Header+Payload_data+TLP_DIGEST(ECRC).
1018 
        --received Header:
1019 
        --First Dword: bit.30/29=format: 00=3DW-header+no_data, 01=4DW-header+no_data,
1020 
        --10=3DW-header+data, 11=4DW-header+data. bit.28:24=type: 00000 or 00001 are memory
1021 
        --read requests, 00000 or 00001 are memory write request if type=1x. read request
1022 
        --completion is 01010 and type=10. bit.9:0 is payload size [DW].
1023 
        --Second Dword: bit.31:16 is requester ID. bit3:0 is first dword byte enable, bit.7:4 is
1024 
        --byte enable for last dword data. intermediate dwords have all bytes enabled.
1025 
        --Third DWORD: address, where bit.1:0=00b. 4DW headers are for 64bit. 64bit adressing
1026 
        --uses 3rd-dword for addre63:32, 4th dword for addr31:0.
1027 
        --
1028 
        --The TLP variables in this core: BRAM memory used store TLP, up to 1-2kBytes
1029 
        --
1030 
        --Read completion is 3DW header and routed by completer-ID and requester-ID, not address.
1031 
        --The core has to store the requester ID and feed it back in the completion packet.
1032 
        --Completion status: 000=successful, 100=completer_abort, 001=unsupported request. byte
1033 
        --count is N.of bytes left. lower_address is the first enabled byte of data returned
1034 
        --with the Completion.
1035 
        --
1036 
        --  Completion packet header:
1037 
        --DW1 >
1038 
        --7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1039 
        --r FMT type----- r TC--- reserv- T E att r r lenght-------------
1040 
        --  x 0                           D P rib
1041 
        --DW2 >
1042 
        --7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1043 
        --COMPLETER_ID------------------- statu B byte_count-------------
1044 
        --                                      CM
1045 
        --DW3 >
1046 
        --7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1047 
        --REQUESTER_ID------------------- tag------------ r lower_address
1048 
 
1049 
 
1050 
         --TLP-protocol statemachine:
1051 
    process (pciewb_localreset_n, trn_clk, tlp_state,
1052 4 buenos 
                                pcierx_detected, tlp_datacount,
1053 2 buenos 
                                bram_rxtlp_readdata,  bram_txtlp_writeaddress, bram_rxtlp_readaddress,
1054 
                                tlp_state_copy, rxtlp_decodedaddress,
1055 
                                rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, rxtlp_header_dw4,
1056 
                                bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag,
1057 
                                tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id,
1058 
                                rxtlp_requesterid)
1059 
    begin
1060 
    if (pciewb_localreset_n='0') then
1061 
                start_read_wb0 <= '0';
1062 
                start_write_wb0 <= '0';
1063 
                pcie_bar0_wb_data_o_feed         <= (others => '0');
1064 
                pcie_bar0_wb_addr_o_feed <= (others => '0');
1065 
                pcie_bar0_wb_sel_o_feed  <= (others => '0');
1066 
                pcie_there_is_a_new_tlp_to_transmit  <= '0';
1067 
                rxtlp_decodedaddress<= (others => '0');
1068 
                tlp_payloadsize_dwords <= (others => '0');
1069 
                rxtlp_firstdw_be <= (others => '0');
1070 
                rxtlp_lastdw_be <= (others => '0');
1071 
                rxtlp_requesterid <= (others => '0');
1072 
                tlp_state <= (others => '0');
1073 
                tlp_state_copy  <= (others => '0');
1074 
                bram_txtlp_we <= "0";
1075 
                bram_txtlp_writeaddress    <= (others => '0');
1076 
                bram_txtlp_writedata     <= (others => '0');
1077 
                bram_rxtlp_readaddress   <= (others => '0');
1078 
                rxtlp_header_dw1   <= "01111111000000000000000000000000";
1079 
                rxtlp_header_dw2   <= (others => '0');
1080 
                rxtlp_header_dw3   <= (others => '0');
1081 
                rxtlp_header_dw4   <= (others => '0');
1082 
                flag1 <= '0';
1083 
                rxdw1_23_0 <= (others => '0');
1084 
                pcie_rxtlp_tag <= (others => '0');
1085 
                rcompl_bytecount_field  <= (others => '0');
1086 3 buenos 
                tlpstm_isin_idle <= '1';
1087 4 buenos 
                pcierx_detect_ff_clear <= '0';
1088 2 buenos 
    else
1089 
      if (trn_clk'event and trn_clk = '1') then
1090 
                case ( tlp_state ) is
1091 
 
1092 
                --********** IDLE STATE  **********
1093 
                                         --also re-initialize signals...
1094 
                when "00000000" =>   --state 0
1095 4 buenos 
                    if (pcierx_detected='1') then
1096 2 buenos 
                                                    tlp_state <= "00000001"; --to tlp decoding state
1097 3 buenos 
                                                         tlpstm_isin_idle <= '0';
1098 
                                                  else
1099 
                                                    tlpstm_isin_idle <= '1';
1100 2 buenos 
                                                  end if;
1101 
                                                  start_write_wb0 <= '0';
1102 
                                                  start_read_wb0 <= '0';
1103 
                                                  tlp_state_copy <= tlp_state;
1104 
                                                        bram_txtlp_we <= "0";
1105 
                                                        bram_txtlp_writeaddress   <= (others => '0');
1106 
                                                        bram_txtlp_writedata     <= (others => '0');
1107 
                                                        bram_rxtlp_readaddress    <= (others => '0');
1108 
                                                        tlp_datacount <= "00000001";
1109 
                                                        rxtlp_header_dw1   <= "01111111000000000000000000000000"; --this is to prevent false decode
1110 
                                                        pcie_bar0_wb_data_o_feed         <= (others => '0');
1111 
                                                        pcie_bar0_wb_addr_o_feed <= (others => '0');
1112 
                                                        pcie_bar0_wb_sel_o_feed  <= (others => '0');
1113 
                                                        rxtlp_header_dw2   <= (others => '0');
1114 
                                                        rxtlp_header_dw3   <= (others => '0');
1115 
                                                        rxtlp_header_dw4   <= (others => '0');
1116 
                                                        rxdw1_23_0 <= (others => '0');
1117 
                                                        pcie_rxtlp_tag <= (others => '0');
1118 
                                                        pcie_there_is_a_new_tlp_to_transmit  <= '0';
1119 
                                                        rxtlp_decodedaddress<= (others => '0');
1120 
                                                        tlp_payloadsize_dwords <= (others => '0');
1121 
                                                        rxtlp_firstdw_be <= (others => '0');
1122 
                                                        rxtlp_lastdw_be <= (others => '0');
1123 
                                                        rxtlp_requesterid <= (others => '0');
1124 
                                                        rcompl_bytecount_field  <= (others => '0');
1125 4 buenos 
                                                        pcierx_detect_ff_clear <= '0';
1126 2 buenos 
 
1127 
 
1128 
                --********** TLP ARRIVED STATE **********
1129 
                                         --read TLP out of EP, decode and decide,
1130 
                                         --latch address/sel/wr_data
1131 
                                         --All the "IF"-statements use address+1, because the BRAM read side has data available 1clk late!!!
1132 
                                         --Added an ectra clock delay, based on testing, since the data is one more CLK late.
1133 
                when "00000001" =>   --state 1
1134 
                    --latch the header:
1135 
                                                  bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
1136 
                                                  if (bram_rxtlp_readaddress = "000000010") then
1137 
                                                    rxtlp_header_dw1 <= bram_rxtlp_readdata;
1138 4 buenos 
                                                         pcierx_detect_ff_clear <= '1';
1139 2 buenos 
                                                  elsif (bram_rxtlp_readaddress = "000000011") then
1140 
                                                    rxtlp_header_dw2 <= bram_rxtlp_readdata;
1141 
                                                  elsif (bram_rxtlp_readaddress = "000000100") then
1142 
                                                    rxtlp_header_dw3 <= bram_rxtlp_readdata;
1143 4 buenos 
                                                         pcierx_detect_ff_clear <= '0';
1144 2 buenos 
                                                  elsif (bram_rxtlp_readaddress = "000000101") then
1145 
                                                    rxtlp_header_dw4 <= bram_rxtlp_readdata;
1146 
                                                  end if;
1147 
                                                  --decode some parameters:
1148 
                                                  tlp_payloadsize_dwords <= rxtlp_header_dw1(7 downto 0);
1149 
                                                  rxtlp_firstdw_be <= rxtlp_header_dw2(3 downto 0);
1150 
                                                  rxtlp_lastdw_be <= rxtlp_header_dw2(7 downto 4);
1151 
                                                  rxtlp_requesterid <= rxtlp_header_dw2(31 downto 16);
1152 
                                                  flag1 <= rxtlp_header_dw1(31);
1153 
                                                  rxdw1_23_0 <= rxtlp_header_dw1(23 downto 0); --various fields pcie_received_tlp (22 downto 0);
1154 
                                                  pcie_rxtlp_tag <= rxtlp_header_dw2(15 downto 8) ; --pcie_received_tlp (47 downto 40);--tag
1155 
                                                  --decide based on header:
1156 
                                                  if (rxtlp_header_dw1(30 downto 24)="0000000") then --32bit read
1157 
                                                         if (bram_rxtlp_readaddress = "000000100") then
1158 
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1159 
                                                                bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
1160 
                                                                tlp_state <= "00000011";
1161 
                                                         end if;
1162 
                                                  elsif (rxtlp_header_dw1(30 downto 24)="0100000") then --64bit read
1163 
                                                         if (bram_rxtlp_readaddress = "000000101") then
1164 
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1165 
                                                                bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
1166 
                                                                tlp_state <= "00000011";
1167 
                                                         end if;
1168 
                                                  elsif (rxtlp_header_dw1(30 downto 24)="1000000") then --32bit write
1169 
                                                         if (bram_rxtlp_readaddress = "000000100") then
1170 
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1171 
                                                                tlp_state <= "00000010";
1172 
                                                         end if;
1173 
                                                  elsif (rxtlp_header_dw1(30 downto 24)="1100000") then --64bit write
1174 
                                                         if (bram_rxtlp_readaddress = "000000101") then
1175 
                                                                rxtlp_decodedaddress <= bram_rxtlp_readdata;
1176 
                                                                tlp_state <= "00000010";
1177 
                                                         end if;
1178 
                                                  elsif (rxtlp_header_dw1(30 downto 24)="1111111") then --just wait until this gets a real value
1179 
                                                    rxtlp_decodedaddress <= bram_rxtlp_readdata;
1180 
                                                  else --unsupported request
1181 
                                                    if (bram_rxtlp_readaddress = "000000100") then
1182 
                                                           tlp_state <= "00000101";
1183 
                                                                bram_txtlp_writeaddress <= "111111111";
1184 
                                                         end if;
1185 
                                                  end if;
1186 
 
1187 
 
1188 
                --********** WRITE STATE **********
1189 
                                         --initiate WB write(s) (1...N DWORD accesses)
1190 
                when "00000010" =>   --state 2
1191 
                                                pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1; --256MBytes size is hardcoded here, by cutting 4-MSB off
1192 
                                                pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
1193 
                                                pcie_bar0_wb_sel_o_feed  <= rxtlp_firstdw_be;
1194 
                                                pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata;
1195 
                                                tlp_state_copy <= tlp_state;
1196 
                                                if (tlp_state_copy = tlp_state) then
1197 
                                                  start_write_wb0 <= '0';
1198 
                                                else --generate just one pulse, at the first clk cycle in this state
1199 
                                                  start_write_wb0 <= '1';
1200 
                                                end if;
1201 
                                                if (wb_transaction_complete='1') then --one DW transfer completed
1202 
 
1203 
                                                        if (tlp_payloadsize_dwords = tlp_datacount) then --all data completed
1204 
                                                          tlp_state <= "00000000"; --to idle
1205 
                                                        else
1206 
                                                          tlp_state <= "00010100"; --restart wb transaction with new data
1207 
                                                          bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
1208 
                                                          tlp_datacount <= tlp_datacount +1;
1209 
                                                        end if;
1210 
                                                end if;
1211 
                --* Write restart state *
1212 
                when "00010100" =>   --state 20
1213 
                                                tlp_state <= "00000010";
1214 4 buenos 
                                                tlp_state_copy <= tlp_state;
1215 2 buenos 
 
1216 
 
1217 
                --********** READ STATE **********
1218 
                                         --initiate WB read, then go to completion state
1219 
                when "00000011" =>   --state 3
1220 
                                                pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1;
1221 
                                                pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
1222 
                                                pcie_bar0_wb_sel_o_feed  <= rxtlp_firstdw_be;
1223 
                                                tlp_state_copy <= tlp_state;
1224 
                                                if (tlp_state_copy = tlp_state) then
1225 
                                                  start_read_wb0 <= '0';
1226 
                                                else --generate just one pulse
1227 
                                                  start_read_wb0 <= '1';
1228 
                                                end if;
1229 
                                                if (wb_transaction_complete='1') then
1230 
                                                        bram_txtlp_writedata <= pcie_bar0_wb_data_i_latched;
1231 
                                                        bram_txtlp_we <= "1";
1232 
                                                        if (tlp_payloadsize_dwords = tlp_datacount)then
1233 
                                                          tlp_state <= "01111110"; --read completion
1234 
                                                          --bram_txtlp_writeaddress remains the same to capture data in next clock cycle
1235 
                                                        else
1236 
                                                          tlp_state <= "00011110"; --one more wb read
1237 
                                                          bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
1238 
                                                          tlp_datacount <= tlp_datacount +1;
1239 
                                                        end if;
1240 
                                                else
1241 
                                                  bram_txtlp_we <= "0";
1242 
                                                end if;
1243 
                --* read restart STATE  *
1244 
                when "00011110" =>   --state 30
1245 
                                                tlp_state <= "00000011";
1246 
                                                bram_txtlp_we <= "0";
1247 4 buenos 
                                                tlp_state_copy <= tlp_state;
1248 2 buenos 
                --intermediate state before completion (to ensure data latch at address-4)
1249 
                                         when "01111110" =>   --state 126
1250 
                                                tlp_state <= "00000100";
1251 4 buenos 
                                                tlp_state_copy <= tlp_state;
1252 2 buenos 
                                                bram_txtlp_writeaddress  <=  (OTHERS => '0');
1253 
                                                --pre-write header-DW1:
1254 
                                                bram_txtlp_writedata (31) <= flag1; --reserved
1255 
                                                bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
1256 
                                                bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
1257 
                                                --Calculate completion header's "rcompl_bytecount_field" from rxtlp_firstdw_be, rxtlp_lastdw_be, tlp_payloadsize_dwords
1258 
                                                if (rxtlp_lastdw_be="0000") then  --max 1DW
1259 
                                                  if (rxtlp_firstdw_be="1111") then --4bytes
1260 
                                                    rcompl_bytecount_field <= "0000000100";
1261 
                                                  elsif (rxtlp_firstdw_be="0111" or rxtlp_firstdw_be="1110") then
1262 
                                                    rcompl_bytecount_field <= "0000000011";
1263 
                                                  elsif (rxtlp_firstdw_be="0011" or rxtlp_firstdw_be="1100" or rxtlp_firstdw_be="0110") then
1264 
                                                    rcompl_bytecount_field <= "0000000010";
1265 
                                                  else
1266 
                                                    rcompl_bytecount_field <= "0000000001";
1267 
                                                  end if;
1268 
                                                else --more than 1DW: right now we dont support non-aligned multi-Dword accesses
1269 
                                                  rcompl_bytecount_field(9 downto 2) <= tlp_payloadsize_dwords;
1270 
                                                  rcompl_bytecount_field(1 downto 0) <= "00";
1271 
                                                end if;
1272 
 
1273 
 
1274 
                --********** READ COMPLETION STATE **********
1275 
                                         --assemble the tx TLP and initiate the transmit
1276 
                                         --buffer signals bram_txtlp_we, bram_txtlp_writeaddress, bram_txtlp_writedata
1277 
                when "00000100" =>   --state 4
1278 
                    tlp_state_copy <= tlp_state;
1279 
                                                  bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
1280 
                                                  if (bram_txtlp_writeaddress="000000000") then --if address is 0: launch data for next lock/address(1): header-2.dw
1281 
                                                          bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
1282 
                                                          bram_txtlp_writedata (15 downto 13) <= "000"; --status= succesful***
1283 
                                                          bram_txtlp_writedata (12) <= '0'; --reserved
1284 
                                                          bram_txtlp_writedata (11 downto 10) <= "00";
1285 
                                                          bram_txtlp_writedata (9 downto 0) <= rcompl_bytecount_field; --total bytes returned
1286 
                                                          bram_txtlp_we <= "1";
1287 
                                                  elsif (bram_txtlp_writeaddress="000000001") then --if address is 1: launch data for next lock/address(2): header-3.dw
1288 
                                                          bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
1289 
                                                          bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
1290 
                                                          bram_txtlp_writedata (7) <= '0'; --reserved
1291 
                                                          bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
1292 
                                                          bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0);                   --lower address
1293 
                                                  else --data dwords, disable writes from next clock cycle
1294 
                                                    bram_txtlp_we <= "0";
1295 
                                                  end if;
1296 
                                                  --one pulse to start the ep-if statemachine, upon arriving to this state
1297 
                                                        if (tlp_state_copy = tlp_state) then
1298 
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '0';
1299 
                                                        else
1300 
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '1';
1301 
                                                        end if;
1302 
                                                        --back to idle when the ep-if tx is finished: (wait to avoid overwrite)
1303 
                                                        if (pcie_tlp_tx_complete='1') then
1304 
                                                                tlp_state <= "00000000";
1305 
                                                        end if;
1306 
 
1307 
 
1308 
                --********** UNSUPPORTED REQUEST STATE **********
1309 
                                         --completion response with status=001
1310 
                when "00000101" =>   --state 5
1311 
                    tlp_state_copy <= tlp_state;
1312 
                                                  tlp_payloadsize_dwords <= "00000000";
1313 3 buenos 
                                                  bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
1314 2 buenos 
                                                  --assembling the TLP packet:           )
1315 
                                                  if (bram_txtlp_writeaddress="111111111") then --header 1.dw
1316 
                                                    bram_txtlp_we <= "1";
1317 
                                                          bram_txtlp_writedata (31) <= flag1; --reserved
1318 
                                                          bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
1319 
                                                          bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
1320 
                                                  elsif (bram_txtlp_writeaddress="000000000") then --header 2.dw
1321 
                                                    bram_txtlp_we <= "1";
1322 
                                                          bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
1323 
                                                          bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST ***
1324 
                                                          bram_txtlp_writedata (12) <= '0'; --reserved
1325 
                                                          bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count
1326 
                                                  elsif (bram_txtlp_writeaddress="000000001") then --header 3.dw
1327 
                                                    bram_txtlp_we <= "1";
1328 
                                                          bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
1329 
                                                          bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
1330 
                                                          bram_txtlp_writedata (7) <= '0'; --reserved
1331 
                                                          bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
1332 
                                                          bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0);                   --lower address
1333 
                                                  else --data dwords
1334 
                                                    bram_txtlp_we <= "0";
1335 
                                                  end if;
1336 
                                                        --one pulse to start the ep-if statemachine, upon arriving to this state
1337 
                                                        if (tlp_state_copy = tlp_state) then
1338 
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '0';
1339 
                                                        else
1340 
                                                          pcie_there_is_a_new_tlp_to_transmit  <= '1';
1341 
                                                        end if;
1342 
                                                        --back to idle when finished:
1343 
                                                        if (pcie_tlp_tx_complete='1') then
1344 
                                                                tlp_state <= "00000000";
1345 
                                                        end if;
1346 
 
1347 
                when others => --error
1348 
                      tlp_state <= "00000000"; --go to state 0
1349 
                end case;
1350 
 
1351 
       end if;
1352 
    end if;
1353 
    end process; --end tlp statemachine
1354 
 
1355 
 
1356 
 
1357 
 
1358 
        --byte enable encoding to wb_address bit1:0
1359 3 buenos 
        --this does not swap the endian, since only the data is swapped in the pcie packets.
1360 
         process ( pciewb_localreset_n, rxtlp_firstdw_be )
1361 
    begin
1362 
       if (pciewb_localreset_n = '0') then
1363 
           bit10(1 downto 0) <="00";
1364 
       else
1365 
         if (rxtlp_firstdw_be ="0001") then
1366 
                          bit10(1 downto 0) <= "00";
1367 
         elsif (rxtlp_firstdw_be ="0010") then
1368 
                          bit10(1 downto 0) <= "01";
1369 
         elsif (rxtlp_firstdw_be ="0100") then
1370 
                          bit10(1 downto 0) <= "10";
1371 
         elsif (rxtlp_firstdw_be ="1000") then
1372 
                          bit10(1 downto 0) <= "11";
1373 
         elsif (rxtlp_firstdw_be ="0011") then
1374 
                          bit10(1 downto 0) <= "00";
1375 
         elsif (rxtlp_firstdw_be ="1100") then
1376 
                          bit10(1 downto 0) <= "10";
1377 
         elsif (rxtlp_firstdw_be ="1111") then
1378 
                          bit10(1 downto 0) <= "00";
1379 
                        else --this should never happen
1380 
                          bit10(1 downto 0) <= "00";
1381 
                        end if;
1382 
       end if;
1383 2 buenos 
    end process;
1384 
 
1385 
 
1386 
 
1387 
 
1388 
 
1389 
        -- INTERRUPTS: -------------------------------------------------------------------------
1390 
        --to assert an interrupt, use the cfg_interrupt_assert_n pin.
1391 
        --datasheet text:
1392 
        --As shown in Figure 6-30, the user application first asserts cfg_interrupt_n and
1393 
        --cfg_interrupt_assert_n to assert the interrupt. The user application should select a
1394 
        --specific interrupt (INTA, INTB, INTC, or INTD) using cfg_interrupt_di[7:0] as shown
1395 
        --in Table 6-19.
1396 
        -- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt has been accepted.
1397 
        --On the following clock cycle, the user application deasserts cfg_interrupt_n and, if the
1398 
        --Interrupt Disable bit in the PCI Command register is set to 0, the core sends an assert
1399 
        --interrupt message (Assert_INTA, Assert_INTB, and so forth).
1400 
        -- After the user application has determined that the interrupt has been serviced, it
1401 
        --asserts cfg_interrupt_n while deasserting cfg_interrupt_assert_n to deassert the
1402 
        --interrupt. The appropriate interrupt must be indicated via cfg_interrupt_di[7:0].
1403 
        -- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt deassertion has
1404 
        --been accepted. On the following clock cycle, the user application deasserts
1405 
        --cfg_interrupt_n and the core sends a deassert interrupt message (Deassert_INTA,
1406 
        --Deassert_INTB, and so forth).
1407 
        --cfg_interrupt_di[7:0] value Legacy Interrupt
1408 
        --00h INTA
1409 
        --01h INTB
1410 
        --02h INTC
1411 
        --03h INTD
1412 
 
1413 
        cfg_interrupt_di    <= "00000000"; --intA used
1414 
 
1415 
    process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
1416 
                                cfg_interrupt_rdy_n)
1417 
    begin
1418 
    if (pciewb_localreset_n='0') then
1419 
       pcieirq_state <= "00000000";
1420 
       cfg_interrupt_n <= '1';
1421 
                 cfg_interrupt_assert_n_1 <= '1';
1422 
    else
1423 
      if (trn_clk'event and trn_clk = '1') then
1424 
                case ( pcieirq_state ) is
1425 
 
1426 
                --********** idle STATE  **********
1427 
                when "00000000" =>   --state 0
1428 
                    if (pcie_irq = '1') then
1429 
                                                    pcieirq_state <= "00000001";
1430 
                                                         cfg_interrupt_n <= '0'; --active
1431 
                                                  else
1432 
                                                    cfg_interrupt_n <= '1'; --inactive
1433 
                                                  end if;
1434 
                                                  cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert
1435 
 
1436 
                --********** assert STATE **********
1437 
                when "00000001" =>   --state 1
1438 
                                                 if (cfg_interrupt_rdy_n ='0') then --ep accepted it
1439 
                                                         cfg_interrupt_n <= '1'; --deassert the request
1440 
                                                         pcieirq_state <= "00000010";
1441 
                                                 else
1442 
                                                         cfg_interrupt_n <= '0'; --request INTA assertion
1443 
                                                 end if;
1444 
 
1445 
                --********** pcie_irq kept asserted STATE **********
1446 
                when "00000010" =>   --state 2
1447 
                    if (pcie_irq = '0') then --pcie_irq gets deasserted
1448 
                                                    pcieirq_state <= "00000011";
1449 
                                                  end if;
1450 
                                                 cfg_interrupt_n <= '1'; --inactive
1451 
                                                 cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
1452 
 
1453 
                --********** DEassert STATE **********
1454 
                when "00000011" =>   --state 3
1455 
                                                 if (cfg_interrupt_rdy_n ='0') then --ep accepted it
1456 
                                                         cfg_interrupt_n <= '1'; --deassert the request
1457 
                                                         pcieirq_state <= "00000000";
1458 
                                                 else
1459 
                                                         cfg_interrupt_n <= '0'; --request INTA DEassertion
1460 
                                                 end if;
1461 
 
1462 
                                                 when others => --error
1463 
                      pcieirq_state <= "00000000"; --go to state 0
1464 
                end case;
1465 
       end if;
1466 
    end if;
1467 
    end process;
1468 
 
1469 
        --this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
1470 
        cfg_interrupt_assert_n <= cfg_interrupt_assert_n_1 or (not pciewb_localreset_n);
1471 
 
1472 
 
1473 
 
1474 
 
1475 
 
1476 
 
1477 
-- -------- END OF FILE -------------------------------------------------------------------------------------
1478 
end Behavioral;
1479 
 
1480 
 

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