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-- Project name: pcie_mini_axi4s_wb
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-- PCI-express EP to Wishbone master bridge, with AXI4S internal connection to the hard-IP.
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--
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-- This design is based on the pcie_mini project that was tested on Xilinx Spartan-6
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-- FPGAs. This new one only works on newer FPGAs that have PCIe-EP-IP with AXI4-STREAM
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-- interface, instead of the old TRN interface. For example Kintex/Virtex-7,
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-- Ultrascale and Ultrascale-plus. The user logic will be a Wishbone-bus based system.
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-- It is called "mini" because it is few lines of code, nothing to do with mini-pci form factor.
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--
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-- Engineer: Istvan Nagy, buenoshun@gmail.com
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-- Contributors (to the original pcie_mini spartan-6): Stephen Battazzo, Scott Cogan
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--
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-- Create Date: 05/30/2010
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-- Modify date: 08/10/2019
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-- Design Name: pcie_mini_axi4s_wb (entity name, top of pcie module)
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-- Version: 1.0
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-- Tool versions: Vivado 2019.1
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--
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-- Target Devices: Xilinx Series-7/usc/usc+ FPGAs. This pcie_mini_axi4s_wb no longer works on
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-- Spartan-6, due to header format change. For spartan-6 use the pcie_mini version 1.4.
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-- The original 1.4 wrapper-less pcie_mini was tested on Spartan-6 LX45T FPGA devices.
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--
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-- Project files: pcie_mini_axi4s_wb.vhd (top), pcie_axi4s2trn_wrapper.vhd, plus several
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-- Vivado-generated files that are not included on opencores, the user has to re-generate them.
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-- Either generate these IPs inside the top Vivado project, or copy the folders (with all files) over.
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-- Dependencies (vivado generated sources):
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-- 1. PCIE-EP-IP:
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-- Generate a PCIe Endpoint block IP core in the IP Catalog (used to be called The CoreGenerator).
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-- In IP catalog > Standard Bus Interfaces > PCI Express > Ultrascale+ PCI Express Integrated Block.
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-- Param: Axi-freq=125 or 62MHz, refclk=100MHz, Additional transceiver c/s ports enabled, width=x1,
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-- max payload=128bytes, set IDs, 1 mem BAR at 256MB size, BaseClass=bridge, Axisten if width = 64bit.,
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-- last tab all additional interfaces most enabled by default (except config intergface, but may need it).
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-- Also copy the generic section of the "pcie" from the file: pcie4_uscale_plus_0_pcie4_uscale_core_top.v
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-- into pcie_axi4s2trn_wrapper.vhd.
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-- Generated files/folders:
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-- ...\proj_name\proj_name.srcs\sources_1\ip\pcie4_uscale_plus_0
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-- 2. Block ram:
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-- Generate a new blockram IP core in the IP Catalog (used to be called The CoreGenerator).
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-- In IP catalog > Basic Elements > Memory Elements > Block Memory Generator.
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-- Param: Dual port block memory, type=True_dualp, a-w=32, a-depth=512, b-w=64, b-depth=256,
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-- Ena=always, common clock,
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-- Generated files/folders:
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-- ..\proj_name\proj_name.srcs\sources_1\ip\blk_mem_gen_0
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-- 3. Device and pinout. The clock buffer primitive below IBUFDS_GTE4 depends on the FPGA family.
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-- The pin assignment: When generating the core, the IP catalog wizard assigns a GT site number,
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-- likely Y225. Check that number, then look up the device/package combination in UG575, to see which
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-- pins are in that region. Then find lane-0, MGT-clokc-0 pins and assign the RX/TX/CLK signals to
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-- these pins on the "I/O Ports" view pin assignment. In case of XCU3-FFVA676: Y1,Y2,AA3,AA4,T5,T6.
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--
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-- Description:
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-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
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-- purpose of this file is to make a useable back-end interface and handle flow control
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-- for the xilinx auto-generated PCIe endpoint IP.
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-- The PCIe endpoint implements one 256MByte memory BAR (Base Address Register).
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-- This 256MBytes size is set up in the core config, and also hardcoded in this
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-- file (search for: "256MBytes").
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-- This 1 BAR is implemented as a Wishbone master interface with byte addressing,
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-- where address [x:2] shows DWORD address, while sel[3:0] decodes the 2 LSBs.
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-- ADDRESSES ARE BYTE ADDRESSES.
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-- The lower address bits are usually zero, so the slave (MCB) has to select bytes based
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-- on the byte select signals: sel[3:0]. The output address of the core contails the 2
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-- LSBs as well. The core was only tested with 32-bit accesses, byte-wide might work or not.
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-- The TLP logic is capable of handling up to 1k bytes (256 DWORDs) payload data in a
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-- single PCIe transaction, and can handle only one request at a time. If a new request
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-- is arriving while processing the previous one (e.g. getting the data from a wishbone
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-- read), then the state machine will not process it immediately, or it will hang. So
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-- the user software has to wait for the previous read completion before issueing a new
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-- request. The multiple DWORDs are handled separately by the WB statemachine.
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-- Performance: WishBone bus: 62.5MHz, 32bit, 2clk/access -> 125MBytes/sec. The maximum
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-- data throughput can be achieved when using the maximum data payload (block).
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-- The core uses INTA wirtual wire to signal interrupts.
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--
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-- x1 PCIe, legacy endpoint, uses a 100MHz ref clock.
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-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
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--
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-- Changes from the pcie_mini Spartan-6 project: works with PCIE-EP-IP that has Axi-4-stream
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-- interface instead of TRN interface, the spartan-6 32/32 blockrams replaced with ultrascale+
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-- 64/32 (width conversion) true-blockram buffers, the PCIe TLP decoding bit field
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-- replaced with axi4s header bit field decoding. 1 new file added for wrapping the PCIe-EP.
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-- Less than 32bit transfers are no longer supported, since Xilinx was so kind and replaced the
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-- PCIe TLP with this Axi4S header (descriptor) that does not have byte enables encoded in it.
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--
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-- Revision:
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-- Revision 1.0 - pcie_mini v1.5 sources copied over and header decoding logic edited.
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity pcie_mini_axi4s_wb is
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generic (
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-- BAR0_WIDTH = 28 sets address space for 2^28 bytes = 256MB, BARO = x"F0000000"
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-- BAR0_WIDTH = 22 sets address space for 2^22 bytes = 4MB, BARO = x"FFC00000"
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BAR0 : bit_vector := x"FFC00000";
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BAR0_WIDTH : integer := 22
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);
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Port ( --FPGA PINS(EXTERNAL):
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pci_exp_txp : out std_logic;
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pci_exp_txn : out std_logic;
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pci_exp_rxp : in std_logic;
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pci_exp_rxn : in std_logic;
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sys_clk_n : in std_logic;
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sys_clk_p : in std_logic;
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sys_reset_n : in std_logic;
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--ON CHIP PORTS:
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--DATA BUS for BAR0 (wishbone):
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pcie_bar0_wb_data_o : out std_logic_vector(31 downto 0);
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pcie_bar0_wb_data_i : in std_logic_vector(31 downto 0);
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pcie_bar0_wb_addr_o : out std_logic_vector(27 downto 0);
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pcie_bar0_wb_cyc_o : out std_logic;
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pcie_bar0_wb_stb_o : out std_logic;
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pcie_bar0_wb_wr_o : out std_logic;
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pcie_bar0_wb_ack_i : in std_logic;
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pcie_bar0_wb_clk_o : out std_logic; --62.5MHz
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pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0);
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--OTHER:
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pcie_irq : in std_logic;
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pcie_msi_enabled : out std_logic; -- added to monitor if MSI interrupt is enabled
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pcie_resetout : out std_logic --active high
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);
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end pcie_mini_axi4s_wb;
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architecture Behavioral of pcie_mini_axi4s_wb is
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-- Internal Signals ------------------------------------------------------------
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--SIGNAL dummy : std_logic_vector(15 downto 0); --write data bus
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SIGNAL cfg_do : std_logic_vector(31 downto 0);
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SIGNAL cfg_rd_wr_done_n : std_logic;
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SIGNAL cfg_dwaddr : std_logic_vector(9 downto 0);
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SIGNAL cfg_rd_en_n : std_logic;
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SIGNAL cfg_err_ur_n : std_logic;
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SIGNAL cfg_err_cor_n : std_logic;
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SIGNAL cfg_err_ecrc_n : std_logic;
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SIGNAL cfg_err_cpl_timeout_n : std_logic;
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SIGNAL cfg_err_cpl_abort_n : std_logic;
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SIGNAL cfg_err_posted_n : std_logic;
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SIGNAL cfg_err_locked_n : std_logic;
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SIGNAL cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
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SIGNAL cfg_err_cpl_rdy_n : std_logic;
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SIGNAL cfg_interrupt_n : std_logic;
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SIGNAL cfg_interrupt_rdy_n : std_logic;
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SIGNAL cfg_interrupt_assert_n : std_logic;
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SIGNAL cfg_interrupt_do : std_logic_vector(7 downto 0);
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SIGNAL cfg_interrupt_di : std_logic_vector(7 downto 0);
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SIGNAL cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
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SIGNAL cfg_interrupt_msienable : std_logic;
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SIGNAL cfg_turnoff_ok_n : std_logic;
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SIGNAL cfg_to_turnoff_n : std_logic;
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SIGNAL cfg_pm_wake_n : std_logic;
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SIGNAL cfg_pcie_link_state_n : std_logic_vector(2 downto 0);
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SIGNAL cfg_trn_pending_n : std_logic;
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SIGNAL cfg_dsn : std_logic_vector(63 downto 0);
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SIGNAL cfg_bus_number : std_logic_vector(7 downto 0);
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SIGNAL cfg_device_number : std_logic_vector(4 downto 0);
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SIGNAL cfg_function_number : std_logic_vector(2 downto 0);
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SIGNAL cfg_status : std_logic_vector(15 downto 0);
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SIGNAL cfg_command : std_logic_vector(15 downto 0);
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SIGNAL cfg_dstatus : std_logic_vector(15 downto 0);
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SIGNAL cfg_dcommand : std_logic_vector(15 downto 0);
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SIGNAL cfg_lstatus : std_logic_vector(15 downto 0);
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SIGNAL cfg_lcommand : std_logic_vector(15 downto 0);
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-- System Interface
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SIGNAL sys_clk : std_logic;
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SIGNAL trn_clk : std_logic;
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SIGNAL trn_reset_n : std_logic;
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SIGNAL received_hot_reset : std_logic;
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-- Transaction (TRN) Interface
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SIGNAL trn_lnk_up_n : std_logic;
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-- data interface Tx
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SIGNAL trn_td : std_logic_vector(63 downto 0);
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SIGNAL trn_tsof_n : std_logic;
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SIGNAL trn_teof_n : std_logic;
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SIGNAL trn_tsrc_rdy_n : std_logic;
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SIGNAL trn_tdst_rdy_n : std_logic;
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SIGNAL trn_terr_drop_n : std_logic;
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SIGNAL trn_tsrc_dsc_n : std_logic;
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SIGNAL trn_terrfwd_n : std_logic;
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SIGNAL trn_tbuf_av : std_logic_vector(5 downto 0);
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SIGNAL trn_tstr_n : std_logic;
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SIGNAL trn_tcfg_req_n : std_logic;
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SIGNAL trn_tcfg_gnt_n : std_logic;
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-- data interface Rx
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SIGNAL trn_rd : std_logic_vector(63 downto 0);
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SIGNAL trn_rsof_n : std_logic;
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SIGNAL trn_reof_n : std_logic;
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SIGNAL trn_rsrc_rdy_n : std_logic;
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SIGNAL trn_rsrc_dsc_n : std_logic;
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SIGNAL trn_rdst_rdy_n : std_logic;
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SIGNAL trn_rerrfwd_n : std_logic;
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SIGNAL trn_rnp_ok_n : std_logic;
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SIGNAL trn_rbar_hit_n : std_logic_vector(6 downto 0);
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-- flow control
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SIGNAL trn_fc_sel : std_logic_vector(2 downto 0);
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SIGNAL trn_fc_nph : std_logic_vector(7 downto 0);
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SIGNAL trn_fc_npd : std_logic_vector(11 downto 0);
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SIGNAL trn_fc_ph : std_logic_vector(7 downto 0);
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SIGNAL trn_fc_pd : std_logic_vector(11 downto 0);
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SIGNAL trn_fc_cplh : std_logic_vector(7 downto 0);
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SIGNAL trn_fc_cpld : std_logic_vector(11 downto 0);
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SIGNAL start_read_wb0 : std_logic;
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SIGNAL start_write_wb0 : std_logic;
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SIGNAL wb_transaction_complete : std_logic;
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SIGNAL pcie_bar0_wb_data_i_latched : std_logic_vector(31 downto 0);
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SIGNAL pcie_bar0_wb_data_o_feed : std_logic_vector(31 downto 0);
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SIGNAL pcie_bar0_wb_addr_o_feed : std_logic_vector(27 downto 0);
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SIGNAL pcie_bar0_wb_sel_o_feed : std_logic_vector(3 downto 0);
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SIGNAL start_read_wb1 : std_logic;
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SIGNAL start_write_wb1 : std_logic;
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SIGNAL rd_data_ready_wb1 : std_logic;
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SIGNAL pcie_just_received_a_new_tlp : std_logic ;
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SIGNAL pcie_start_reading_rx_tlp : std_logic ;
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SIGNAL pcie_there_is_a_new_tlp_to_transmit : std_logic ;
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SIGNAL rxtlp_decodedaddress : std_logic_vector(31 downto 0);
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SIGNAL tlp_payloadsize_dwords : std_logic_vector(7 downto 0);
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SIGNAL rxtlp_firstdw_be : std_logic_vector(3 downto 0);
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SIGNAL rxtlp_lastdw_be : std_logic_vector(3 downto 0);
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SIGNAL rxtlp_requesterid : std_logic_vector(15 downto 0);
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SIGNAL tlp_state : std_logic_vector(7 downto 0);
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SIGNAL tlp_state_copy : std_logic_vector(7 downto 0);
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SIGNAL rxtlp_data_0 : std_logic_vector(31 downto 0);
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SIGNAL rxtlp_data_1 : std_logic_vector(31 downto 0);
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SIGNAL rxtlp_data_2 : std_logic_vector(31 downto 0);
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SIGNAL rxtlp_data_3 : std_logic_vector(31 downto 0);
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SIGNAL rxtlp_data_4 : std_logic_vector(31 downto 0);
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SIGNAL rxtlp_data_5 : std_logic_vector(31 downto 0);
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SIGNAL rxtlp_data_6 : std_logic_vector(31 downto 0);
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SIGNAL rxtlp_data_7 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_0 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_1 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_2 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_3 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_4 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_5 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_6 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_7 : std_logic_vector(31 downto 0);
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SIGNAL pcie_tlp_tx_complete : std_logic;
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--this signal added by StBa, AAC Microtec
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SIGNAL irq_prohibit : std_logic;
|
| 259 |
|
|
|
| 260 |
|
|
SIGNAL pcieirq_state : std_logic_vector(2 downto 0);
|
| 261 |
|
|
SIGNAL txtrn_counter : std_logic_vector(7 downto 0);
|
| 262 |
|
|
SIGNAL trn_rx_counter : std_logic_vector(7 downto 0);
|
| 263 |
|
|
SIGNAL cfg_completer_id : std_logic_vector(15 downto 0);
|
| 264 |
|
|
SIGNAL wb0_state : std_logic_vector(7 downto 0);
|
| 265 |
|
|
SIGNAL epif_tx_state : std_logic_vector(7 downto 0);
|
| 266 |
|
|
SIGNAL epif_rx_state : std_logic_vector(7 downto 0);
|
| 267 |
|
|
SIGNAL bit10 : std_logic_vector(1 downto 0);
|
| 268 |
|
|
|
| 269 |
|
|
SIGNAL bram_rxtlp_we : std_logic_vector(0 downto 0);
|
| 270 |
|
|
SIGNAL bram_rxtlp_writeaddress : std_logic_vector(31 downto 0);
|
| 271 |
|
|
SIGNAL bram_rxtlp_writedata : std_logic_vector(63 downto 0);
|
| 272 |
|
|
SIGNAL bram_rxtlp_readaddress : std_logic_vector(31 downto 0);
|
| 273 |
|
|
SIGNAL bram_rxtlp_readdata : std_logic_vector(31 downto 0);
|
| 274 |
|
|
SIGNAL bram_txtlp_we : std_logic_vector(0 downto 0);
|
| 275 |
|
|
SIGNAL bram_txtlp_writeaddress : std_logic_vector(8 downto 0);
|
| 276 |
|
|
SIGNAL bram_txtlp_writedata : std_logic_vector(31 downto 0);
|
| 277 |
|
|
SIGNAL bram_txtlp_readaddress : std_logic_vector(31 downto 0);
|
| 278 |
|
|
SIGNAL bram_txtlp_readdata : std_logic_vector(63 downto 0);
|
| 279 |
|
|
|
| 280 |
|
|
SIGNAL tlp_datacount : std_logic_vector(7 downto 0);
|
| 281 |
|
|
--SIGNAL bram_rxtlp_firstdata_address : std_logic_vector(8 downto 0);
|
| 282 |
|
|
SIGNAL rxtlp_header_dw0 : std_logic_vector(31 downto 0);
|
| 283 |
|
|
SIGNAL rxtlp_header_dw1 : std_logic_vector(31 downto 0);
|
| 284 |
|
|
SIGNAL rxtlp_header_dw2 : std_logic_vector(31 downto 0);
|
| 285 |
|
|
SIGNAL rxtlp_header_dw3 : std_logic_vector(31 downto 0);
|
| 286 |
|
|
SIGNAL flag1 : std_logic;
|
| 287 |
|
|
SIGNAL rxdw1_23_0 : std_logic_vector(23 downto 0);
|
| 288 |
|
|
SIGNAL pcie_rxtlp_tag : std_logic_vector(7 downto 0);
|
| 289 |
|
|
SIGNAL rxtlp_attr_tc : std_logic_vector(5 downto 0);
|
| 290 |
|
|
SIGNAL rxtlp_at : std_logic_vector(1 downto 0);
|
| 291 |
|
|
SIGNAL pciewb_localreset_n : std_logic;
|
| 292 |
|
|
SIGNAL cfg_interrupt_assert_n_1 : std_logic;
|
| 293 |
|
|
SIGNAL trn_tsrc_rdy_n_1 : std_logic;
|
| 294 |
|
|
SIGNAL trn_tsof_n1 : std_logic;
|
| 295 |
|
|
SIGNAL rcompl_bytecount_field : std_logic_vector(9 downto 0);
|
| 296 |
|
|
SIGNAL rxstm_readytoroll : std_logic;
|
| 297 |
|
|
SIGNAL tlpstm_isin_idle : std_logic;
|
| 298 |
|
|
|
| 299 |
|
|
SIGNAL dummy_dina_bram : std_logic_vector(31 downto 0);
|
| 300 |
|
|
SIGNAL dummy_doutb_bram : std_logic_vector(63 downto 0);
|
| 301 |
|
|
SIGNAL dummy_douta_bram : std_logic_vector(31 downto 0);
|
| 302 |
|
|
SIGNAL dummy_dinb_bram : std_logic_vector(63 downto 0);
|
| 303 |
|
|
SIGNAL sys_clk2 : std_logic;
|
| 304 |
|
|
|
| 305 |
|
|
|
| 306 |
|
|
|
| 307 |
|
|
-- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
|
| 308 |
|
|
|
| 309 |
|
|
--this is the pcie endpoint core from coregenerator.
|
| 310 |
|
|
--Core name: Xilinx Spartan-6 Integrated
|
| 311 |
|
|
--Block for PCI Express
|
| 312 |
|
|
--Version: 1.2
|
| 313 |
|
|
--Release Date: September 16, 2009. ISE DS 11.4
|
| 314 |
|
|
component pcie is
|
| 315 |
|
|
generic (
|
| 316 |
|
|
TL_TX_RAM_RADDR_LATENCY : integer := 0;
|
| 317 |
|
|
TL_TX_RAM_RDATA_LATENCY : integer := 2;
|
| 318 |
|
|
TL_RX_RAM_RADDR_LATENCY : integer := 0;
|
| 319 |
|
|
TL_RX_RAM_RDATA_LATENCY : integer := 2;
|
| 320 |
|
|
TL_RX_RAM_WRITE_LATENCY : integer := 0;
|
| 321 |
|
|
VC0_TX_LASTPACKET : integer := 14;
|
| 322 |
|
|
VC0_RX_RAM_LIMIT : bit_vector := x"7FF";
|
| 323 |
|
|
VC0_TOTAL_CREDITS_PH : integer := 32;
|
| 324 |
|
|
VC0_TOTAL_CREDITS_PD : integer := 211;
|
| 325 |
|
|
VC0_TOTAL_CREDITS_NPH : integer := 8;
|
| 326 |
|
|
VC0_TOTAL_CREDITS_CH : integer := 40;
|
| 327 |
|
|
VC0_TOTAL_CREDITS_CD : integer := 211;
|
| 328 |
|
|
VC0_CPL_INFINITE : boolean := TRUE;
|
| 329 |
|
|
BAR0 : bit_vector := BAR0; --x"F0000000";
|
| 330 |
|
|
BAR1 : bit_vector := x"00000000";
|
| 331 |
|
|
BAR2 : bit_vector := x"00000000";
|
| 332 |
|
|
BAR3 : bit_vector := x"00000000";
|
| 333 |
|
|
BAR4 : bit_vector := x"00000000";
|
| 334 |
|
|
BAR5 : bit_vector := x"00000000";
|
| 335 |
|
|
EXPANSION_ROM : bit_vector := "0000000000000000000000";
|
| 336 |
|
|
DISABLE_BAR_FILTERING : boolean := FALSE;
|
| 337 |
|
|
DISABLE_ID_CHECK : boolean := FALSE;
|
| 338 |
|
|
TL_TFC_DISABLE : boolean := FALSE;
|
| 339 |
|
|
TL_TX_CHECKS_DISABLE : boolean := FALSE;
|
| 340 |
|
|
USR_CFG : boolean := FALSE;
|
| 341 |
|
|
USR_EXT_CFG : boolean := FALSE;
|
| 342 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
|
| 343 |
|
|
CLASS_CODE : bit_vector := x"068000";
|
| 344 |
|
|
CARDBUS_CIS_POINTER : bit_vector := x"00000000";
|
| 345 |
|
|
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1";
|
| 346 |
|
|
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"1";
|
| 347 |
|
|
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
|
| 348 |
|
|
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000";
|
| 349 |
|
|
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
|
| 350 |
|
|
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE;
|
| 351 |
|
|
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7;
|
| 352 |
|
|
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
|
| 353 |
|
|
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
|
| 354 |
|
|
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
|
| 355 |
|
|
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
|
| 356 |
|
|
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
|
| 357 |
|
|
LINK_CAP_ASPM_SUPPORT : integer := 1;
|
| 358 |
|
|
--LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
|
| 359 |
|
|
--LINK_CAP_L1_EXIT_LATENCY : integer := 7;
|
| 360 |
|
|
LL_ACK_TIMEOUT : bit_vector := x"0000";
|
| 361 |
|
|
LL_ACK_TIMEOUT_EN : boolean := FALSE;
|
| 362 |
|
|
--LL_REPLAY_TIMEOUT : bit_vector := x"0204";
|
| 363 |
|
|
LL_REPLAY_TIMEOUT : bit_vector := x"0000";
|
| 364 |
|
|
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
|
| 365 |
|
|
MSI_CAP_MULTIMSGCAP : integer := 0;
|
| 366 |
|
|
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
|
| 367 |
|
|
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
|
| 368 |
|
|
PLM_AUTO_CONFIG : boolean := FALSE;
|
| 369 |
|
|
FAST_TRAIN : boolean := FALSE;
|
| 370 |
|
|
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
|
| 371 |
|
|
DISABLE_SCRAMBLING : boolean := FALSE;
|
| 372 |
|
|
PM_CAP_VERSION : integer := 3;
|
| 373 |
|
|
PM_CAP_PME_CLOCK : boolean := FALSE;
|
| 374 |
|
|
PM_CAP_DSI : boolean := FALSE;
|
| 375 |
|
|
PM_CAP_AUXCURRENT : integer := 0;
|
| 376 |
|
|
PM_CAP_D1SUPPORT : boolean := TRUE;
|
| 377 |
|
|
PM_CAP_D2SUPPORT : boolean := TRUE;
|
| 378 |
|
|
PM_CAP_PMESUPPORT : bit_vector := x"0F";
|
| 379 |
|
|
PM_DATA0 : bit_vector := x"04";
|
| 380 |
|
|
PM_DATA_SCALE0 : bit_vector := x"0";
|
| 381 |
|
|
PM_DATA1 : bit_vector := x"00";
|
| 382 |
|
|
PM_DATA_SCALE1 : bit_vector := x"0";
|
| 383 |
|
|
PM_DATA2 : bit_vector := x"00";
|
| 384 |
|
|
PM_DATA_SCALE2 : bit_vector := x"0";
|
| 385 |
|
|
PM_DATA3 : bit_vector := x"00";
|
| 386 |
|
|
PM_DATA_SCALE3 : bit_vector := x"0";
|
| 387 |
|
|
PM_DATA4 : bit_vector := x"04";
|
| 388 |
|
|
PM_DATA_SCALE4 : bit_vector := x"0";
|
| 389 |
|
|
PM_DATA5 : bit_vector := x"00";
|
| 390 |
|
|
PM_DATA_SCALE5 : bit_vector := x"0";
|
| 391 |
|
|
PM_DATA6 : bit_vector := x"00";
|
| 392 |
|
|
PM_DATA_SCALE6 : bit_vector := x"0";
|
| 393 |
|
|
PM_DATA7 : bit_vector := x"00";
|
| 394 |
|
|
PM_DATA_SCALE7 : bit_vector := x"0";
|
| 395 |
|
|
PCIE_GENERIC : bit_vector := "000011101111";
|
| 396 |
|
|
GTP_SEL : integer := 0;
|
| 397 |
|
|
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
|
| 398 |
|
|
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"BADD";
|
| 399 |
|
|
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
|
| 400 |
|
|
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
|
| 401 |
|
|
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234";
|
| 402 |
|
|
REF_CLK_FREQ : integer := 0
|
| 403 |
|
|
);
|
| 404 |
|
|
port (
|
| 405 |
|
|
-- PCI Express Fabric Interface
|
| 406 |
|
|
pci_exp_txp : out std_logic;
|
| 407 |
|
|
pci_exp_txn : out std_logic;
|
| 408 |
|
|
pci_exp_rxp : in std_logic;
|
| 409 |
|
|
pci_exp_rxn : in std_logic;
|
| 410 |
|
|
|
| 411 |
|
|
-- Transaction (TRN) Interface
|
| 412 |
|
|
trn_lnk_up_n : out std_logic;
|
| 413 |
|
|
|
| 414 |
|
|
-- Tx
|
| 415 |
|
|
trn_td : in std_logic_vector(63 downto 0);
|
| 416 |
|
|
trn_tsof_n : in std_logic;
|
| 417 |
|
|
trn_teof_n : in std_logic;
|
| 418 |
|
|
trn_tsrc_rdy_n : in std_logic;
|
| 419 |
|
|
trn_tdst_rdy_n : out std_logic;
|
| 420 |
|
|
trn_terr_drop_n : out std_logic;
|
| 421 |
|
|
trn_tsrc_dsc_n : in std_logic;
|
| 422 |
|
|
trn_terrfwd_n : in std_logic;
|
| 423 |
|
|
trn_tbuf_av : out std_logic_vector(5 downto 0);
|
| 424 |
|
|
trn_tstr_n : in std_logic;
|
| 425 |
|
|
trn_tcfg_req_n : out std_logic;
|
| 426 |
|
|
trn_tcfg_gnt_n : in std_logic;
|
| 427 |
|
|
|
| 428 |
|
|
-- Rx
|
| 429 |
|
|
trn_rd : out std_logic_vector(63 downto 0);
|
| 430 |
|
|
trn_rsof_n : out std_logic;
|
| 431 |
|
|
trn_reof_n : out std_logic;
|
| 432 |
|
|
trn_rsrc_rdy_n : out std_logic;
|
| 433 |
|
|
trn_rsrc_dsc_n : out std_logic;
|
| 434 |
|
|
trn_rdst_rdy_n : in std_logic;
|
| 435 |
|
|
trn_rerrfwd_n : out std_logic;
|
| 436 |
|
|
trn_rnp_ok_n : in std_logic;
|
| 437 |
|
|
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
|
| 438 |
|
|
trn_fc_sel : in std_logic_vector(2 downto 0);
|
| 439 |
|
|
trn_fc_nph : out std_logic_vector(7 downto 0);
|
| 440 |
|
|
trn_fc_npd : out std_logic_vector(11 downto 0);
|
| 441 |
|
|
trn_fc_ph : out std_logic_vector(7 downto 0);
|
| 442 |
|
|
trn_fc_pd : out std_logic_vector(11 downto 0);
|
| 443 |
|
|
trn_fc_cplh : out std_logic_vector(7 downto 0);
|
| 444 |
|
|
trn_fc_cpld : out std_logic_vector(11 downto 0);
|
| 445 |
|
|
|
| 446 |
|
|
-- Host (CFG) Interface
|
| 447 |
|
|
cfg_do : out std_logic_vector(31 downto 0);
|
| 448 |
|
|
cfg_rd_wr_done_n : out std_logic;
|
| 449 |
|
|
cfg_dwaddr : in std_logic_vector(9 downto 0);
|
| 450 |
|
|
cfg_rd_en_n : in std_logic;
|
| 451 |
|
|
cfg_err_ur_n : in std_logic;
|
| 452 |
|
|
cfg_err_cor_n : in std_logic;
|
| 453 |
|
|
cfg_err_ecrc_n : in std_logic;
|
| 454 |
|
|
cfg_err_cpl_timeout_n : in std_logic;
|
| 455 |
|
|
cfg_err_cpl_abort_n : in std_logic;
|
| 456 |
|
|
cfg_err_posted_n : in std_logic;
|
| 457 |
|
|
cfg_err_locked_n : in std_logic;
|
| 458 |
|
|
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
|
| 459 |
|
|
cfg_err_cpl_rdy_n : out std_logic;
|
| 460 |
|
|
cfg_interrupt_n : in std_logic;
|
| 461 |
|
|
cfg_interrupt_rdy_n : out std_logic;
|
| 462 |
|
|
cfg_interrupt_assert_n : in std_logic;
|
| 463 |
|
|
cfg_interrupt_do : out std_logic_vector(7 downto 0);
|
| 464 |
|
|
cfg_interrupt_di : in std_logic_vector(7 downto 0);
|
| 465 |
|
|
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
|
| 466 |
|
|
cfg_interrupt_msienable : out std_logic;
|
| 467 |
|
|
cfg_turnoff_ok_n : in std_logic;
|
| 468 |
|
|
cfg_to_turnoff_n : out std_logic;
|
| 469 |
|
|
cfg_pm_wake_n : in std_logic;
|
| 470 |
|
|
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
|
| 471 |
|
|
cfg_trn_pending_n : in std_logic;
|
| 472 |
|
|
cfg_dsn : in std_logic_vector(63 downto 0);
|
| 473 |
|
|
cfg_bus_number : out std_logic_vector(7 downto 0);
|
| 474 |
|
|
cfg_device_number : out std_logic_vector(4 downto 0);
|
| 475 |
|
|
cfg_function_number : out std_logic_vector(2 downto 0);
|
| 476 |
|
|
cfg_status : out std_logic_vector(15 downto 0);
|
| 477 |
|
|
cfg_command : out std_logic_vector(15 downto 0);
|
| 478 |
|
|
cfg_dstatus : out std_logic_vector(15 downto 0);
|
| 479 |
|
|
cfg_dcommand : out std_logic_vector(15 downto 0);
|
| 480 |
|
|
cfg_lstatus : out std_logic_vector(15 downto 0);
|
| 481 |
|
|
cfg_lcommand : out std_logic_vector(15 downto 0);
|
| 482 |
|
|
|
| 483 |
|
|
-- System Interface
|
| 484 |
|
|
sys_clk : in std_logic;
|
| 485 |
|
|
sys_clk2 : in std_logic;
|
| 486 |
|
|
sys_reset_n : in std_logic;
|
| 487 |
|
|
trn_clk : out std_logic;
|
| 488 |
|
|
trn_reset_n : out std_logic;
|
| 489 |
|
|
received_hot_reset : out std_logic
|
| 490 |
|
|
);
|
| 491 |
|
|
end component pcie;
|
| 492 |
|
|
|
| 493 |
|
|
|
| 494 |
|
|
|
| 495 |
|
|
COMPONENT blk_mem_gen_0
|
| 496 |
|
|
PORT (
|
| 497 |
|
|
clka : IN STD_LOGIC;
|
| 498 |
|
|
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
| 499 |
|
|
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
| 500 |
|
|
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
| 501 |
|
|
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
| 502 |
|
|
clkb : IN STD_LOGIC;
|
| 503 |
|
|
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
| 504 |
|
|
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
| 505 |
|
|
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
| 506 |
|
|
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
|
| 507 |
|
|
);
|
| 508 |
|
|
END COMPONENT;
|
| 509 |
|
|
|
| 510 |
|
|
|
| 511 |
|
|
|
| 512 |
|
|
---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
|
| 513 |
|
|
--attribute keep_hierarchy : string;
|
| 514 |
|
|
--attribute keep_hierarchy of pcie_mini_axi4s_wb: entity is "yes";
|
| 515 |
|
|
attribute keep : string;
|
| 516 |
|
|
attribute keep of cfg_dstatus : signal is "true";
|
| 517 |
|
|
attribute keep of tlp_state : signal is "true";
|
| 518 |
|
|
|
| 519 |
|
|
|
| 520 |
|
|
-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
|
| 521 |
|
|
begin
|
| 522 |
|
|
|
| 523 |
|
|
|
| 524 |
|
|
cfg_turnoff_ok_n <= '1';
|
| 525 |
|
|
|
| 526 |
|
|
-- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
|
| 527 |
|
|
|
| 528 |
|
|
|
| 529 |
|
|
-- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------------
|
| 530 |
|
|
|
| 531 |
|
|
inst_pcie : pcie
|
| 532 |
|
|
port map (
|
| 533 |
|
|
pci_exp_txp => pci_exp_txp,
|
| 534 |
|
|
pci_exp_txn => pci_exp_txn,
|
| 535 |
|
|
pci_exp_rxp => pci_exp_rxp,
|
| 536 |
|
|
pci_exp_rxn => pci_exp_rxn,
|
| 537 |
|
|
trn_lnk_up_n => trn_lnk_up_n,
|
| 538 |
|
|
trn_td => trn_td, -- Bus [63 : 0]
|
| 539 |
|
|
trn_tsof_n => trn_tsof_n,
|
| 540 |
|
|
trn_teof_n => trn_teof_n,
|
| 541 |
|
|
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
|
| 542 |
|
|
trn_tdst_rdy_n => trn_tdst_rdy_n,
|
| 543 |
|
|
trn_terr_drop_n => trn_terr_drop_n,
|
| 544 |
|
|
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
|
| 545 |
|
|
trn_terrfwd_n => trn_terrfwd_n,
|
| 546 |
|
|
trn_tbuf_av => trn_tbuf_av, -- Bus [31 : 0]
|
| 547 |
|
|
trn_tstr_n => trn_tstr_n,
|
| 548 |
|
|
trn_tcfg_req_n => trn_tcfg_req_n,
|
| 549 |
|
|
trn_tcfg_gnt_n => trn_tcfg_gnt_n,
|
| 550 |
|
|
trn_rd => trn_rd, -- Bus [63 : 0]
|
| 551 |
|
|
trn_rsof_n => trn_rsof_n,
|
| 552 |
|
|
trn_reof_n => trn_reof_n,
|
| 553 |
|
|
trn_rsrc_rdy_n => trn_rsrc_rdy_n,
|
| 554 |
|
|
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
|
| 555 |
|
|
trn_rdst_rdy_n => trn_rdst_rdy_n,
|
| 556 |
|
|
trn_rerrfwd_n => trn_rerrfwd_n,
|
| 557 |
|
|
trn_rnp_ok_n => trn_rnp_ok_n,
|
| 558 |
|
|
trn_rbar_hit_n => trn_rbar_hit_n, -- Bus [31 : 0]
|
| 559 |
|
|
trn_fc_sel => trn_fc_sel, -- Bus [31 : 0]
|
| 560 |
|
|
trn_fc_nph => trn_fc_nph, -- Bus [31 : 0]
|
| 561 |
|
|
trn_fc_npd => trn_fc_npd, -- Bus [31 : 0]
|
| 562 |
|
|
trn_fc_ph => trn_fc_ph, -- Bus [31 : 0]
|
| 563 |
|
|
trn_fc_pd => trn_fc_pd, -- Bus [31 : 0]
|
| 564 |
|
|
trn_fc_cplh => trn_fc_cplh, -- Bus [31 : 0]
|
| 565 |
|
|
trn_fc_cpld => trn_fc_cpld, -- Bus [31 : 0]
|
| 566 |
|
|
cfg_do => cfg_do, -- Bus [31 : 0]
|
| 567 |
|
|
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
|
| 568 |
|
|
cfg_dwaddr => cfg_dwaddr, -- Bus [31 : 0]
|
| 569 |
|
|
cfg_rd_en_n => cfg_rd_en_n,
|
| 570 |
|
|
cfg_err_ur_n => cfg_err_ur_n,
|
| 571 |
|
|
cfg_err_cor_n => cfg_err_cor_n,
|
| 572 |
|
|
cfg_err_ecrc_n => cfg_err_ecrc_n,
|
| 573 |
|
|
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
|
| 574 |
|
|
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
|
| 575 |
|
|
cfg_err_posted_n => cfg_err_posted_n,
|
| 576 |
|
|
cfg_err_locked_n => cfg_err_locked_n,
|
| 577 |
|
|
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header, -- Bus [31 : 0]
|
| 578 |
|
|
cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
|
| 579 |
|
|
cfg_interrupt_n => cfg_interrupt_n,
|
| 580 |
|
|
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
|
| 581 |
|
|
cfg_interrupt_assert_n => cfg_interrupt_assert_n,
|
| 582 |
|
|
cfg_interrupt_do => cfg_interrupt_do, -- Bus [31 : 0]
|
| 583 |
|
|
cfg_interrupt_di => cfg_interrupt_di, -- Bus [31 : 0]
|
| 584 |
|
|
cfg_interrupt_mmenable => cfg_interrupt_mmenable, -- Bus [31 : 0]
|
| 585 |
|
|
cfg_interrupt_msienable => cfg_interrupt_msienable,
|
| 586 |
|
|
cfg_turnoff_ok_n => cfg_turnoff_ok_n,
|
| 587 |
|
|
cfg_to_turnoff_n => cfg_to_turnoff_n,
|
| 588 |
|
|
cfg_pm_wake_n => cfg_pm_wake_n,
|
| 589 |
|
|
cfg_pcie_link_state_n => cfg_pcie_link_state_n, -- Bus [2 : 0]
|
| 590 |
|
|
cfg_trn_pending_n => cfg_trn_pending_n,
|
| 591 |
|
|
cfg_dsn => cfg_dsn, -- Bus [31 : 0]
|
| 592 |
|
|
cfg_bus_number => cfg_bus_number, -- Bus [31 : 0]
|
| 593 |
|
|
cfg_device_number => cfg_device_number, -- Bus [31 : 0]
|
| 594 |
|
|
cfg_function_number => cfg_function_number, -- Bus [31 : 0]
|
| 595 |
|
|
cfg_status => cfg_status, -- Bus [31 : 0]
|
| 596 |
|
|
cfg_command => cfg_command, -- Bus [31 : 0]
|
| 597 |
|
|
cfg_dstatus => cfg_dstatus, -- Bus [31 : 0]
|
| 598 |
|
|
cfg_dcommand => cfg_dcommand, -- Bus [31 : 0]
|
| 599 |
|
|
cfg_lstatus => cfg_lstatus, -- Bus [31 : 0]
|
| 600 |
|
|
cfg_lcommand => cfg_lcommand, -- Bus [31 : 0]
|
| 601 |
|
|
sys_clk => sys_clk,
|
| 602 |
|
|
sys_clk2 => sys_clk2,
|
| 603 |
|
|
sys_reset_n => sys_reset_n,
|
| 604 |
|
|
trn_clk => trn_clk,
|
| 605 |
|
|
trn_reset_n => trn_reset_n,
|
| 606 |
|
|
received_hot_reset => received_hot_reset
|
| 607 |
|
|
);
|
| 608 |
|
|
|
| 609 |
|
|
|
| 610 |
|
|
|
| 611 |
|
|
--block ram for RX TLP:
|
| 612 |
|
|
Inst_bram_rxtlp: blk_mem_gen_0
|
| 613 |
|
|
PORT MAP (
|
| 614 |
|
|
-- 32bit user side port:
|
| 615 |
|
|
clka => trn_clk,
|
| 616 |
|
|
wea => "0",
|
| 617 |
|
|
addra => bram_rxtlp_readaddress(8 downto 0),
|
| 618 |
|
|
dina => dummy_dina_bram,
|
| 619 |
|
|
douta => bram_rxtlp_readdata,
|
| 620 |
|
|
-- 64bit PCIe side port:
|
| 621 |
|
|
clkb => trn_clk,
|
| 622 |
|
|
web => bram_rxtlp_we,
|
| 623 |
|
|
addrb => bram_rxtlp_writeaddress(7 downto 0),
|
| 624 |
|
|
dinb => bram_rxtlp_writedata,
|
| 625 |
|
|
doutb => dummy_doutb_bram
|
| 626 |
|
|
);
|
| 627 |
|
|
|
| 628 |
|
|
--block ram for TX TLP:
|
| 629 |
|
|
Inst_bram_txtlp: blk_mem_gen_0
|
| 630 |
|
|
PORT MAP (
|
| 631 |
|
|
-- 32bit user side port:
|
| 632 |
|
|
clka => trn_clk,
|
| 633 |
|
|
wea => bram_txtlp_we,
|
| 634 |
|
|
addra => bram_txtlp_writeaddress(8 downto 0),
|
| 635 |
|
|
dina => bram_txtlp_writedata,
|
| 636 |
|
|
douta => dummy_douta_bram,
|
| 637 |
|
|
-- 64bit PCIe side port:
|
| 638 |
|
|
clkb => trn_clk,
|
| 639 |
|
|
web => "0",
|
| 640 |
|
|
addrb => bram_txtlp_readaddress(7 downto 0),
|
| 641 |
|
|
dinb => dummy_dinb_bram,
|
| 642 |
|
|
doutb => bram_txtlp_readdata
|
| 643 |
|
|
);
|
| 644 |
|
|
|
| 645 |
|
|
|
| 646 |
|
|
|
| 647 |
|
|
-- MAIN LOGIC: ---------------------------------------------------------------------------------------------
|
| 648 |
|
|
|
| 649 |
|
|
dummy_dina_bram <= (OTHERS => '0');
|
| 650 |
|
|
dummy_dinb_bram <= (OTHERS => '0');
|
| 651 |
|
|
|
| 652 |
|
|
--System Signals:--------------------------------
|
| 653 |
|
|
|
| 654 |
|
|
--Clock Input Buffer for differential system clock
|
| 655 |
|
|
--IBUFDS_GTE3/4 is the gigabit transceiver input pad buffer component. The REFCLK signal should be routed to the dedicated referenceclock input pins
|
| 656 |
|
|
--on the serial transceiver, and the user design should instantiate the IBUFDS_GTE3 primitive in the user design.
|
| 657 |
|
|
IBUFDS_inst : IBUFDS_GTE4 --IBUFDS_GTE3 for Ultrascale (use ODIV2), GTE4 for ultrascale+ (use ODIV2), GTE2 for Virtex7 (swap O with ODIV2)
|
| 658 |
|
|
generic map (
|
| 659 |
|
|
REFCLK_EN_TX_PATH => '0',
|
| 660 |
|
|
REFCLK_HROW_CK_SEL => "00",
|
| 661 |
|
|
REFCLK_ICNTL_RX => "00")
|
| 662 |
|
|
port map (
|
| 663 |
|
|
O => sys_clk2, -- Buffer output 1 (use on Virtex 7 only)
|
| 664 |
|
|
I => sys_clk_p, -- Diff_p buffer input (connect directly to top-level port)
|
| 665 |
|
|
CEB => '0',
|
| 666 |
|
|
ODIV2 => sys_clk, --Buffer output 2 (use on ultrascale/+)
|
| 667 |
|
|
IB => sys_clk_n -- Diff_n buffer input (connect directly to top-level port)
|
| 668 |
|
|
);
|
| 669 |
|
|
|
| 670 |
|
|
--wishbone clock output:
|
| 671 |
|
|
pcie_bar0_wb_clk_o <= trn_clk;
|
| 672 |
|
|
--pcie_bar1_wb_clk_o <= trn_clk;
|
| 673 |
|
|
|
| 674 |
|
|
|
| 675 |
|
|
--use one of these for resetting logic in this file:
|
| 676 |
|
|
pciewb_localreset_n <= sys_reset_n; --dont wait for the PCIE-EP to finish its init.
|
| 677 |
|
|
--pciewb_localreset_n <= trn_reset_n;
|
| 678 |
|
|
--pciewb_localreset_n <= trn_reset_n and (not trn_lnk_up_n) and (not received_hot_reset);
|
| 679 |
|
|
--reset to the core:
|
| 680 |
|
|
--sys_reset_n comes from toplevel directly to the core. same name
|
| 681 |
|
|
--reset output to other cores:
|
| 682 |
|
|
pcie_resetout <= not pciewb_localreset_n;
|
| 683 |
|
|
|
| 684 |
|
|
--trn_lnk_up_n --not used.
|
| 685 |
|
|
|
| 686 |
|
|
|
| 687 |
|
|
--pcie ep ip config port: ----------------------------------------------------------
|
| 688 |
|
|
|
| 689 |
|
|
--trn_fc_sel <= "000";
|
| 690 |
|
|
|
| 691 |
|
|
trn_rnp_ok_n <= '0';
|
| 692 |
|
|
--trn_terrfwd_n <= '1';
|
| 693 |
|
|
|
| 694 |
|
|
--trn_tcfg_gnt_n <= '0';
|
| 695 |
|
|
|
| 696 |
|
|
cfg_err_cor_n <= '1';
|
| 697 |
|
|
cfg_err_ur_n <= '1';
|
| 698 |
|
|
cfg_err_ecrc_n <= '1';
|
| 699 |
|
|
cfg_err_cpl_timeout_n <= '1';
|
| 700 |
|
|
cfg_err_cpl_abort_n <= '1';
|
| 701 |
|
|
cfg_err_posted_n <= '0';
|
| 702 |
|
|
cfg_err_locked_n <= '1';
|
| 703 |
|
|
cfg_pm_wake_n <= '1';
|
| 704 |
|
|
cfg_trn_pending_n <= '1';
|
| 705 |
|
|
|
| 706 |
|
|
--trn_tstr_n <= '0';
|
| 707 |
|
|
--cfg_interrupt_assert_n <= '1'; --used in a process at the bottom of this file
|
| 708 |
|
|
--cfg_interrupt_n <= '1';
|
| 709 |
|
|
--cfg_interrupt_di <= x"00"; --intA used
|
| 710 |
|
|
|
| 711 |
|
|
cfg_err_tlp_cpl_header <= (OTHERS => '0');
|
| 712 |
|
|
cfg_dwaddr <= (OTHERS => '0');
|
| 713 |
|
|
cfg_rd_en_n <= '1';
|
| 714 |
|
|
--serial number:
|
| 715 |
|
|
cfg_dsn <= (OTHERS => '0');
|
| 716 |
|
|
|
| 717 |
|
|
-- AT THE BOTTOM OF THIS FILE:
|
| 718 |
|
|
-- --some fix values:
|
| 719 |
|
|
-- trn_tsrc_dsc_n <= '1'; --no errors on trn bus
|
| 720 |
|
|
-- trn_tstr_n <= '0'; --pipelining (0= link may begin before the entire packet has been written)
|
| 721 |
|
|
-- trn_tcfg_gnt_n <= '0'; --no tlp priorities
|
| 722 |
|
|
-- trn_terrfwd_n <= '1'; --no errors on trn
|
| 723 |
|
|
-- --nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
|
| 724 |
|
|
|
| 725 |
|
|
|
| 726 |
|
|
|
| 727 |
|
|
--use this in read completion packets:
|
| 728 |
|
|
cfg_completer_id <= cfg_bus_number & cfg_device_number & cfg_function_number;
|
| 729 |
|
|
|
| 730 |
|
|
|
| 731 |
|
|
|
| 732 |
|
|
|
| 733 |
|
|
|
| 734 |
|
|
|
| 735 |
|
|
-- WISBONE BACK-end INTERFACE ----------------------------------------------------
|
| 736 |
|
|
|
| 737 |
|
|
--main state machine: set states, capture inputs, set addr/data outputs
|
| 738 |
|
|
--minimum 2 clock cycles / transaction. writes are posted, reads have wait states.
|
| 739 |
|
|
process (pciewb_localreset_n, trn_clk, wb0_state, start_read_wb0, start_write_wb0,
|
| 740 |
|
|
pcie_bar0_wb_addr_o_feed, pcie_bar0_wb_data_o_feed, pcie_bar0_wb_sel_o_feed)
|
| 741 |
|
|
begin
|
| 742 |
|
|
if (pciewb_localreset_n='0') then
|
| 743 |
|
|
wb0_state <= "00000000";
|
| 744 |
|
|
wb_transaction_complete <= '0';
|
| 745 |
|
|
pcie_bar0_wb_addr_o <= "0000000000000000000000000000";
|
| 746 |
|
|
pcie_bar0_wb_sel_o <= "0000";
|
| 747 |
|
|
pcie_bar0_wb_data_o <= "00000000000000000000000000000000";
|
| 748 |
|
|
wb_transaction_complete <='0';
|
| 749 |
|
|
else
|
| 750 |
|
|
if (trn_clk'event and trn_clk = '1') then
|
| 751 |
|
|
case ( wb0_state ) is
|
| 752 |
|
|
|
| 753 |
|
|
--********** IDLE STATE **********
|
| 754 |
|
|
when "00000000" => --state 0
|
| 755 |
|
|
wb_transaction_complete <='0';
|
| 756 |
|
|
pcie_bar0_wb_sel_o <= pcie_bar0_wb_sel_o_feed;
|
| 757 |
|
|
pcie_bar0_wb_addr_o <= pcie_bar0_wb_addr_o_feed;
|
| 758 |
|
|
if (start_read_wb0 ='1') then --go to read
|
| 759 |
|
|
wb0_state <= "00000001";
|
| 760 |
|
|
elsif (start_write_wb0 ='1') then --go to write
|
| 761 |
|
|
wb0_state <= "00000010";
|
| 762 |
|
|
--no endian swap: pcie_bar0_wb_data_o <= pcie_bar0_wb_data_o_feed;
|
| 763 |
|
|
pcie_bar0_wb_data_o (7 downto 0) <= pcie_bar0_wb_data_o_feed(31 downto 24); --swap endianism
|
| 764 |
|
|
pcie_bar0_wb_data_o (15 downto 8) <= pcie_bar0_wb_data_o_feed(23 downto 16); --swap endianism
|
| 765 |
|
|
pcie_bar0_wb_data_o (23 downto 16) <= pcie_bar0_wb_data_o_feed(15 downto 8); --swap endianism
|
| 766 |
|
|
pcie_bar0_wb_data_o (31 downto 24) <= pcie_bar0_wb_data_o_feed(7 downto 0); --swap endianism
|
| 767 |
|
|
end if;
|
| 768 |
|
|
|
| 769 |
|
|
--********** READ STATE **********
|
| 770 |
|
|
--set the outputs,
|
| 771 |
|
|
--if ACK asserted, sample the data input
|
| 772 |
|
|
--The hold requirements are oversatisfyed by going back to idle, and by the fact that the slave uses the cyc/stb/wr strobes synchronously.
|
| 773 |
|
|
when "00000001" => --state 1
|
| 774 |
|
|
if (pcie_bar0_wb_ack_i='1') then
|
| 775 |
|
|
--no endian swap: pcie_bar0_wb_data_i_latched <= pcie_bar0_wb_data_i; --sample the incoming data
|
| 776 |
|
|
pcie_bar0_wb_data_i_latched (7 downto 0) <= pcie_bar0_wb_data_i(31 downto 24); --swap endianism
|
| 777 |
|
|
pcie_bar0_wb_data_i_latched (15 downto 8) <= pcie_bar0_wb_data_i(23 downto 16); --swap endianism
|
| 778 |
|
|
pcie_bar0_wb_data_i_latched (23 downto 16) <= pcie_bar0_wb_data_i(15 downto 8); --swap endianism
|
| 779 |
|
|
pcie_bar0_wb_data_i_latched (31 downto 24) <= pcie_bar0_wb_data_i(7 downto 0); --swap endianism
|
| 780 |
|
|
wb_transaction_complete <='1'; --signalling ready, but only for one clock cycle
|
| 781 |
|
|
wb0_state <= "00000000"; --go to state 0
|
| 782 |
|
|
else
|
| 783 |
|
|
wb_transaction_complete <='0';
|
| 784 |
|
|
end if;
|
| 785 |
|
|
|
| 786 |
|
|
--********** WRITE STATE **********
|
| 787 |
|
|
--if ACK asserted, go back to idle
|
| 788 |
|
|
--The hold requirements are oversatisfyed by waiting for ACK to remove write data
|
| 789 |
|
|
when "00000010" => --state 2
|
| 790 |
|
|
if (pcie_bar0_wb_ack_i='1') then
|
| 791 |
|
|
wb0_state <= "00000000"; --go to state 0
|
| 792 |
|
|
wb_transaction_complete <='1';
|
| 793 |
|
|
else
|
| 794 |
|
|
wb_transaction_complete <='0';
|
| 795 |
|
|
end if;
|
| 796 |
|
|
|
| 797 |
|
|
when others => --error
|
| 798 |
|
|
wb0_state <= "00000000"; --go to state 0
|
| 799 |
|
|
end case;
|
| 800 |
|
|
end if;
|
| 801 |
|
|
end if;
|
| 802 |
|
|
end process;
|
| 803 |
|
|
--sync control on wb-control signals:
|
| 804 |
|
|
process (pciewb_localreset_n, wb0_state)
|
| 805 |
|
|
begin
|
| 806 |
|
|
if (pciewb_localreset_n='0') then
|
| 807 |
|
|
pcie_bar0_wb_cyc_o <= '0';
|
| 808 |
|
|
pcie_bar0_wb_stb_o <= '0';
|
| 809 |
|
|
pcie_bar0_wb_wr_o <= '0';
|
| 810 |
|
|
else
|
| 811 |
|
|
if (wb0_state = "00000000") then --idle
|
| 812 |
|
|
pcie_bar0_wb_cyc_o <= '0';
|
| 813 |
|
|
pcie_bar0_wb_stb_o <= '0';
|
| 814 |
|
|
pcie_bar0_wb_wr_o <= '0';
|
| 815 |
|
|
elsif (wb0_state = "00000001") then --read
|
| 816 |
|
|
pcie_bar0_wb_cyc_o <= '1';
|
| 817 |
|
|
pcie_bar0_wb_stb_o <= '1';
|
| 818 |
|
|
pcie_bar0_wb_wr_o <= '0';
|
| 819 |
|
|
elsif (wb0_state = "00000010") then --write
|
| 820 |
|
|
pcie_bar0_wb_cyc_o <= '1';
|
| 821 |
|
|
pcie_bar0_wb_stb_o <= '1';
|
| 822 |
|
|
pcie_bar0_wb_wr_o <= '1';
|
| 823 |
|
|
else
|
| 824 |
|
|
pcie_bar0_wb_cyc_o <= '0';
|
| 825 |
|
|
pcie_bar0_wb_stb_o <= '0';
|
| 826 |
|
|
pcie_bar0_wb_wr_o <= '0';
|
| 827 |
|
|
end if;
|
| 828 |
|
|
end if;
|
| 829 |
|
|
end process;
|
| 830 |
|
|
|
| 831 |
|
|
|
| 832 |
|
|
|
| 833 |
|
|
|
| 834 |
|
|
|
| 835 |
|
|
|
| 836 |
|
|
|
| 837 |
|
|
|
| 838 |
|
|
-- INTERFACE TO THE PCIE-EP IP --------------------------------------------------------
|
| 839 |
|
|
--trn_clk and trn_reset_n are the same as the pcie_resetout and pcie_bar0_wb_clk_o,
|
| 840 |
|
|
--so it is not a clock domain crossing.
|
| 841 |
|
|
|
| 842 |
|
|
|
| 843 |
|
|
-- TX: INTERFACE TO THE PCIE-EP: TRANSMIT TLP PACKETS:-----
|
| 844 |
|
|
--Read completion is 3DW header. This core only transmits read completion or Unbsupported request packets.
|
| 845 |
|
|
process (pciewb_localreset_n, trn_clk, epif_tx_state, bram_txtlp_readdata , bram_txtlp_readaddress,
|
| 846 |
|
|
pcie_there_is_a_new_tlp_to_transmit, tlp_payloadsize_dwords, txtrn_counter)
|
| 847 |
|
|
begin
|
| 848 |
|
|
if (pciewb_localreset_n='0') then
|
| 849 |
|
|
epif_tx_state <= "00000000";
|
| 850 |
|
|
trn_tsrc_rdy_n_1 <='1';
|
| 851 |
|
|
trn_tsof_n1 <= '1';
|
| 852 |
|
|
trn_teof_n <= '1';
|
| 853 |
|
|
trn_td <= (OTHERS => '0');
|
| 854 |
|
|
pcie_tlp_tx_complete <= '0';
|
| 855 |
|
|
txtrn_counter <= "00000001";
|
| 856 |
|
|
bram_txtlp_readaddress <= (OTHERS => '0');
|
| 857 |
|
|
else
|
| 858 |
|
|
if (trn_clk'event and trn_clk = '1') then
|
| 859 |
|
|
case ( epif_tx_state ) is
|
| 860 |
|
|
|
| 861 |
|
|
--********** idle STATE **********
|
| 862 |
|
|
when "00000000" => --state 0
|
| 863 |
|
|
--if there is a new TLP assembled and the EP is ready,
|
| 864 |
|
|
--start the tx-trn bus transaction.
|
| 865 |
|
|
if (pcie_there_is_a_new_tlp_to_transmit='1') then
|
| 866 |
|
|
epif_tx_state <= "00000001"; --next state
|
| 867 |
|
|
end if;
|
| 868 |
|
|
trn_tsrc_rdy_n_1 <='1';
|
| 869 |
|
|
trn_tsof_n1 <= '1';
|
| 870 |
|
|
trn_teof_n <= '1';
|
| 871 |
|
|
trn_td <= (OTHERS => '0');
|
| 872 |
|
|
pcie_tlp_tx_complete <= '0';
|
| 873 |
|
|
txtrn_counter <= "00000001";
|
| 874 |
|
|
bram_txtlp_readaddress <= (OTHERS => '0');
|
| 875 |
|
|
|
| 876 |
|
|
--********** ready-wait STATE **********
|
| 877 |
|
|
when "00000001" => --state 1
|
| 878 |
|
|
--if there is a new TLP assembled and the EP is ready,
|
| 879 |
|
|
--start the tx-trn bus transaction.
|
| 880 |
|
|
if (trn_tdst_rdy_n='0') then
|
| 881 |
|
|
epif_tx_state <= "00000010"; --next state
|
| 882 |
|
|
end if;
|
| 883 |
|
|
trn_tsrc_rdy_n_1 <='1';
|
| 884 |
|
|
trn_tsof_n1 <= '1';
|
| 885 |
|
|
trn_teof_n <= '1';
|
| 886 |
|
|
trn_td <= (OTHERS => '0');
|
| 887 |
|
|
pcie_tlp_tx_complete <= '0';
|
| 888 |
|
|
txtrn_counter <= "00000001";
|
| 889 |
|
|
bram_txtlp_readaddress <= (OTHERS => '0');
|
| 890 |
|
|
|
| 891 |
|
|
--********** transfer STATE **********
|
| 892 |
|
|
when "00000010" => --state 2
|
| 893 |
|
|
trn_tsrc_rdy_n_1 <='0';
|
| 894 |
|
|
trn_td <= bram_txtlp_readdata;
|
| 895 |
|
|
if (trn_tdst_rdy_n='0') then
|
| 896 |
|
|
txtrn_counter <= txtrn_counter +1;
|
| 897 |
|
|
bram_txtlp_readaddress <= bram_txtlp_readaddress +1;
|
| 898 |
|
|
end if;
|
| 899 |
|
|
if (txtrn_counter = "00000010") then
|
| 900 |
|
|
trn_tsof_n1 <= '0'; --start
|
| 901 |
|
|
else
|
| 902 |
|
|
trn_tsof_n1 <= '1';
|
| 903 |
|
|
end if;
|
| 904 |
|
|
--test number of dwords:
|
| 905 |
|
|
if (txtrn_counter = tlp_payloadsize_dwords +4) then -- "+3" is the header and "+1" is for the delay
|
| 906 |
|
|
--this is the last dword, next clk is next state
|
| 907 |
|
|
epif_tx_state <= "00000000"; --back to idle, since finished
|
| 908 |
|
|
trn_teof_n <= '0'; --end
|
| 909 |
|
|
pcie_tlp_tx_complete <= '1'; --assert for 1 clk
|
| 910 |
|
|
else
|
| 911 |
|
|
trn_teof_n <= '1'; --not end yet
|
| 912 |
|
|
pcie_tlp_tx_complete <= '0'; --not complete yet
|
| 913 |
|
|
end if;
|
| 914 |
|
|
|
| 915 |
|
|
when others => --error
|
| 916 |
|
|
epif_tx_state <= "00000000"; --back to idle
|
| 917 |
|
|
trn_tsrc_rdy_n_1 <='1';
|
| 918 |
|
|
trn_tsof_n1 <= '1';
|
| 919 |
|
|
trn_teof_n <= '1';
|
| 920 |
|
|
trn_td <= (OTHERS => '0');
|
| 921 |
|
|
pcie_tlp_tx_complete <= '0';
|
| 922 |
|
|
txtrn_counter <= "00000001";
|
| 923 |
|
|
|
| 924 |
|
|
end case;
|
| 925 |
|
|
end if;
|
| 926 |
|
|
end if;
|
| 927 |
|
|
end process;
|
| 928 |
|
|
|
| 929 |
|
|
--this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
|
| 930 |
|
|
trn_tsrc_rdy_n <= trn_tsrc_rdy_n_1 or (not pciewb_localreset_n);
|
| 931 |
|
|
trn_tsof_n <= trn_tsof_n1 or (not pciewb_localreset_n);
|
| 932 |
|
|
|
| 933 |
|
|
|
| 934 |
|
|
|
| 935 |
|
|
--some fix values:
|
| 936 |
|
|
trn_tsrc_dsc_n <= '1'; --no errors on trn bus
|
| 937 |
|
|
trn_tstr_n <= '0'; --pipelining
|
| 938 |
|
|
trn_tcfg_gnt_n <= '0'; --no tlp priorities
|
| 939 |
|
|
trn_terrfwd_n <= '1'; --no errors on trn
|
| 940 |
|
|
--nc: trn_tbuf_av, trn_terr_drop_n, trn_tcfg_req_n
|
| 941 |
|
|
|
| 942 |
|
|
|
| 943 |
|
|
|
| 944 |
|
|
|
| 945 |
|
|
|
| 946 |
|
|
-- RX: INTERFACE TO THE PCIE-EP: GET the received TLP PACKETS:- ----
|
| 947 |
|
|
process (pciewb_localreset_n, trn_clk, epif_rx_state, tlp_state, trn_rx_counter,
|
| 948 |
|
|
bram_rxtlp_writeaddress, rxstm_readytoroll, trn_rsof_n, tlpstm_isin_idle, trn_rdst_rdy_n)
|
| 949 |
|
|
begin
|
| 950 |
|
|
if (pciewb_localreset_n='0') then
|
| 951 |
|
|
pcie_just_received_a_new_tlp <= '0';
|
| 952 |
|
|
epif_rx_state <= "00000000";
|
| 953 |
|
|
trn_rdst_rdy_n <= '1';
|
| 954 |
|
|
trn_rx_counter <= (OTHERS => '0');
|
| 955 |
|
|
bram_rxtlp_we <= "0";
|
| 956 |
|
|
bram_rxtlp_writeaddress <= (OTHERS => '0');
|
| 957 |
|
|
bram_rxtlp_writedata <= (OTHERS => '0');
|
| 958 |
|
|
rxstm_readytoroll <= '0';
|
| 959 |
|
|
else
|
| 960 |
|
|
if (trn_clk'event and trn_clk = '1') then
|
| 961 |
|
|
|
| 962 |
|
|
case ( epif_rx_state ) is
|
| 963 |
|
|
|
| 964 |
|
|
--********** idle STATE **********
|
| 965 |
|
|
when "00000000" => --state 0
|
| 966 |
|
|
pcie_just_received_a_new_tlp <= '0';
|
| 967 |
|
|
bram_rxtlp_writedata <= trn_rd;
|
| 968 |
|
|
if (trn_rsrc_rdy_n='0' and trn_rsof_n='0' and tlpstm_isin_idle = '1' and trn_rdst_rdy_n='0') then
|
| 969 |
|
|
trn_rx_counter <= trn_rx_counter +1;
|
| 970 |
|
|
bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
|
| 971 |
|
|
epif_rx_state <= "00000001";
|
| 972 |
|
|
else
|
| 973 |
|
|
trn_rx_counter <= (OTHERS => '0');
|
| 974 |
|
|
bram_rxtlp_writeaddress <= (OTHERS => '0');
|
| 975 |
|
|
end if;
|
| 976 |
|
|
--destination ready:
|
| 977 |
|
|
if (tlpstm_isin_idle = '1')then
|
| 978 |
|
|
trn_rdst_rdy_n <= '0';
|
| 979 |
|
|
else
|
| 980 |
|
|
trn_rdst_rdy_n <= '1';
|
| 981 |
|
|
end if;
|
| 982 |
|
|
--write into buffer:
|
| 983 |
|
|
if (trn_rsrc_rdy_n='0' and trn_rsof_n='0' and tlpstm_isin_idle = '1') then
|
| 984 |
|
|
bram_rxtlp_we <= "1";
|
| 985 |
|
|
rxstm_readytoroll <= '1';
|
| 986 |
|
|
else
|
| 987 |
|
|
bram_rxtlp_we <= "0";
|
| 988 |
|
|
rxstm_readytoroll <= '0';
|
| 989 |
|
|
end if;
|
| 990 |
|
|
|
| 991 |
|
|
--********** read STATE **********
|
| 992 |
|
|
when "00000001" => --state 1
|
| 993 |
|
|
rxstm_readytoroll <= '0';
|
| 994 |
|
|
if (trn_reof_n ='0') then --last dw
|
| 995 |
|
|
epif_rx_state <= "00000010"; --for the next clk cycle
|
| 996 |
|
|
trn_rdst_rdy_n <= '1'; --ok, dont send more yet
|
| 997 |
|
|
end if;
|
| 998 |
|
|
if (trn_rsrc_rdy_n='0') then --only act if the EP was ready
|
| 999 |
|
|
trn_rx_counter <= trn_rx_counter +1;
|
| 1000 |
|
|
bram_rxtlp_writeaddress <= bram_rxtlp_writeaddress +1;
|
| 1001 |
|
|
bram_rxtlp_writedata <= trn_rd;
|
| 1002 |
|
|
end if;
|
| 1003 |
|
|
--in an early stage of this transfer, the scheduler can already
|
| 1004 |
|
|
--start working on the data, this way its pipelined, so the latency is lower.
|
| 1005 |
|
|
if (trn_rx_counter = "00000010") then
|
| 1006 |
|
|
pcie_just_received_a_new_tlp <= '1';--assert for one clk only
|
| 1007 |
|
|
else
|
| 1008 |
|
|
pcie_just_received_a_new_tlp <= '0';
|
| 1009 |
|
|
end if;
|
| 1010 |
|
|
|
| 1011 |
|
|
--********** finished filling up RX TLP STATE **********
|
| 1012 |
|
|
when "00000010" => --state 2
|
| 1013 |
|
|
epif_rx_state <= "00000000";
|
| 1014 |
|
|
trn_rx_counter <= (OTHERS => '0');
|
| 1015 |
|
|
|
| 1016 |
|
|
when others => --error
|
| 1017 |
|
|
epif_rx_state <= "00000000"; --go to state 0
|
| 1018 |
|
|
end case;
|
| 1019 |
|
|
end if;
|
| 1020 |
|
|
end if;
|
| 1021 |
|
|
end process;
|
| 1022 |
|
|
|
| 1023 |
|
|
--fixed connections:
|
| 1024 |
|
|
--trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
|
| 1025 |
|
|
--not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
|
| 1026 |
|
|
|
| 1027 |
|
|
|
| 1028 |
|
|
|
| 1029 |
|
|
|
| 1030 |
|
|
|
| 1031 |
|
|
-- flow control: INTERFACE TO THE PCIE-EP: - ----
|
| 1032 |
|
|
--not used. pcie-ep provides information about credit status.
|
| 1033 |
|
|
--unconnected: trn_fc_nph, trn_fc_npd, trn_fc_ph, trn_fc_pd, trn_fc_cplh, trn_fc_cpld
|
| 1034 |
|
|
trn_fc_sel <= "000";
|
| 1035 |
|
|
|
| 1036 |
|
|
|
| 1037 |
|
|
|
| 1038 |
|
|
|
| 1039 |
|
|
|
| 1040 |
|
|
-- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
|
| 1041 |
|
|
-- --- ALSO TLP PACKET PROCESSING.
|
| 1042 |
|
|
--Theory of operation:
|
| 1043 |
|
|
--RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle),
|
| 1044 |
|
|
--then store it (pcie_received_tlp), decode it (to figure out if its read request,
|
| 1045 |
|
|
--posted write or non-supported request), then assert a flag (start_write_wb0 or
|
| 1046 |
|
|
--start_read_wb0)to initiate a wishbone cycle.
|
| 1047 |
|
|
--TX: At the completion of a wishbone read, the wishbone statemachine asserts the
|
| 1048 |
|
|
--wb_transaction_complete flag, so we can assemble the TX TLP packet (pcie_to_transmit_tlp)
|
| 1049 |
|
|
--and assert the flag named pcie_there_is_a_new_tlp_to_transmit. This packet will be
|
| 1050 |
|
|
--a read completion packet on the PCIe link.
|
| 1051 |
|
|
--
|
| 1052 |
|
|
--This core can handle 1...8 DWORD accesses in one request (max 256bit payload ),
|
| 1053 |
|
|
--and can handle only one request at a time. If a new request is arriving while
|
| 1054 |
|
|
--processing the previous one (e.g. getting the data from a wishbone read), then
|
| 1055 |
|
|
--the state machine will not process it immediately, or it will hang. So the user
|
| 1056 |
|
|
--software has to wait for the previous read completion before issueing a new request.
|
| 1057 |
|
|
--The multiple DWORDs are handled separately by the WB statemachine.
|
| 1058 |
|
|
--Performance: WishBone bus: 62.5MHz, 32bit, 3clk/access -> 83MBytes/sec
|
| 1059 |
|
|
--
|
| 1060 |
|
|
--TLP decoding:
|
| 1061 |
|
|
--Header+Payload_data+TLP_DIGEST(ECRC).
|
| 1062 |
|
|
--received Header:
|
| 1063 |
|
|
--First Dword: bit.30/29=format: 00=3DW-header+no_data, 01=4DW-header+no_data,
|
| 1064 |
|
|
--10=3DW-header+data, 11=4DW-header+data. bit.28:24=type: 00000 or 00001 are memory
|
| 1065 |
|
|
--read requests, 00000 or 00001 are memory write request if type=1x. read request
|
| 1066 |
|
|
--completion is 01010 and type=10. bit.9:0 is payload size [DW].
|
| 1067 |
|
|
--Second Dword: bit.31:16 is requester ID. bit3:0 is first dword byte enable, bit.7:4 is
|
| 1068 |
|
|
--byte enable for last dword data. intermediate dwords have all bytes enabled.
|
| 1069 |
|
|
--Third DWORD: address, where bit.1:0=00b. 4DW headers are for 64bit. 64bit adressing
|
| 1070 |
|
|
--uses 3rd-dword for addre63:32, 4th dword for addr31:0.
|
| 1071 |
|
|
--
|
| 1072 |
|
|
--The TLP variables in this core: BRAM memory used store TLP, up to 1-2kBytes
|
| 1073 |
|
|
--
|
| 1074 |
|
|
--Read completion is 3DW header and routed by completer-ID and requester-ID, not address.
|
| 1075 |
|
|
--The core has to store the requester ID and feed it back in the completion packet.
|
| 1076 |
|
|
--Completion status: 000=successful, 100=completer_abort, 001=unsupported request. byte
|
| 1077 |
|
|
--count is N.of bytes left. lower_address is the first enabled byte of data returned
|
| 1078 |
|
|
--with the Completion.
|
| 1079 |
|
|
--
|
| 1080 |
|
|
-- Completion packet header (descriptor): new, axi4-stream format used!!!!!!!!!!!!
|
| 1081 |
|
|
--
|
| 1082 |
|
|
-- 63 32 31 0
|
| 1083 |
|
|
-- /---------DW1--------------\/-----------DW0---------------\
|
| 1084 |
|
|
-- ------------------------address63:2----------------------AT (address type)
|
| 1085 |
|
|
--
|
| 1086 |
|
|
-- 63 32 31 0
|
| 1087 |
|
|
-- /---------DW3--------------\/-----------DW2---------------\
|
| 1088 |
|
|
-- R attr TC BAR-ap BAR-id tar-funct, tag, bus dev, funct, R, req type, dword count
|
| 1089 |
|
|
--
|
| 1090 |
|
|
|
| 1091 |
|
|
|
| 1092 |
|
|
--TLP-protocol statemachine:
|
| 1093 |
|
|
process (pciewb_localreset_n, trn_clk, tlp_state,
|
| 1094 |
|
|
pcie_just_received_a_new_tlp, tlp_datacount,
|
| 1095 |
|
|
bram_rxtlp_readdata, bram_txtlp_writeaddress, bram_rxtlp_readaddress,
|
| 1096 |
|
|
tlp_state_copy, rxtlp_decodedaddress,
|
| 1097 |
|
|
rxtlp_header_dw0, rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3,
|
| 1098 |
|
|
bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag,
|
| 1099 |
|
|
tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id,
|
| 1100 |
|
|
rxtlp_requesterid)
|
| 1101 |
|
|
begin
|
| 1102 |
|
|
if (pciewb_localreset_n='0') then
|
| 1103 |
|
|
start_read_wb0 <= '0';
|
| 1104 |
|
|
start_write_wb0 <= '0';
|
| 1105 |
|
|
pcie_bar0_wb_data_o_feed <= (others => '0');
|
| 1106 |
|
|
pcie_bar0_wb_addr_o_feed <= (others => '0');
|
| 1107 |
|
|
pcie_bar0_wb_sel_o_feed <= (others => '0');
|
| 1108 |
|
|
pcie_there_is_a_new_tlp_to_transmit <= '0';
|
| 1109 |
|
|
rxtlp_decodedaddress<= (others => '0');
|
| 1110 |
|
|
tlp_payloadsize_dwords <= (others => '0');
|
| 1111 |
|
|
rxtlp_firstdw_be <= (others => '0');
|
| 1112 |
|
|
rxtlp_lastdw_be <= (others => '0');
|
| 1113 |
|
|
rxtlp_requesterid <= (others => '0');
|
| 1114 |
|
|
tlp_state <= (others => '0');
|
| 1115 |
|
|
tlp_state_copy <= (others => '0');
|
| 1116 |
|
|
bram_txtlp_we <= "0";
|
| 1117 |
|
|
bram_txtlp_writeaddress <= (others => '0');
|
| 1118 |
|
|
bram_txtlp_writedata <= (others => '0');
|
| 1119 |
|
|
bram_rxtlp_readaddress <= (others => '0');
|
| 1120 |
|
|
rxtlp_header_dw0 <= "01111111000000000000000000000000";
|
| 1121 |
|
|
rxtlp_header_dw1 <= (others => '0');
|
| 1122 |
|
|
rxtlp_header_dw2 <= (others => '0');
|
| 1123 |
|
|
rxtlp_header_dw3 <= (others => '0');
|
| 1124 |
|
|
flag1 <= '0';
|
| 1125 |
|
|
rxdw1_23_0 <= (others => '0');
|
| 1126 |
|
|
pcie_rxtlp_tag <= (others => '0');
|
| 1127 |
|
|
rcompl_bytecount_field <= (others => '0');
|
| 1128 |
|
|
tlpstm_isin_idle <= '1';
|
| 1129 |
|
|
else
|
| 1130 |
|
|
if (trn_clk'event and trn_clk = '1') then
|
| 1131 |
|
|
case ( tlp_state ) is
|
| 1132 |
|
|
|
| 1133 |
|
|
--********** IDLE STATE **********
|
| 1134 |
|
|
--also re-initialize signals...
|
| 1135 |
|
|
when "00000000" => --state 0
|
| 1136 |
|
|
if (pcie_just_received_a_new_tlp='1') then
|
| 1137 |
|
|
tlp_state <= "00000001"; --to tlp decoding state
|
| 1138 |
|
|
tlpstm_isin_idle <= '0';
|
| 1139 |
|
|
else
|
| 1140 |
|
|
tlpstm_isin_idle <= '1';
|
| 1141 |
|
|
end if;
|
| 1142 |
|
|
start_write_wb0 <= '0';
|
| 1143 |
|
|
start_read_wb0 <= '0';
|
| 1144 |
|
|
tlp_state_copy <= tlp_state;
|
| 1145 |
|
|
bram_txtlp_we <= "0";
|
| 1146 |
|
|
bram_txtlp_writeaddress <= (others => '0');
|
| 1147 |
|
|
bram_txtlp_writedata <= (others => '0');
|
| 1148 |
|
|
bram_rxtlp_readaddress <= (others => '0');
|
| 1149 |
|
|
tlp_datacount <= "00000001";
|
| 1150 |
|
|
rxtlp_header_dw0 <= "01111111000000000000000000000000"; --this is to prevent false decode
|
| 1151 |
|
|
pcie_bar0_wb_data_o_feed <= (others => '0');
|
| 1152 |
|
|
pcie_bar0_wb_addr_o_feed <= (others => '0');
|
| 1153 |
|
|
pcie_bar0_wb_sel_o_feed <= (others => '0');
|
| 1154 |
|
|
rxtlp_header_dw1 <= (others => '0');
|
| 1155 |
|
|
rxtlp_header_dw2 <= (others => '0');
|
| 1156 |
|
|
rxtlp_header_dw3 <= (others => '0');
|
| 1157 |
|
|
rxdw1_23_0 <= (others => '0');
|
| 1158 |
|
|
pcie_rxtlp_tag <= (others => '0');
|
| 1159 |
|
|
pcie_there_is_a_new_tlp_to_transmit <= '0';
|
| 1160 |
|
|
rxtlp_decodedaddress<= (others => '0');
|
| 1161 |
|
|
tlp_payloadsize_dwords <= (others => '0');
|
| 1162 |
|
|
rxtlp_firstdw_be <= (others => '0');
|
| 1163 |
|
|
rxtlp_lastdw_be <= (others => '0');
|
| 1164 |
|
|
rxtlp_requesterid <= (others => '0');
|
| 1165 |
|
|
rcompl_bytecount_field <= (others => '0');
|
| 1166 |
|
|
|
| 1167 |
|
|
|
| 1168 |
|
|
--********** TLP ARRIVED STATE **********
|
| 1169 |
|
|
--read TLP out of EP, decode and decide,
|
| 1170 |
|
|
--latch address/sel/wr_data
|
| 1171 |
|
|
--All the "IF"-statements use address+1, because the BRAM read side has data available 1clk late!!!
|
| 1172 |
|
|
--Added an ectra clock delay, based on testing, since the data is one more CLK late.
|
| 1173 |
|
|
when "00000001" => --state 1
|
| 1174 |
|
|
--latch the header:
|
| 1175 |
|
|
bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
|
| 1176 |
|
|
if (bram_rxtlp_readaddress = "000000010") then
|
| 1177 |
|
|
rxtlp_header_dw0 <= bram_rxtlp_readdata;
|
| 1178 |
|
|
elsif (bram_rxtlp_readaddress = "000000011") then
|
| 1179 |
|
|
rxtlp_header_dw1 <= bram_rxtlp_readdata;
|
| 1180 |
|
|
elsif (bram_rxtlp_readaddress = "000000100") then
|
| 1181 |
|
|
rxtlp_header_dw2 <= bram_rxtlp_readdata;
|
| 1182 |
|
|
elsif (bram_rxtlp_readaddress = "000000101") then
|
| 1183 |
|
|
rxtlp_header_dw3 <= bram_rxtlp_readdata;
|
| 1184 |
|
|
end if;
|
| 1185 |
|
|
--decode some parameters:
|
| 1186 |
|
|
tlp_payloadsize_dwords <= rxtlp_header_dw2(7 downto 0);
|
| 1187 |
|
|
rxtlp_firstdw_be <= "1111"; --rxtlp_header_dw1(3 downto 0); no longer supported
|
| 1188 |
|
|
rxtlp_lastdw_be <= "1111"; --rxtlp_header_dw1(7 downto 4); no longer supported
|
| 1189 |
|
|
rxtlp_requesterid <= rxtlp_header_dw2(31 downto 16);
|
| 1190 |
|
|
rxtlp_attr_tc <= rxtlp_header_dw3(30 downto 25);
|
| 1191 |
|
|
pcie_rxtlp_tag <= rxtlp_header_dw3(7 downto 0) ; --tag
|
| 1192 |
|
|
rxtlp_at <= rxtlp_header_dw0(1 downto 0);
|
| 1193 |
|
|
--decide based on header:
|
| 1194 |
|
|
if (rxtlp_header_dw2(14 downto 8)="0000") then --32bit read
|
| 1195 |
|
|
if (bram_rxtlp_readaddress = "000000100") then
|
| 1196 |
|
|
--rxtlp_decodedaddress <= bram_rxtlp_readdata;
|
| 1197 |
|
|
rxtlp_decodedaddress(29 downto 0) <= rxtlp_header_dw0(31 downto 2); --byte address or dword address?????
|
| 1198 |
|
|
bram_txtlp_writeaddress(8 downto 0) <= "000000011"; --point after the 3dw readcompl header
|
| 1199 |
|
|
tlp_state <= "00000011";
|
| 1200 |
|
|
end if;
|
| 1201 |
|
|
elsif (rxtlp_header_dw2(14 downto 8)="0001") then --32bit write
|
| 1202 |
|
|
if (bram_rxtlp_readaddress = "000000100") then
|
| 1203 |
|
|
--rxtlp_decodedaddress <= bram_rxtlp_readdata;
|
| 1204 |
|
|
rxtlp_decodedaddress(29 downto 0) <= rxtlp_header_dw0(31 downto 2);
|
| 1205 |
|
|
tlp_state <= "00000010";
|
| 1206 |
|
|
end if;
|
| 1207 |
|
|
elsif (rxtlp_header_dw0(30 downto 24)="1111111") then --just wait until this gets a real value (not ready yet)
|
| 1208 |
|
|
rxtlp_decodedaddress <= bram_rxtlp_readdata;
|
| 1209 |
|
|
else --unsupported request
|
| 1210 |
|
|
if (bram_rxtlp_readaddress = "000000100") then
|
| 1211 |
|
|
tlp_state <= "00000101";
|
| 1212 |
|
|
bram_txtlp_writeaddress <= "111111111";
|
| 1213 |
|
|
end if;
|
| 1214 |
|
|
end if;
|
| 1215 |
|
|
|
| 1216 |
|
|
|
| 1217 |
|
|
--********** WRITE STATE **********
|
| 1218 |
|
|
--initiate WB write(s) (1...N DWORD accesses)
|
| 1219 |
|
|
when "00000010" => --state 2
|
| 1220 |
|
|
pcie_bar0_wb_addr_o_feed(BAR0_WIDTH-1 downto 2) <= rxtlp_decodedaddress(BAR0_WIDTH-1 downto 2) + tlp_datacount -1; -- BAR0 size is hardcoded here, by cutting MSB's off
|
| 1221 |
|
|
pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
|
| 1222 |
|
|
pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be;
|
| 1223 |
|
|
pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata;
|
| 1224 |
|
|
tlp_state_copy <= tlp_state;
|
| 1225 |
|
|
if (tlp_state_copy = tlp_state) then
|
| 1226 |
|
|
start_write_wb0 <= '0';
|
| 1227 |
|
|
else --generate just one pulse, at the first clk cycle in this state
|
| 1228 |
|
|
start_write_wb0 <= '1';
|
| 1229 |
|
|
end if;
|
| 1230 |
|
|
if (wb_transaction_complete='1') then --one DW transfer completed
|
| 1231 |
|
|
|
| 1232 |
|
|
if (tlp_payloadsize_dwords = tlp_datacount) then --all data completed
|
| 1233 |
|
|
tlp_state <= "00000000"; --to idle
|
| 1234 |
|
|
else
|
| 1235 |
|
|
tlp_state <= "00010100"; --restart wb transaction with new data
|
| 1236 |
|
|
bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
|
| 1237 |
|
|
tlp_datacount <= tlp_datacount +1;
|
| 1238 |
|
|
end if;
|
| 1239 |
|
|
end if;
|
| 1240 |
|
|
--* Write restart state *
|
| 1241 |
|
|
when "00010100" => --state 20
|
| 1242 |
|
|
tlp_state <= "00000010";
|
| 1243 |
|
|
|
| 1244 |
|
|
|
| 1245 |
|
|
--********** READ STATE **********
|
| 1246 |
|
|
--initiate WB read, store all data, starting from address=2, then go to completion state
|
| 1247 |
|
|
when "00000011" => --state 3
|
| 1248 |
|
|
pcie_bar0_wb_addr_o_feed(BAR0_WIDTH-1 downto 2) <= rxtlp_decodedaddress(BAR0_WIDTH-1 downto 2) + tlp_datacount -1;
|
| 1249 |
|
|
pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
|
| 1250 |
|
|
pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be;
|
| 1251 |
|
|
tlp_state_copy <= tlp_state;
|
| 1252 |
|
|
if (tlp_state_copy = tlp_state) then
|
| 1253 |
|
|
start_read_wb0 <= '0';
|
| 1254 |
|
|
else --generate just one pulse
|
| 1255 |
|
|
start_read_wb0 <= '1';
|
| 1256 |
|
|
end if;
|
| 1257 |
|
|
if (wb_transaction_complete='1') then
|
| 1258 |
|
|
bram_txtlp_writedata <= pcie_bar0_wb_data_i_latched;
|
| 1259 |
|
|
bram_txtlp_we <= "1";
|
| 1260 |
|
|
if (tlp_payloadsize_dwords = tlp_datacount)then
|
| 1261 |
|
|
tlp_state <= "01111110"; --read completion
|
| 1262 |
|
|
--bram_txtlp_writeaddress remains the same to capture data in next clock cycle
|
| 1263 |
|
|
--Calculate completion header's "rcompl_bytecount_field" from rxtlp_firstdw_be, rxtlp_lastdw_be, tlp_payloadsize_dwords
|
| 1264 |
|
|
if (rxtlp_lastdw_be="0000") then --max 1DW
|
| 1265 |
|
|
if (rxtlp_firstdw_be="1111") then --4bytes
|
| 1266 |
|
|
rcompl_bytecount_field <= "0000000100";
|
| 1267 |
|
|
bram_txtlp_writedata (25 downto 16) <= "0000000100";
|
| 1268 |
|
|
elsif (rxtlp_firstdw_be="0111" or rxtlp_firstdw_be="1110") then
|
| 1269 |
|
|
rcompl_bytecount_field <= "0000000011";
|
| 1270 |
|
|
bram_txtlp_writedata (25 downto 16) <= "0000000011";
|
| 1271 |
|
|
elsif (rxtlp_firstdw_be="0011" or rxtlp_firstdw_be="1100" or rxtlp_firstdw_be="0110") then
|
| 1272 |
|
|
rcompl_bytecount_field <= "0000000010";
|
| 1273 |
|
|
bram_txtlp_writedata (25 downto 16) <= "0000000010";
|
| 1274 |
|
|
else
|
| 1275 |
|
|
rcompl_bytecount_field <= "0000000001";
|
| 1276 |
|
|
bram_txtlp_writedata (25 downto 16) <= "0000000001";
|
| 1277 |
|
|
end if;
|
| 1278 |
|
|
else --more than 1DW: right now we dont support non-aligned multi-Dword accesses
|
| 1279 |
|
|
rcompl_bytecount_field(9 downto 2) <= tlp_payloadsize_dwords;
|
| 1280 |
|
|
rcompl_bytecount_field(1 downto 0) <= "00";
|
| 1281 |
|
|
end if;
|
| 1282 |
|
|
else
|
| 1283 |
|
|
tlp_state <= "00011110"; --one more wb read
|
| 1284 |
|
|
tlp_datacount <= tlp_datacount +1;
|
| 1285 |
|
|
end if;
|
| 1286 |
|
|
else
|
| 1287 |
|
|
bram_txtlp_we <= "0";
|
| 1288 |
|
|
end if;
|
| 1289 |
|
|
--* read restart STATE *
|
| 1290 |
|
|
when "00011110" => --state 30
|
| 1291 |
|
|
tlp_state_copy <= tlp_state; -- SC: required to re-trigger additional reads, start_read_wb0 <= '1'
|
| 1292 |
|
|
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; -- SC: increment address here (moved)
|
| 1293 |
|
|
tlp_state <= "00000011";
|
| 1294 |
|
|
bram_txtlp_we <= "0";
|
| 1295 |
|
|
|
| 1296 |
|
|
--intermediate state before completion (to ensure data latch at address-4)
|
| 1297 |
|
|
--for additional data bytes/dwords
|
| 1298 |
|
|
when "01111110" => --state 126
|
| 1299 |
|
|
tlp_state <= "00000100";
|
| 1300 |
|
|
bram_txtlp_writeaddress <= (OTHERS => '0'); --reset address to zero, for the TLP header latching!!!!
|
| 1301 |
|
|
--pre-write header-DW0: ***
|
| 1302 |
|
|
bram_txtlp_writedata (31) <= '0'; --flag1; --reserved
|
| 1303 |
|
|
bram_txtlp_writedata (30) <= '0'; --not locked read
|
| 1304 |
|
|
bram_txtlp_writedata (29 downto 26) <= "0000"; --byte count upper
|
| 1305 |
|
|
bram_txtlp_writedata (25 downto 16) <= rcompl_bytecount_field;
|
| 1306 |
|
|
bram_txtlp_writedata (15 downto 10) <= "000000";
|
| 1307 |
|
|
bram_txtlp_writedata (9 downto 8) <= rxtlp_at;
|
| 1308 |
|
|
bram_txtlp_writedata (7) <= '0';
|
| 1309 |
|
|
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(4 downto 0); --lower address - decoding correct, 32bit or 8bit addressing???
|
| 1310 |
|
|
case (rxtlp_firstdw_be) is
|
| 1311 |
|
|
when "0000" => bram_txtlp_writedata (1 downto 0) <= "00"; --lower address
|
| 1312 |
|
|
when "1000" => bram_txtlp_writedata (1 downto 0) <= "11"; --lower address
|
| 1313 |
|
|
when "0100" => bram_txtlp_writedata (1 downto 0) <= "10"; --lower address
|
| 1314 |
|
|
when "1100" => bram_txtlp_writedata (1 downto 0) <= "10"; --lower address
|
| 1315 |
|
|
when "0010" => bram_txtlp_writedata (1 downto 0) <= "01"; --lower address
|
| 1316 |
|
|
when "0110" => bram_txtlp_writedata (1 downto 0) <= "01"; --lower address
|
| 1317 |
|
|
when "1010" => bram_txtlp_writedata (1 downto 0) <= "01"; --lower address
|
| 1318 |
|
|
when "1110" => bram_txtlp_writedata (1 downto 0) <= "01"; --lower address
|
| 1319 |
|
|
when others => bram_txtlp_writedata (1 downto 0) <= "00"; --lower address
|
| 1320 |
|
|
end case;
|
| 1321 |
|
|
|
| 1322 |
|
|
|
| 1323 |
|
|
|
| 1324 |
|
|
--********** READ COMPLETION STATE **********
|
| 1325 |
|
|
--assemble the tx TLP header, starting from position-0, and initiate the transmit
|
| 1326 |
|
|
--buffer signals bram_txtlp_we, bram_txtlp_writeaddress, bram_txtlp_writedata
|
| 1327 |
|
|
when "00000100" => --state 4
|
| 1328 |
|
|
tlp_state_copy <= tlp_state;
|
| 1329 |
|
|
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
|
| 1330 |
|
|
--header-1.dw ***
|
| 1331 |
|
|
if (bram_txtlp_writeaddress="000000000") then --if address is 0: launch data for next lock/address(1):
|
| 1332 |
|
|
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid;
|
| 1333 |
|
|
bram_txtlp_writedata (15) <= '0';
|
| 1334 |
|
|
bram_txtlp_writedata (14) <= '0';
|
| 1335 |
|
|
bram_txtlp_writedata (13 downto 12) <= "00"; --completion status 000=successful, 001=unsupported, 100=abort
|
| 1336 |
|
|
bram_txtlp_writedata (11 downto 8) <= "0000"; --tlp_payloadsize_dwords;
|
| 1337 |
|
|
bram_txtlp_writedata (7 downto 0) <= tlp_payloadsize_dwords;
|
| 1338 |
|
|
bram_txtlp_we <= "1";
|
| 1339 |
|
|
--header-2.dw ***
|
| 1340 |
|
|
elsif (bram_txtlp_writeaddress="000000001") then --if address is 1: launch data for next lock/address(2):
|
| 1341 |
|
|
bram_txtlp_writedata (31) <= '0';
|
| 1342 |
|
|
bram_txtlp_writedata (30 downto 25) <= rxtlp_attr_tc;
|
| 1343 |
|
|
bram_txtlp_writedata (24) <= '1'; --completer id enable
|
| 1344 |
|
|
bram_txtlp_writedata (23 downto 8) <= cfg_completer_id;
|
| 1345 |
|
|
bram_txtlp_writedata (7 downto 0) <= pcie_rxtlp_tag;
|
| 1346 |
|
|
else --data dwords, disable writes from next clock cycle
|
| 1347 |
|
|
bram_txtlp_we <= "0";
|
| 1348 |
|
|
end if;
|
| 1349 |
|
|
--one pulse to start the ep-if statemachine, upon arriving to this state
|
| 1350 |
|
|
if (tlp_state_copy = tlp_state) then
|
| 1351 |
|
|
pcie_there_is_a_new_tlp_to_transmit <= '0';
|
| 1352 |
|
|
else
|
| 1353 |
|
|
pcie_there_is_a_new_tlp_to_transmit <= '1';
|
| 1354 |
|
|
end if;
|
| 1355 |
|
|
--back to idle when the ep-if tx is finished: (wait to avoid overwrite)
|
| 1356 |
|
|
if (pcie_tlp_tx_complete='1') then
|
| 1357 |
|
|
tlp_state <= "00000000";
|
| 1358 |
|
|
end if;
|
| 1359 |
|
|
|
| 1360 |
|
|
|
| 1361 |
|
|
--********** UNSUPPORTED REQUEST STATE **********
|
| 1362 |
|
|
--completion response with status=001
|
| 1363 |
|
|
when "00000101" => --state 5
|
| 1364 |
|
|
tlp_state_copy <= tlp_state;
|
| 1365 |
|
|
tlp_payloadsize_dwords <= "00000000";
|
| 1366 |
|
|
bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
|
| 1367 |
|
|
--assembling the TLP packet: )
|
| 1368 |
|
|
if (bram_txtlp_writeaddress="111111111") then --header 0.dw
|
| 1369 |
|
|
bram_txtlp_we <= "1";
|
| 1370 |
|
|
bram_txtlp_writedata (31) <= flag1; --reserved
|
| 1371 |
|
|
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
|
| 1372 |
|
|
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
|
| 1373 |
|
|
elsif (bram_txtlp_writeaddress="000000000") then --header 1.dw
|
| 1374 |
|
|
bram_txtlp_we <= "1";
|
| 1375 |
|
|
bram_txtlp_writedata (31 downto 16) <= cfg_completer_id; --completer ID
|
| 1376 |
|
|
bram_txtlp_writedata (15 downto 13) <= "000"; --status= UNSUPPORTED REQUEST ***
|
| 1377 |
|
|
bram_txtlp_writedata (12) <= '0'; --reserved
|
| 1378 |
|
|
bram_txtlp_writedata (11 downto 0) <= "000000000000"; --remaining byte count
|
| 1379 |
|
|
elsif (bram_txtlp_writeaddress="000000001") then --header 2.dw
|
| 1380 |
|
|
bram_txtlp_we <= "1";
|
| 1381 |
|
|
bram_txtlp_writedata (31 downto 16) <= rxtlp_requesterid; --requester ID
|
| 1382 |
|
|
bram_txtlp_writedata (15 downto 8) <= pcie_rxtlp_tag ; --pcie_received_tlp (47 downto 40);--tag
|
| 1383 |
|
|
bram_txtlp_writedata (7) <= '0'; --reserved
|
| 1384 |
|
|
bram_txtlp_writedata (6 downto 2) <= rxtlp_decodedaddress(6 downto 2); --lower address
|
| 1385 |
|
|
bram_txtlp_writedata (1 downto 0) <= bit10(1 downto 0); --lower address
|
| 1386 |
|
|
else --data dwords
|
| 1387 |
|
|
bram_txtlp_we <= "0";
|
| 1388 |
|
|
end if;
|
| 1389 |
|
|
--one pulse to start the ep-if statemachine, upon arriving to this state
|
| 1390 |
|
|
if (tlp_state_copy = tlp_state) then
|
| 1391 |
|
|
pcie_there_is_a_new_tlp_to_transmit <= '0';
|
| 1392 |
|
|
else
|
| 1393 |
|
|
pcie_there_is_a_new_tlp_to_transmit <= '1';
|
| 1394 |
|
|
end if;
|
| 1395 |
|
|
--back to idle when finished:
|
| 1396 |
|
|
if (pcie_tlp_tx_complete='1') then
|
| 1397 |
|
|
tlp_state <= "00000000";
|
| 1398 |
|
|
end if;
|
| 1399 |
|
|
|
| 1400 |
|
|
when others => --error
|
| 1401 |
|
|
tlp_state <= "00000000"; --go to state 0
|
| 1402 |
|
|
end case;
|
| 1403 |
|
|
|
| 1404 |
|
|
end if;
|
| 1405 |
|
|
end if;
|
| 1406 |
|
|
end process; --end tlp statemachine
|
| 1407 |
|
|
|
| 1408 |
|
|
|
| 1409 |
|
|
|
| 1410 |
|
|
|
| 1411 |
|
|
--byte enable encoding to wb_address bit1:0
|
| 1412 |
|
|
--this does not swap the endian, since only the data is swapped in the pcie packets.
|
| 1413 |
|
|
process ( pciewb_localreset_n, rxtlp_firstdw_be )
|
| 1414 |
|
|
begin
|
| 1415 |
|
|
if (pciewb_localreset_n = '0') then
|
| 1416 |
|
|
bit10(1 downto 0) <="00";
|
| 1417 |
|
|
else
|
| 1418 |
|
|
if (rxtlp_firstdw_be ="0001") then
|
| 1419 |
|
|
bit10(1 downto 0) <= "00";
|
| 1420 |
|
|
elsif (rxtlp_firstdw_be ="0010") then
|
| 1421 |
|
|
bit10(1 downto 0) <= "01";
|
| 1422 |
|
|
elsif (rxtlp_firstdw_be ="0100") then
|
| 1423 |
|
|
bit10(1 downto 0) <= "10";
|
| 1424 |
|
|
elsif (rxtlp_firstdw_be ="1000") then
|
| 1425 |
|
|
bit10(1 downto 0) <= "11";
|
| 1426 |
|
|
elsif (rxtlp_firstdw_be ="0011") then
|
| 1427 |
|
|
bit10(1 downto 0) <= "00";
|
| 1428 |
|
|
elsif (rxtlp_firstdw_be ="1100") then
|
| 1429 |
|
|
bit10(1 downto 0) <= "10";
|
| 1430 |
|
|
elsif (rxtlp_firstdw_be ="1111") then
|
| 1431 |
|
|
bit10(1 downto 0) <= "00";
|
| 1432 |
|
|
else --this should never happen
|
| 1433 |
|
|
bit10(1 downto 0) <= "00";
|
| 1434 |
|
|
end if;
|
| 1435 |
|
|
end if;
|
| 1436 |
|
|
end process;
|
| 1437 |
|
|
|
| 1438 |
|
|
|
| 1439 |
|
|
|
| 1440 |
|
|
|
| 1441 |
|
|
|
| 1442 |
|
|
-- INTERRUPTS: -------------------------------------------------------------------------
|
| 1443 |
|
|
--to assert an interrupt, use the cfg_interrupt_assert_n pin.
|
| 1444 |
|
|
--datasheet text:
|
| 1445 |
|
|
--As shown in Figure 6-30, the user application first asserts cfg_interrupt_n and
|
| 1446 |
|
|
--cfg_interrupt_assert_n to assert the interrupt. The user application should select a
|
| 1447 |
|
|
--specific interrupt (INTA, INTB, INTC, or INTD) using cfg_interrupt_di[7:0] as shown
|
| 1448 |
|
|
--in Table 6-19.
|
| 1449 |
|
|
-- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt has been accepted.
|
| 1450 |
|
|
--On the following clock cycle, the user application deasserts cfg_interrupt_n and, if the
|
| 1451 |
|
|
--Interrupt Disable bit in the PCI Command register is set to 0, the core sends an assert
|
| 1452 |
|
|
--interrupt message (Assert_INTA, Assert_INTB, and so forth).
|
| 1453 |
|
|
-- After the user application has determined that the interrupt has been serviced, it
|
| 1454 |
|
|
--asserts cfg_interrupt_n while deasserting cfg_interrupt_assert_n to deassert the
|
| 1455 |
|
|
--interrupt. The appropriate interrupt must be indicated via cfg_interrupt_di[7:0].
|
| 1456 |
|
|
-- The core then asserts cfg_interrupt_rdy_n to indicate the interrupt deassertion has
|
| 1457 |
|
|
--been accepted. On the following clock cycle, the user application deasserts
|
| 1458 |
|
|
--cfg_interrupt_n and the core sends a deassert interrupt message (Deassert_INTA,
|
| 1459 |
|
|
--Deassert_INTB, and so forth).
|
| 1460 |
|
|
--cfg_interrupt_di[7:0] value Legacy Interrupt
|
| 1461 |
|
|
--00h INTA
|
| 1462 |
|
|
--01h INTB
|
| 1463 |
|
|
--02h INTC
|
| 1464 |
|
|
--03h INTD
|
| 1465 |
|
|
|
| 1466 |
|
|
cfg_interrupt_di <= "00000000"; --intA used
|
| 1467 |
|
|
|
| 1468 |
|
|
--prohibit IRQ assert when TLP state machine not idle.
|
| 1469 |
|
|
-- if an IRQ is asserted between a read request and completion, it causes an error in the endpoint block.
|
| 1470 |
|
|
-- added by StBa, AAC Microtec, 2012
|
| 1471 |
|
|
irq_prohibit <= not tlpstm_isin_idle;
|
| 1472 |
|
|
|
| 1473 |
|
|
-- fixed compatibility with both MSI interrupts and legacy interrupts
|
| 1474 |
|
|
-- added by SC, FRIB, 2016
|
| 1475 |
|
|
pcie_msi_enabled <= cfg_interrupt_msienable;
|
| 1476 |
|
|
|
| 1477 |
|
|
process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
|
| 1478 |
|
|
cfg_interrupt_rdy_n)
|
| 1479 |
|
|
begin
|
| 1480 |
|
|
if (pciewb_localreset_n='0') then
|
| 1481 |
|
|
pcieirq_state <= "000";
|
| 1482 |
|
|
cfg_interrupt_n <= '1';
|
| 1483 |
|
|
cfg_interrupt_assert_n_1 <= '1';
|
| 1484 |
|
|
else
|
| 1485 |
|
|
if (trn_clk'event and trn_clk = '1') then
|
| 1486 |
|
|
case ( pcieirq_state ) is
|
| 1487 |
|
|
--********** idle STATE **********
|
| 1488 |
|
|
when "000" => --state 0
|
| 1489 |
|
|
cfg_interrupt_n <= '1'; --inactive
|
| 1490 |
|
|
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
|
| 1491 |
|
|
if (pcie_irq = '1') then
|
| 1492 |
|
|
pcieirq_state <= "001";
|
| 1493 |
|
|
end if;
|
| 1494 |
|
|
--********** wait for not irq_prohibit **********
|
| 1495 |
|
|
when "001" => --state 1
|
| 1496 |
|
|
if (irq_prohibit = '0') then
|
| 1497 |
|
|
pcieirq_state <= "010";
|
| 1498 |
|
|
cfg_interrupt_n <= '0'; --active
|
| 1499 |
|
|
cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert
|
| 1500 |
|
|
end if;
|
| 1501 |
|
|
--********** assert STATE **********
|
| 1502 |
|
|
when "010" => --state 2
|
| 1503 |
|
|
cfg_interrupt_n <= '0'; --request INTA assertion
|
| 1504 |
|
|
if (cfg_interrupt_rdy_n ='0') then --ep accepted it
|
| 1505 |
|
|
cfg_interrupt_n <= '1'; --deassert the request
|
| 1506 |
|
|
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
|
| 1507 |
|
|
pcieirq_state <= "011"; -- wait for IRQ deassert
|
| 1508 |
|
|
end if;
|
| 1509 |
|
|
--********** (LEGACY) pcie_irq kept asserted STATE **********
|
| 1510 |
|
|
when "011" => --state 3
|
| 1511 |
|
|
if (pcie_irq='0' and irq_prohibit='0' and cfg_interrupt_msienable='0') then
|
| 1512 |
|
|
pcieirq_state <= "100"; -- LEGACY, pcie_irq gets deasserted
|
| 1513 |
|
|
end if;
|
| 1514 |
|
|
if (pcie_irq='0' and cfg_interrupt_msienable='1') then
|
| 1515 |
|
|
pcieirq_state <= "000"; -- MSI IRQ, back to IDLE when pcie_irq deasserted
|
| 1516 |
|
|
end if;
|
| 1517 |
|
|
cfg_interrupt_n <= '1'; --inactive
|
| 1518 |
|
|
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
|
| 1519 |
|
|
--********** DEassert STATE **********
|
| 1520 |
|
|
-- below state only used for legacy interrupts
|
| 1521 |
|
|
when "100" => --state 4
|
| 1522 |
|
|
cfg_interrupt_n <= '0'; --request INTA DEassertion
|
| 1523 |
|
|
if (cfg_interrupt_rdy_n ='0') then --ep accepted it
|
| 1524 |
|
|
cfg_interrupt_n <= '1'; --deassert the request
|
| 1525 |
|
|
pcieirq_state <= "000";
|
| 1526 |
|
|
end if;
|
| 1527 |
|
|
|
| 1528 |
|
|
when others => --error
|
| 1529 |
|
|
pcieirq_state <= "000"; --go to state 0
|
| 1530 |
|
|
end case;
|
| 1531 |
|
|
end if;
|
| 1532 |
|
|
end if;
|
| 1533 |
|
|
end process;
|
| 1534 |
|
|
|
| 1535 |
|
|
--this (little delay) is to fix a hold time violation created inside the pcie-ep ip:
|
| 1536 |
|
|
cfg_interrupt_assert_n <= cfg_interrupt_assert_n_1 or (not pciewb_localreset_n);
|
| 1537 |
|
|
|
| 1538 |
|
|
|
| 1539 |
|
|
|
| 1540 |
|
|
|
| 1541 |
|
|
|
| 1542 |
|
|
|
| 1543 |
|
|
-- -------- END OF FILE -------------------------------------------------------------------------------------
|
| 1544 |
|
|
end Behavioral;
|
| 1545 |
|
|
|
| 1546 |
|
|
|
