OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [synopsis] - Blame information for rev 13

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 13 barabba 
{
2 
  'attributes' => {
3 
    'HDLCodeGenStatus' => 0,
4 
    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
5 
    'Impl_file' => 'ISE Defaults',
6 
    'Impl_file_sgadvanced' => '',
7 
    'Synth_file' => 'XST Defaults',
8 
    'Synth_file_sgadvanced' => '',
9 
    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
10 
    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
11 
    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
12 
    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
13 
    'base_system_period_hardware' => 5,
14 
    'base_system_period_simulink' => '8e-009',
15 
    'block_icon_display' => 'Default',
16 
    'block_type' => 'sysgen',
17 
    'block_version' => '',
18 
    'ce_clr' => 0,
19 
    'clkWrapper' => 'inout_logic_cw',
20 
    'clkWrapperFile' => 'inout_logic_cw.vhd',
21 
    'clock_loc' => '',
22 
    'clock_wrapper' => 'Clock Enables',
23 
    'clock_wrapper_sgadvanced' => '',
24 
    'compilation' => 'NGC Netlist',
25 
    'compilation_lut' => {
26 
      'keys' => [
27 
        'HDL Netlist',
28 
        'Bitstream',
29 
        'NGC Netlist',
30 
      ],
31 
      'values' => [
32 
        'target1',
33 
        'target2',
34 
        'target3',
35 
      ],
36 
    },
37 
    'compilation_target' => 'NGC Netlist',
38 
    'core_generation' => 1,
39 
    'core_generation_sgadvanced' => '',
40 
    'core_is_deployed' => 0,
41 
    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c46e83d2645affbd5',
42 
    'coregen_part_family' => 'virtex6',
43 
    'createTestbench' => 0,
44 
    'create_interface_document' => 'off',
45 
    'dbl_ovrd' => -1,
46 
    'dbl_ovrd_sgadvanced' => '',
47 
    'dcm_info' => {
48 
    },
49 
    'dcm_input_clock_period' => 5,
50 
    'deprecated_control' => 'off',
51 
    'deprecated_control_sgadvanced' => '',
52 
    'design' => 'inout_logic',
53 
    'designFile' => 'inout_logic.vhd',
54 
    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\ML605_ISE13.3\\MySysGen\\PCIe_UserLogic_00.mdl',
55 
    'device' => 'xc6vlx240t-1ff1156',
56 
    'device_speed' => -1,
57 
    'directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
58 
    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
59 
    'entityNamingInstrs' => {
60 
      'nameMap' => undef,
61 
      'namesAlreadyUsed' => {
62 
        'default_clock_driver' => 1,
63 
        'inout_logic_cw' => 1,
64 
      },
65 
    },
66 
    'eval_field' => 0,
67 
    'fileAttributes' => {
68 
      'nonleaf_results.vhd' => {
69 
        'producer' => 'nonleafNetlister',
70 
      },
71 
    },
72 
    'files' => [
73 
      'xlpersistentdff.ngc',
74 
      'synopsis',
75 
      'inout_logic.vhd',
76 
      'xlpersistentdff.ngc',
77 
      'inout_logic_cw.vhd',
78 
      'inout_logic_cw.ucf',
79 
      'inout_logic_cw.xcf',
80 
      'inout_logic_cw.sdc',
81 
      'xst_inout_logic.prj',
82 
      'xst_inout_logic.scr',
83 
      'vcom.do',
84 
      'isim_inout_logic.prj',
85 
      'globals',
86 
      'hdlFiles',
87 
      'inout_logic_cw.xise',
88 
      'inout_logic_cw.gise',
89 
      'inout_logic_cw.sgp',
90 
    ],
91 
    'fxdptinstalled' => 1,
92 
    'generateUsing71FrontEnd' => 1,
93 
    'generating_island_subsystem_handle' => 2084.00048828125,
94 
    'generating_subsystem_handle' => 2084.00048828125,
95 
    'generation_directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
96 
    'has_advanced_control' => 0,
97 
    'hdlDir' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl',
98 
    'hdlKind' => 'vhdl',
99 
    'hdl_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
100 
    'impl_file' => 'ISE Defaults*',
101 
    'incr_netlist' => 'off',
102 
    'incr_netlist_sgadvanced' => '',
103 
    'infoedit' => ' System Generator',
104 
    'isCombinatorial' => 1,
105 
    'isdeployed' => 0,
106 
    'ise_version' => '13.3i',
107 
    'master_sysgen_token_handle' => 2085.00048828125,
108 
    'matlab' => 'C:/Programmi/MATLAB/R2010b',
109 
    'matlab_fixedpoint' => 1,
110 
    'mdlHandle' => 2083.00048828125,
111 
    'mdlPath' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
112 
    'modelDiagnostics' => [
113 
      {
114 
        'count' => 351,
115 
        'isMask' => 0,
116 
        'type' => 'PCIe_UserLogic_00 Total blocks',
117 
      },
118 
      {
119 
        'count' => 4,
120 
        'isMask' => 0,
121 
        'type' => 'DiscretePulseGenerator',
122 
      },
123 
      {
124 
        'count' => 339,
125 
        'isMask' => 0,
126 
        'type' => 'S-Function',
127 
      },
128 
      {
129 
        'count' => 4,
130 
        'isMask' => 0,
131 
        'type' => 'SubSystem',
132 
      },
133 
      {
134 
        'count' => 4,
135 
        'isMask' => 0,
136 
        'type' => 'Terminator',
137 
      },
138 
      {
139 
        'count' => 1,
140 
        'isMask' => 1,
141 
        'type' => 'Xilinx ChipScope Block',
142 
      },
143 
      {
144 
        'count' => 23,
145 
        'isMask' => 1,
146 
        'type' => 'Xilinx Constant Block Block',
147 
      },
148 
      {
149 
        'count' => 1,
150 
        'isMask' => 1,
151 
        'type' => 'Xilinx Counter Block',
152 
      },
153 
      {
154 
        'count' => 44,
155 
        'isMask' => 1,
156 
        'type' => 'Xilinx Gateway In Block',
157 
      },
158 
      {
159 
        'count' => 39,
160 
        'isMask' => 1,
161 
        'type' => 'Xilinx Gateway Out Block',
162 
      },
163 
      {
164 
        'count' => 2,
165 
        'isMask' => 1,
166 
        'type' => 'Xilinx Inverter Block',
167 
      },
168 
      {
169 
        'count' => 1,
170 
        'isMask' => 1,
171 
        'type' => 'Xilinx Logical Block Block',
172 
      },
173 
      {
174 
        'count' => 89,
175 
        'isMask' => 1,
176 
        'type' => 'Xilinx Register Block',
177 
      },
178 
      {
179 
        'count' => 62,
180 
        'isMask' => 1,
181 
        'type' => 'Xilinx Shared Memory Based From Register Block',
182 
      },
183 
      {
184 
        'count' => 62,
185 
        'isMask' => 1,
186 
        'type' => 'Xilinx Shared Memory Based To Register Block',
187 
      },
188 
      {
189 
        'count' => 1,
190 
        'isMask' => 1,
191 
        'type' => 'Xilinx Subsystem Generator Block',
192 
      },
193 
      {
194 
        'count' => 2,
195 
        'isMask' => 1,
196 
        'type' => 'Xilinx System Generator Block',
197 
      },
198 
      {
199 
        'count' => 14,
200 
        'isMask' => 1,
201 
        'type' => 'Xilinx Type Converter Block',
202 
      },
203 
    ],
204 
    'model_globals_initialized' => 1,
205 
    'model_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
206 
    'myxilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
207 
    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
208 
    'ngc_config' => {
209 
      'include_cf' => 1,
210 
      'include_clockwrapper' => 1,
211 
    },
212 
    'ngc_files' => [
213 
      'xlpersistentdff.ngc',
214 
    ],
215 
    'num_sim_cycles' => 1250000000,
216 
    'package' => 'ff1156',
217 
    'part' => 'xc6vlx240t',
218 
    'partFamily' => 'virtex6',
219 
    'port_data_types_enabled' => 1,
220 
    'postgeneration_fcn' => 'xlNGCPostGeneration',
221 
    'preserve_hierarchy' => 0,
222 
    'proj_type' => 'Project Navigator',
223 
    'proj_type_sgadvanced' => '',
224 
    'run_coregen' => 'off',
225 
    'run_coregen_sgadvanced' => '',
226 
    'sample_time_colors_enabled' => 1,
227 
    'sampletimecolors' => 1,
228 
    'sdcFile' => 'inout_logic_cw.sdc',
229 
    'settings_fcn' => 'xlngcsettings',
230 
    'sg_blockgui_xml' => '',
231 
    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
232 
    'sg_list_contents' => '',
233 
    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
234 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
235 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
236 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
237 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
238 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
239 
fprintf(\'\',\'COMMENT: end icon graphics\');
240 
fprintf(\'\',\'COMMENT: begin icon text\');
241 
fprintf(\'\',\'COMMENT: end icon text\');',
242 
    'sg_version' => '',
243 
    'sggui_pos' => '-1,-1,-1,-1',
244 
    'simulation_island_subsystem_handle' => 2084.00048828125,
245 
    'simulinkName' => 'parking_lot',
246 
    'simulink_accelerator_running' => 0,
247 
    'simulink_debugger_running' => 0,
248 
    'simulink_period' => '8e-009',
249 
    'speed' => -1,
250 
    'synth_file' => 'XST Defaults*',
251 
    'synthesisTool' => 'XST',
252 
    'synthesis_language' => 'vhdl',
253 
    'synthesis_tool' => 'XST',
254 
    'synthesis_tool_sgadvanced' => '',
255 
    'sysclk_period' => 5,
256 
    'sysgen' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
257 
    'sysgenRoot' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
258 
    'sysgenTokenSettings' => {
259 
      'Impl_file' => 'ISE Defaults',
260 
      'Impl_file_sgadvanced' => '',
261 
      'Synth_file' => 'XST Defaults',
262 
      'Synth_file_sgadvanced' => '',
263 
      'base_system_period_hardware' => 5,
264 
      'base_system_period_simulink' => '8e-009',
265 
      'block_icon_display' => 'Default',
266 
      'block_type' => 'sysgen',
267 
      'block_version' => '',
268 
      'ce_clr' => 0,
269 
      'clock_loc' => '',
270 
      'clock_wrapper' => 'Clock Enables',
271 
      'clock_wrapper_sgadvanced' => '',
272 
      'compilation' => 'NGC Netlist',
273 
      'compilation_lut' => {
274 
        'keys' => [
275 
          'HDL Netlist',
276 
          'Bitstream',
277 
          'NGC Netlist',
278 
        ],
279 
        'values' => [
280 
          'target1',
281 
          'target2',
282 
          'target3',
283 
        ],
284 
      },
285 
      'core_generation' => 1,
286 
      'core_generation_sgadvanced' => '',
287 
      'coregen_part_family' => 'virtex6',
288 
      'create_interface_document' => 'off',
289 
      'dbl_ovrd' => -1,
290 
      'dbl_ovrd_sgadvanced' => '',
291 
      'dcm_input_clock_period' => 5,
292 
      'deprecated_control' => 'off',
293 
      'deprecated_control_sgadvanced' => '',
294 
      'directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
295 
      'eval_field' => 0,
296 
      'has_advanced_control' => 0,
297 
      'impl_file' => 'ISE Defaults*',
298 
      'incr_netlist' => 'off',
299 
      'incr_netlist_sgadvanced' => '',
300 
      'infoedit' => ' System Generator',
301 
      'master_sysgen_token_handle' => 2085.00048828125,
302 
      'ngc_config' => {
303 
        'include_cf' => 1,
304 
        'include_clockwrapper' => 1,
305 
      },
306 
      'package' => 'ff1156',
307 
      'part' => 'xc6vlx240t',
308 
      'postgeneration_fcn' => 'xlNGCPostGeneration',
309 
      'preserve_hierarchy' => 0,
310 
      'proj_type' => 'Project Navigator',
311 
      'proj_type_sgadvanced' => '',
312 
      'run_coregen' => 'off',
313 
      'run_coregen_sgadvanced' => '',
314 
      'settings_fcn' => 'xlngcsettings',
315 
      'sg_blockgui_xml' => '',
316 
      'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
317 
      'sg_list_contents' => '',
318 
      'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
319 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
320 
patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
321 
patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
322 
patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
323 
patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
324 
fprintf(\'\',\'COMMENT: end icon graphics\');
325 
fprintf(\'\',\'COMMENT: begin icon text\');
326 
fprintf(\'\',\'COMMENT: end icon text\');',
327 
      'sggui_pos' => '-1,-1,-1,-1',
328 
      'simulation_island_subsystem_handle' => 2084.00048828125,
329 
      'simulink_period' => '8e-009',
330 
      'speed' => -1,
331 
      'synth_file' => 'XST Defaults*',
332 
      'synthesis_language' => 'vhdl',
333 
      'synthesis_tool' => 'XST',
334 
      'synthesis_tool_sgadvanced' => '',
335 
      'sysclk_period' => 5,
336 
      'testbench' => 0,
337 
      'testbench_sgadvanced' => '',
338 
      'trim_vbits' => 1,
339 
      'trim_vbits_sgadvanced' => '',
340 
      'xilinx_device' => 'xc6vlx240t-1ff1156',
341 
      'xilinxfamily' => 'virtex6',
342 
    },
343 
    'sysgen_Root' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen',
344 
    'systemClockPeriod' => 5,
345 
    'tempdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
346 
    'testbench' => 0,
347 
    'testbench_sgadvanced' => '',
348 
    'tmpDir' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/sysgen',
349 
    'trim_vbits' => 1,
350 
    'trim_vbits_sgadvanced' => '',
351 
    'ucfFile' => 'inout_logic_cw.ucf',
352 
    'use_ce_syn_keep' => 1,
353 
    'use_strict_names' => 1,
354 
    'user_tips_enabled' => 0,
355 
    'usertemp' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
356 
    'using71Netlister' => 1,
357 
    'verilog_files' => [
358 
      'conv_pkg.v',
359 
      'synth_reg.v',
360 
      'synth_reg_w_init.v',
361 
      'convert_type.v',
362 
    ],
363 
    'version' => '',
364 
    'vhdl_files' => [
365 
      'conv_pkg.vhd',
366 
      'synth_reg.vhd',
367 
      'synth_reg_w_init.vhd',
368 
    ],
369 
    'vsimtime' => '6875000275.000000 ns',
370 
    'xcfFile' => 'inout_logic_cw.xcf',
371 
    'xilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
372 
    'xilinx_device' => 'xc6vlx240t-1ff1156',
373 
    'xilinx_family' => 'virtex6',
374 
    'xilinx_package' => 'ff1156',
375 
    'xilinx_part' => 'xc6vlx240t',
376 
    'xilinxdevice' => 'xc6vlx240t-1ff1156',
377 
    'xilinxfamily' => 'virtex6',
378 
    'xilinxpart' => 'xc6vlx240t',
379 
  },
380 
  'entityName' => '',
381 
  'nets' => {
382 
    '.clk' => {
383 
      'hdlType' => 'std_logic',
384 
      'width' => 1,
385 
    },
386 
    '.debug_in_1i' => {
387 
      'hdlType' => 'std_logic_vector(31 downto 0)',
388 
      'width' => 32,
389 
    },
390 
    '.debug_in_2i' => {
391 
      'hdlType' => 'std_logic_vector(31 downto 0)',
392 
      'width' => 32,
393 
    },
394 
    '.debug_in_3i' => {
395 
      'hdlType' => 'std_logic_vector(31 downto 0)',
396 
      'width' => 32,
397 
    },
398 
    '.debug_in_4i' => {
399 
      'hdlType' => 'std_logic_vector(31 downto 0)',
400 
      'width' => 32,
401 
    },
402 
    '.dma_host2board_busy' => {
403 
      'hdlType' => 'std_logic',
404 
      'width' => 1,
405 
    },
406 
    '.dma_host2board_done' => {
407 
      'hdlType' => 'std_logic',
408 
      'width' => 1,
409 
    },
410 
    '.reg01_td' => {
411 
      'hdlType' => 'std_logic_vector(31 downto 0)',
412 
      'width' => 32,
413 
    },
414 
    '.reg01_tv' => {
415 
      'hdlType' => 'std_logic',
416 
      'width' => 1,
417 
    },
418 
    '.reg02_td' => {
419 
      'hdlType' => 'std_logic_vector(31 downto 0)',
420 
      'width' => 32,
421 
    },
422 
    '.reg02_tv' => {
423 
      'hdlType' => 'std_logic',
424 
      'width' => 1,
425 
    },
426 
    '.reg03_td' => {
427 
      'hdlType' => 'std_logic_vector(31 downto 0)',
428 
      'width' => 32,
429 
    },
430 
    '.reg03_tv' => {
431 
      'hdlType' => 'std_logic',
432 
      'width' => 1,
433 
    },
434 
    '.reg04_td' => {
435 
      'hdlType' => 'std_logic_vector(31 downto 0)',
436 
      'width' => 32,
437 
    },
438 
    '.reg04_tv' => {
439 
      'hdlType' => 'std_logic',
440 
      'width' => 1,
441 
    },
442 
    '.reg05_td' => {
443 
      'hdlType' => 'std_logic_vector(31 downto 0)',
444 
      'width' => 32,
445 
    },
446 
    '.reg05_tv' => {
447 
      'hdlType' => 'std_logic',
448 
      'width' => 1,
449 
    },
450 
    '.reg06_td' => {
451 
      'hdlType' => 'std_logic_vector(31 downto 0)',
452 
      'width' => 32,
453 
    },
454 
    '.reg06_tv' => {
455 
      'hdlType' => 'std_logic',
456 
      'width' => 1,
457 
    },
458 
    '.reg07_td' => {
459 
      'hdlType' => 'std_logic_vector(31 downto 0)',
460 
      'width' => 32,
461 
    },
462 
    '.reg07_tv' => {
463 
      'hdlType' => 'std_logic',
464 
      'width' => 1,
465 
    },
466 
    '.reg08_td' => {
467 
      'hdlType' => 'std_logic_vector(31 downto 0)',
468 
      'width' => 32,
469 
    },
470 
    '.reg08_tv' => {
471 
      'hdlType' => 'std_logic',
472 
      'width' => 1,
473 
    },
474 
    '.reg09_td' => {
475 
      'hdlType' => 'std_logic_vector(31 downto 0)',
476 
      'width' => 32,
477 
    },
478 
    '.reg09_tv' => {
479 
      'hdlType' => 'std_logic',
480 
      'width' => 1,
481 
    },
482 
    '.reg10_td' => {
483 
      'hdlType' => 'std_logic_vector(31 downto 0)',
484 
      'width' => 32,
485 
    },
486 
    '.reg10_tv' => {
487 
      'hdlType' => 'std_logic',
488 
      'width' => 1,
489 
    },
490 
    '.reg11_td' => {
491 
      'hdlType' => 'std_logic_vector(31 downto 0)',
492 
      'width' => 32,
493 
    },
494 
    '.reg11_tv' => {
495 
      'hdlType' => 'std_logic',
496 
      'width' => 1,
497 
    },
498 
    '.reg12_td' => {
499 
      'hdlType' => 'std_logic_vector(31 downto 0)',
500 
      'width' => 32,
501 
    },
502 
    '.reg12_tv' => {
503 
      'hdlType' => 'std_logic',
504 
      'width' => 1,
505 
    },
506 
    '.reg13_td' => {
507 
      'hdlType' => 'std_logic_vector(31 downto 0)',
508 
      'width' => 32,
509 
    },
510 
    '.reg13_tv' => {
511 
      'hdlType' => 'std_logic',
512 
      'width' => 1,
513 
    },
514 
    '.reg14_td' => {
515 
      'hdlType' => 'std_logic_vector(31 downto 0)',
516 
      'width' => 32,
517 
    },
518 
    '.reg14_tv' => {
519 
      'hdlType' => 'std_logic',
520 
      'width' => 1,
521 
    },
522 
    'from_register1.data_out' => {
523 
      'hdlType' => 'std_logic',
524 
      'width' => 1,
525 
    },
526 
    'from_register10.data_out' => {
527 
      'hdlType' => 'std_logic_vector(31 downto 0)',
528 
      'width' => 32,
529 
    },
530 
    'from_register11.data_out' => {
531 
      'hdlType' => 'std_logic_vector(31 downto 0)',
532 
      'width' => 32,
533 
    },
534 
    'from_register12.data_out' => {
535 
      'hdlType' => 'std_logic',
536 
      'width' => 1,
537 
    },
538 
    'from_register13.data_out' => {
539 
      'hdlType' => 'std_logic_vector(31 downto 0)',
540 
      'width' => 32,
541 
    },
542 
    'from_register14.data_out' => {
543 
      'hdlType' => 'std_logic',
544 
      'width' => 1,
545 
    },
546 
    'from_register15.data_out' => {
547 
      'hdlType' => 'std_logic_vector(31 downto 0)',
548 
      'width' => 32,
549 
    },
550 
    'from_register16.data_out' => {
551 
      'hdlType' => 'std_logic',
552 
      'width' => 1,
553 
    },
554 
    'from_register17.data_out' => {
555 
      'hdlType' => 'std_logic_vector(31 downto 0)',
556 
      'width' => 32,
557 
    },
558 
    'from_register18.data_out' => {
559 
      'hdlType' => 'std_logic',
560 
      'width' => 1,
561 
    },
562 
    'from_register19.data_out' => {
563 
      'hdlType' => 'std_logic_vector(31 downto 0)',
564 
      'width' => 32,
565 
    },
566 
    'from_register2.data_out' => {
567 
      'hdlType' => 'std_logic',
568 
      'width' => 1,
569 
    },
570 
    'from_register20.data_out' => {
571 
      'hdlType' => 'std_logic',
572 
      'width' => 1,
573 
    },
574 
    'from_register21.data_out' => {
575 
      'hdlType' => 'std_logic_vector(31 downto 0)',
576 
      'width' => 32,
577 
    },
578 
    'from_register22.data_out' => {
579 
      'hdlType' => 'std_logic',
580 
      'width' => 1,
581 
    },
582 
    'from_register23.data_out' => {
583 
      'hdlType' => 'std_logic_vector(31 downto 0)',
584 
      'width' => 32,
585 
    },
586 
    'from_register24.data_out' => {
587 
      'hdlType' => 'std_logic',
588 
      'width' => 1,
589 
    },
590 
    'from_register25.data_out' => {
591 
      'hdlType' => 'std_logic_vector(31 downto 0)',
592 
      'width' => 32,
593 
    },
594 
    'from_register26.data_out' => {
595 
      'hdlType' => 'std_logic',
596 
      'width' => 1,
597 
    },
598 
    'from_register27.data_out' => {
599 
      'hdlType' => 'std_logic_vector(31 downto 0)',
600 
      'width' => 32,
601 
    },
602 
    'from_register28.data_out' => {
603 
      'hdlType' => 'std_logic',
604 
      'width' => 1,
605 
    },
606 
    'from_register3.data_out' => {
607 
      'hdlType' => 'std_logic_vector(31 downto 0)',
608 
      'width' => 32,
609 
    },
610 
    'from_register4.data_out' => {
611 
      'hdlType' => 'std_logic',
612 
      'width' => 1,
613 
    },
614 
    'from_register5.data_out' => {
615 
      'hdlType' => 'std_logic_vector(31 downto 0)',
616 
      'width' => 32,
617 
    },
618 
    'from_register6.data_out' => {
619 
      'hdlType' => 'std_logic',
620 
      'width' => 1,
621 
    },
622 
    'from_register7.data_out' => {
623 
      'hdlType' => 'std_logic_vector(31 downto 0)',
624 
      'width' => 32,
625 
    },
626 
    'from_register8.data_out' => {
627 
      'hdlType' => 'std_logic_vector(31 downto 0)',
628 
      'width' => 32,
629 
    },
630 
    'from_register9.data_out' => {
631 
      'hdlType' => 'std_logic',
632 
      'width' => 1,
633 
    },
634 
    'sysgen_dut.reg01_rd' => {
635 
      'hdlType' => 'std_logic_vector(31 downto 0)',
636 
      'width' => 32,
637 
    },
638 
    'sysgen_dut.reg01_rv' => {
639 
      'hdlType' => 'std_logic',
640 
      'width' => 1,
641 
    },
642 
    'sysgen_dut.reg02_rd' => {
643 
      'hdlType' => 'std_logic_vector(31 downto 0)',
644 
      'width' => 32,
645 
    },
646 
    'sysgen_dut.reg02_rv' => {
647 
      'hdlType' => 'std_logic',
648 
      'width' => 1,
649 
    },
650 
    'sysgen_dut.reg03_rd' => {
651 
      'hdlType' => 'std_logic_vector(31 downto 0)',
652 
      'width' => 32,
653 
    },
654 
    'sysgen_dut.reg03_rv' => {
655 
      'hdlType' => 'std_logic',
656 
      'width' => 1,
657 
    },
658 
    'sysgen_dut.reg04_rd' => {
659 
      'hdlType' => 'std_logic_vector(31 downto 0)',
660 
      'width' => 32,
661 
    },
662 
    'sysgen_dut.reg04_rv' => {
663 
      'hdlType' => 'std_logic',
664 
      'width' => 1,
665 
    },
666 
    'sysgen_dut.reg05_rd' => {
667 
      'hdlType' => 'std_logic_vector(31 downto 0)',
668 
      'width' => 32,
669 
    },
670 
    'sysgen_dut.reg05_rv' => {
671 
      'hdlType' => 'std_logic',
672 
      'width' => 1,
673 
    },
674 
    'sysgen_dut.reg06_rd' => {
675 
      'hdlType' => 'std_logic_vector(31 downto 0)',
676 
      'width' => 32,
677 
    },
678 
    'sysgen_dut.reg06_rv' => {
679 
      'hdlType' => 'std_logic',
680 
      'width' => 1,
681 
    },
682 
    'sysgen_dut.reg07_rd' => {
683 
      'hdlType' => 'std_logic_vector(31 downto 0)',
684 
      'width' => 32,
685 
    },
686 
    'sysgen_dut.reg07_rv' => {
687 
      'hdlType' => 'std_logic',
688 
      'width' => 1,
689 
    },
690 
    'sysgen_dut.reg08_rd' => {
691 
      'hdlType' => 'std_logic_vector(31 downto 0)',
692 
      'width' => 32,
693 
    },
694 
    'sysgen_dut.reg08_rv' => {
695 
      'hdlType' => 'std_logic',
696 
      'width' => 1,
697 
    },
698 
    'sysgen_dut.reg09_rd' => {
699 
      'hdlType' => 'std_logic_vector(31 downto 0)',
700 
      'width' => 32,
701 
    },
702 
    'sysgen_dut.reg09_rv' => {
703 
      'hdlType' => 'std_logic',
704 
      'width' => 1,
705 
    },
706 
    'sysgen_dut.reg10_rd' => {
707 
      'hdlType' => 'std_logic_vector(31 downto 0)',
708 
      'width' => 32,
709 
    },
710 
    'sysgen_dut.reg10_rv' => {
711 
      'hdlType' => 'std_logic',
712 
      'width' => 1,
713 
    },
714 
    'sysgen_dut.reg11_rd' => {
715 
      'hdlType' => 'std_logic_vector(31 downto 0)',
716 
      'width' => 32,
717 
    },
718 
    'sysgen_dut.reg11_rv' => {
719 
      'hdlType' => 'std_logic',
720 
      'width' => 1,
721 
    },
722 
    'sysgen_dut.reg12_rd' => {
723 
      'hdlType' => 'std_logic_vector(31 downto 0)',
724 
      'width' => 32,
725 
    },
726 
    'sysgen_dut.reg12_rv' => {
727 
      'hdlType' => 'std_logic',
728 
      'width' => 1,
729 
    },
730 
    'sysgen_dut.reg13_rd' => {
731 
      'hdlType' => 'std_logic_vector(31 downto 0)',
732 
      'width' => 32,
733 
    },
734 
    'sysgen_dut.reg13_rv' => {
735 
      'hdlType' => 'std_logic',
736 
      'width' => 1,
737 
    },
738 
    'sysgen_dut.reg14_rd' => {
739 
      'hdlType' => 'std_logic_vector(31 downto 0)',
740 
      'width' => 32,
741 
    },
742 
    'sysgen_dut.reg14_rv' => {
743 
      'hdlType' => 'std_logic',
744 
      'width' => 1,
745 
    },
746 
    'sysgen_dut.to_register10_ce' => {
747 
      'hdlType' => 'std_logic',
748 
      'width' => 1,
749 
    },
750 
    'sysgen_dut.to_register10_clk' => {
751 
      'hdlType' => 'std_logic',
752 
      'width' => 1,
753 
    },
754 
    'sysgen_dut.to_register10_clr' => {
755 
      'hdlType' => 'std_logic',
756 
      'width' => 1,
757 
    },
758 
    'sysgen_dut.to_register10_data_in' => {
759 
      'hdlType' => 'std_logic',
760 
      'width' => 1,
761 
    },
762 
    'sysgen_dut.to_register10_en' => {
763 
      'hdlType' => 'std_logic',
764 
      'width' => 1,
765 
    },
766 
    'sysgen_dut.to_register11_ce' => {
767 
      'hdlType' => 'std_logic',
768 
      'width' => 1,
769 
    },
770 
    'sysgen_dut.to_register11_clk' => {
771 
      'hdlType' => 'std_logic',
772 
      'width' => 1,
773 
    },
774 
    'sysgen_dut.to_register11_clr' => {
775 
      'hdlType' => 'std_logic',
776 
      'width' => 1,
777 
    },
778 
    'sysgen_dut.to_register11_data_in' => {
779 
      'hdlType' => 'std_logic_vector(31 downto 0)',
780 
      'width' => 32,
781 
    },
782 
    'sysgen_dut.to_register11_en' => {
783 
      'hdlType' => 'std_logic',
784 
      'width' => 1,
785 
    },
786 
    'sysgen_dut.to_register12_ce' => {
787 
      'hdlType' => 'std_logic',
788 
      'width' => 1,
789 
    },
790 
    'sysgen_dut.to_register12_clk' => {
791 
      'hdlType' => 'std_logic',
792 
      'width' => 1,
793 
    },
794 
    'sysgen_dut.to_register12_clr' => {
795 
      'hdlType' => 'std_logic',
796 
      'width' => 1,
797 
    },
798 
    'sysgen_dut.to_register12_data_in' => {
799 
      'hdlType' => 'std_logic',
800 
      'width' => 1,
801 
    },
802 
    'sysgen_dut.to_register12_en' => {
803 
      'hdlType' => 'std_logic',
804 
      'width' => 1,
805 
    },
806 
    'sysgen_dut.to_register13_ce' => {
807 
      'hdlType' => 'std_logic',
808 
      'width' => 1,
809 
    },
810 
    'sysgen_dut.to_register13_clk' => {
811 
      'hdlType' => 'std_logic',
812 
      'width' => 1,
813 
    },
814 
    'sysgen_dut.to_register13_clr' => {
815 
      'hdlType' => 'std_logic',
816 
      'width' => 1,
817 
    },
818 
    'sysgen_dut.to_register13_data_in' => {
819 
      'hdlType' => 'std_logic_vector(31 downto 0)',
820 
      'width' => 32,
821 
    },
822 
    'sysgen_dut.to_register13_en' => {
823 
      'hdlType' => 'std_logic',
824 
      'width' => 1,
825 
    },
826 
    'sysgen_dut.to_register14_ce' => {
827 
      'hdlType' => 'std_logic',
828 
      'width' => 1,
829 
    },
830 
    'sysgen_dut.to_register14_clk' => {
831 
      'hdlType' => 'std_logic',
832 
      'width' => 1,
833 
    },
834 
    'sysgen_dut.to_register14_clr' => {
835 
      'hdlType' => 'std_logic',
836 
      'width' => 1,
837 
    },
838 
    'sysgen_dut.to_register14_data_in' => {
839 
      'hdlType' => 'std_logic',
840 
      'width' => 1,
841 
    },
842 
    'sysgen_dut.to_register14_en' => {
843 
      'hdlType' => 'std_logic',
844 
      'width' => 1,
845 
    },
846 
    'sysgen_dut.to_register15_ce' => {
847 
      'hdlType' => 'std_logic',
848 
      'width' => 1,
849 
    },
850 
    'sysgen_dut.to_register15_clk' => {
851 
      'hdlType' => 'std_logic',
852 
      'width' => 1,
853 
    },
854 
    'sysgen_dut.to_register15_clr' => {
855 
      'hdlType' => 'std_logic',
856 
      'width' => 1,
857 
    },
858 
    'sysgen_dut.to_register15_data_in' => {
859 
      'hdlType' => 'std_logic_vector(31 downto 0)',
860 
      'width' => 32,
861 
    },
862 
    'sysgen_dut.to_register15_en' => {
863 
      'hdlType' => 'std_logic',
864 
      'width' => 1,
865 
    },
866 
    'sysgen_dut.to_register16_ce' => {
867 
      'hdlType' => 'std_logic',
868 
      'width' => 1,
869 
    },
870 
    'sysgen_dut.to_register16_clk' => {
871 
      'hdlType' => 'std_logic',
872 
      'width' => 1,
873 
    },
874 
    'sysgen_dut.to_register16_clr' => {
875 
      'hdlType' => 'std_logic',
876 
      'width' => 1,
877 
    },
878 
    'sysgen_dut.to_register16_data_in' => {
879 
      'hdlType' => 'std_logic',
880 
      'width' => 1,
881 
    },
882 
    'sysgen_dut.to_register16_en' => {
883 
      'hdlType' => 'std_logic',
884 
      'width' => 1,
885 
    },
886 
    'sysgen_dut.to_register17_ce' => {
887 
      'hdlType' => 'std_logic',
888 
      'width' => 1,
889 
    },
890 
    'sysgen_dut.to_register17_clk' => {
891 
      'hdlType' => 'std_logic',
892 
      'width' => 1,
893 
    },
894 
    'sysgen_dut.to_register17_clr' => {
895 
      'hdlType' => 'std_logic',
896 
      'width' => 1,
897 
    },
898 
    'sysgen_dut.to_register17_data_in' => {
899 
      'hdlType' => 'std_logic_vector(31 downto 0)',
900 
      'width' => 32,
901 
    },
902 
    'sysgen_dut.to_register17_en' => {
903 
      'hdlType' => 'std_logic',
904 
      'width' => 1,
905 
    },
906 
    'sysgen_dut.to_register18_ce' => {
907 
      'hdlType' => 'std_logic',
908 
      'width' => 1,
909 
    },
910 
    'sysgen_dut.to_register18_clk' => {
911 
      'hdlType' => 'std_logic',
912 
      'width' => 1,
913 
    },
914 
    'sysgen_dut.to_register18_clr' => {
915 
      'hdlType' => 'std_logic',
916 
      'width' => 1,
917 
    },
918 
    'sysgen_dut.to_register18_data_in' => {
919 
      'hdlType' => 'std_logic',
920 
      'width' => 1,
921 
    },
922 
    'sysgen_dut.to_register18_en' => {
923 
      'hdlType' => 'std_logic',
924 
      'width' => 1,
925 
    },
926 
    'sysgen_dut.to_register19_ce' => {
927 
      'hdlType' => 'std_logic',
928 
      'width' => 1,
929 
    },
930 
    'sysgen_dut.to_register19_clk' => {
931 
      'hdlType' => 'std_logic',
932 
      'width' => 1,
933 
    },
934 
    'sysgen_dut.to_register19_clr' => {
935 
      'hdlType' => 'std_logic',
936 
      'width' => 1,
937 
    },
938 
    'sysgen_dut.to_register19_data_in' => {
939 
      'hdlType' => 'std_logic',
940 
      'width' => 1,
941 
    },
942 
    'sysgen_dut.to_register19_en' => {
943 
      'hdlType' => 'std_logic',
944 
      'width' => 1,
945 
    },
946 
    'sysgen_dut.to_register1_ce' => {
947 
      'hdlType' => 'std_logic',
948 
      'width' => 1,
949 
    },
950 
    'sysgen_dut.to_register1_clk' => {
951 
      'hdlType' => 'std_logic',
952 
      'width' => 1,
953 
    },
954 
    'sysgen_dut.to_register1_clr' => {
955 
      'hdlType' => 'std_logic',
956 
      'width' => 1,
957 
    },
958 
    'sysgen_dut.to_register1_data_in' => {
959 
      'hdlType' => 'std_logic_vector(31 downto 0)',
960 
      'width' => 32,
961 
    },
962 
    'sysgen_dut.to_register1_en' => {
963 
      'hdlType' => 'std_logic',
964 
      'width' => 1,
965 
    },
966 
    'sysgen_dut.to_register20_ce' => {
967 
      'hdlType' => 'std_logic',
968 
      'width' => 1,
969 
    },
970 
    'sysgen_dut.to_register20_clk' => {
971 
      'hdlType' => 'std_logic',
972 
      'width' => 1,
973 
    },
974 
    'sysgen_dut.to_register20_clr' => {
975 
      'hdlType' => 'std_logic',
976 
      'width' => 1,
977 
    },
978 
    'sysgen_dut.to_register20_data_in' => {
979 
      'hdlType' => 'std_logic_vector(31 downto 0)',
980 
      'width' => 32,
981 
    },
982 
    'sysgen_dut.to_register20_en' => {
983 
      'hdlType' => 'std_logic',
984 
      'width' => 1,
985 
    },
986 
    'sysgen_dut.to_register21_ce' => {
987 
      'hdlType' => 'std_logic',
988 
      'width' => 1,
989 
    },
990 
    'sysgen_dut.to_register21_clk' => {
991 
      'hdlType' => 'std_logic',
992 
      'width' => 1,
993 
    },
994 
    'sysgen_dut.to_register21_clr' => {
995 
      'hdlType' => 'std_logic',
996 
      'width' => 1,
997 
    },
998 
    'sysgen_dut.to_register21_data_in' => {
999 
      'hdlType' => 'std_logic',
1000 
      'width' => 1,
1001 
    },
1002 
    'sysgen_dut.to_register21_en' => {
1003 
      'hdlType' => 'std_logic',
1004 
      'width' => 1,
1005 
    },
1006 
    'sysgen_dut.to_register22_ce' => {
1007 
      'hdlType' => 'std_logic',
1008 
      'width' => 1,
1009 
    },
1010 
    'sysgen_dut.to_register22_clk' => {
1011 
      'hdlType' => 'std_logic',
1012 
      'width' => 1,
1013 
    },
1014 
    'sysgen_dut.to_register22_clr' => {
1015 
      'hdlType' => 'std_logic',
1016 
      'width' => 1,
1017 
    },
1018 
    'sysgen_dut.to_register22_data_in' => {
1019 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1020 
      'width' => 32,
1021 
    },
1022 
    'sysgen_dut.to_register22_en' => {
1023 
      'hdlType' => 'std_logic',
1024 
      'width' => 1,
1025 
    },
1026 
    'sysgen_dut.to_register23_ce' => {
1027 
      'hdlType' => 'std_logic',
1028 
      'width' => 1,
1029 
    },
1030 
    'sysgen_dut.to_register23_clk' => {
1031 
      'hdlType' => 'std_logic',
1032 
      'width' => 1,
1033 
    },
1034 
    'sysgen_dut.to_register23_clr' => {
1035 
      'hdlType' => 'std_logic',
1036 
      'width' => 1,
1037 
    },
1038 
    'sysgen_dut.to_register23_data_in' => {
1039 
      'hdlType' => 'std_logic',
1040 
      'width' => 1,
1041 
    },
1042 
    'sysgen_dut.to_register23_en' => {
1043 
      'hdlType' => 'std_logic',
1044 
      'width' => 1,
1045 
    },
1046 
    'sysgen_dut.to_register24_ce' => {
1047 
      'hdlType' => 'std_logic',
1048 
      'width' => 1,
1049 
    },
1050 
    'sysgen_dut.to_register24_clk' => {
1051 
      'hdlType' => 'std_logic',
1052 
      'width' => 1,
1053 
    },
1054 
    'sysgen_dut.to_register24_clr' => {
1055 
      'hdlType' => 'std_logic',
1056 
      'width' => 1,
1057 
    },
1058 
    'sysgen_dut.to_register24_data_in' => {
1059 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1060 
      'width' => 32,
1061 
    },
1062 
    'sysgen_dut.to_register24_en' => {
1063 
      'hdlType' => 'std_logic',
1064 
      'width' => 1,
1065 
    },
1066 
    'sysgen_dut.to_register25_ce' => {
1067 
      'hdlType' => 'std_logic',
1068 
      'width' => 1,
1069 
    },
1070 
    'sysgen_dut.to_register25_clk' => {
1071 
      'hdlType' => 'std_logic',
1072 
      'width' => 1,
1073 
    },
1074 
    'sysgen_dut.to_register25_clr' => {
1075 
      'hdlType' => 'std_logic',
1076 
      'width' => 1,
1077 
    },
1078 
    'sysgen_dut.to_register25_data_in' => {
1079 
      'hdlType' => 'std_logic',
1080 
      'width' => 1,
1081 
    },
1082 
    'sysgen_dut.to_register25_en' => {
1083 
      'hdlType' => 'std_logic',
1084 
      'width' => 1,
1085 
    },
1086 
    'sysgen_dut.to_register26_ce' => {
1087 
      'hdlType' => 'std_logic',
1088 
      'width' => 1,
1089 
    },
1090 
    'sysgen_dut.to_register26_clk' => {
1091 
      'hdlType' => 'std_logic',
1092 
      'width' => 1,
1093 
    },
1094 
    'sysgen_dut.to_register26_clr' => {
1095 
      'hdlType' => 'std_logic',
1096 
      'width' => 1,
1097 
    },
1098 
    'sysgen_dut.to_register26_data_in' => {
1099 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1100 
      'width' => 32,
1101 
    },
1102 
    'sysgen_dut.to_register26_en' => {
1103 
      'hdlType' => 'std_logic',
1104 
      'width' => 1,
1105 
    },
1106 
    'sysgen_dut.to_register27_ce' => {
1107 
      'hdlType' => 'std_logic',
1108 
      'width' => 1,
1109 
    },
1110 
    'sysgen_dut.to_register27_clk' => {
1111 
      'hdlType' => 'std_logic',
1112 
      'width' => 1,
1113 
    },
1114 
    'sysgen_dut.to_register27_clr' => {
1115 
      'hdlType' => 'std_logic',
1116 
      'width' => 1,
1117 
    },
1118 
    'sysgen_dut.to_register27_data_in' => {
1119 
      'hdlType' => 'std_logic',
1120 
      'width' => 1,
1121 
    },
1122 
    'sysgen_dut.to_register27_en' => {
1123 
      'hdlType' => 'std_logic',
1124 
      'width' => 1,
1125 
    },
1126 
    'sysgen_dut.to_register28_ce' => {
1127 
      'hdlType' => 'std_logic',
1128 
      'width' => 1,
1129 
    },
1130 
    'sysgen_dut.to_register28_clk' => {
1131 
      'hdlType' => 'std_logic',
1132 
      'width' => 1,
1133 
    },
1134 
    'sysgen_dut.to_register28_clr' => {
1135 
      'hdlType' => 'std_logic',
1136 
      'width' => 1,
1137 
    },
1138 
    'sysgen_dut.to_register28_data_in' => {
1139 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1140 
      'width' => 32,
1141 
    },
1142 
    'sysgen_dut.to_register28_en' => {
1143 
      'hdlType' => 'std_logic',
1144 
      'width' => 1,
1145 
    },
1146 
    'sysgen_dut.to_register29_ce' => {
1147 
      'hdlType' => 'std_logic',
1148 
      'width' => 1,
1149 
    },
1150 
    'sysgen_dut.to_register29_clk' => {
1151 
      'hdlType' => 'std_logic',
1152 
      'width' => 1,
1153 
    },
1154 
    'sysgen_dut.to_register29_clr' => {
1155 
      'hdlType' => 'std_logic',
1156 
      'width' => 1,
1157 
    },
1158 
    'sysgen_dut.to_register29_data_in' => {
1159 
      'hdlType' => 'std_logic',
1160 
      'width' => 1,
1161 
    },
1162 
    'sysgen_dut.to_register29_en' => {
1163 
      'hdlType' => 'std_logic',
1164 
      'width' => 1,
1165 
    },
1166 
    'sysgen_dut.to_register2_ce' => {
1167 
      'hdlType' => 'std_logic',
1168 
      'width' => 1,
1169 
    },
1170 
    'sysgen_dut.to_register2_clk' => {
1171 
      'hdlType' => 'std_logic',
1172 
      'width' => 1,
1173 
    },
1174 
    'sysgen_dut.to_register2_clr' => {
1175 
      'hdlType' => 'std_logic',
1176 
      'width' => 1,
1177 
    },
1178 
    'sysgen_dut.to_register2_data_in' => {
1179 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1180 
      'width' => 32,
1181 
    },
1182 
    'sysgen_dut.to_register2_en' => {
1183 
      'hdlType' => 'std_logic',
1184 
      'width' => 1,
1185 
    },
1186 
    'sysgen_dut.to_register30_ce' => {
1187 
      'hdlType' => 'std_logic',
1188 
      'width' => 1,
1189 
    },
1190 
    'sysgen_dut.to_register30_clk' => {
1191 
      'hdlType' => 'std_logic',
1192 
      'width' => 1,
1193 
    },
1194 
    'sysgen_dut.to_register30_clr' => {
1195 
      'hdlType' => 'std_logic',
1196 
      'width' => 1,
1197 
    },
1198 
    'sysgen_dut.to_register30_data_in' => {
1199 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1200 
      'width' => 32,
1201 
    },
1202 
    'sysgen_dut.to_register30_en' => {
1203 
      'hdlType' => 'std_logic',
1204 
      'width' => 1,
1205 
    },
1206 
    'sysgen_dut.to_register31_ce' => {
1207 
      'hdlType' => 'std_logic',
1208 
      'width' => 1,
1209 
    },
1210 
    'sysgen_dut.to_register31_clk' => {
1211 
      'hdlType' => 'std_logic',
1212 
      'width' => 1,
1213 
    },
1214 
    'sysgen_dut.to_register31_clr' => {
1215 
      'hdlType' => 'std_logic',
1216 
      'width' => 1,
1217 
    },
1218 
    'sysgen_dut.to_register31_data_in' => {
1219 
      'hdlType' => 'std_logic',
1220 
      'width' => 1,
1221 
    },
1222 
    'sysgen_dut.to_register31_en' => {
1223 
      'hdlType' => 'std_logic',
1224 
      'width' => 1,
1225 
    },
1226 
    'sysgen_dut.to_register32_ce' => {
1227 
      'hdlType' => 'std_logic',
1228 
      'width' => 1,
1229 
    },
1230 
    'sysgen_dut.to_register32_clk' => {
1231 
      'hdlType' => 'std_logic',
1232 
      'width' => 1,
1233 
    },
1234 
    'sysgen_dut.to_register32_clr' => {
1235 
      'hdlType' => 'std_logic',
1236 
      'width' => 1,
1237 
    },
1238 
    'sysgen_dut.to_register32_data_in' => {
1239 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1240 
      'width' => 32,
1241 
    },
1242 
    'sysgen_dut.to_register32_en' => {
1243 
      'hdlType' => 'std_logic',
1244 
      'width' => 1,
1245 
    },
1246 
    'sysgen_dut.to_register33_ce' => {
1247 
      'hdlType' => 'std_logic',
1248 
      'width' => 1,
1249 
    },
1250 
    'sysgen_dut.to_register33_clk' => {
1251 
      'hdlType' => 'std_logic',
1252 
      'width' => 1,
1253 
    },
1254 
    'sysgen_dut.to_register33_clr' => {
1255 
      'hdlType' => 'std_logic',
1256 
      'width' => 1,
1257 
    },
1258 
    'sysgen_dut.to_register33_data_in' => {
1259 
      'hdlType' => 'std_logic',
1260 
      'width' => 1,
1261 
    },
1262 
    'sysgen_dut.to_register33_en' => {
1263 
      'hdlType' => 'std_logic',
1264 
      'width' => 1,
1265 
    },
1266 
    'sysgen_dut.to_register34_ce' => {
1267 
      'hdlType' => 'std_logic',
1268 
      'width' => 1,
1269 
    },
1270 
    'sysgen_dut.to_register34_clk' => {
1271 
      'hdlType' => 'std_logic',
1272 
      'width' => 1,
1273 
    },
1274 
    'sysgen_dut.to_register34_clr' => {
1275 
      'hdlType' => 'std_logic',
1276 
      'width' => 1,
1277 
    },
1278 
    'sysgen_dut.to_register34_data_in' => {
1279 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1280 
      'width' => 32,
1281 
    },
1282 
    'sysgen_dut.to_register34_en' => {
1283 
      'hdlType' => 'std_logic',
1284 
      'width' => 1,
1285 
    },
1286 
    'sysgen_dut.to_register3_ce' => {
1287 
      'hdlType' => 'std_logic',
1288 
      'width' => 1,
1289 
    },
1290 
    'sysgen_dut.to_register3_clk' => {
1291 
      'hdlType' => 'std_logic',
1292 
      'width' => 1,
1293 
    },
1294 
    'sysgen_dut.to_register3_clr' => {
1295 
      'hdlType' => 'std_logic',
1296 
      'width' => 1,
1297 
    },
1298 
    'sysgen_dut.to_register3_data_in' => {
1299 
      'hdlType' => 'std_logic',
1300 
      'width' => 1,
1301 
    },
1302 
    'sysgen_dut.to_register3_en' => {
1303 
      'hdlType' => 'std_logic',
1304 
      'width' => 1,
1305 
    },
1306 
    'sysgen_dut.to_register4_ce' => {
1307 
      'hdlType' => 'std_logic',
1308 
      'width' => 1,
1309 
    },
1310 
    'sysgen_dut.to_register4_clk' => {
1311 
      'hdlType' => 'std_logic',
1312 
      'width' => 1,
1313 
    },
1314 
    'sysgen_dut.to_register4_clr' => {
1315 
      'hdlType' => 'std_logic',
1316 
      'width' => 1,
1317 
    },
1318 
    'sysgen_dut.to_register4_data_in' => {
1319 
      'hdlType' => 'std_logic',
1320 
      'width' => 1,
1321 
    },
1322 
    'sysgen_dut.to_register4_en' => {
1323 
      'hdlType' => 'std_logic',
1324 
      'width' => 1,
1325 
    },
1326 
    'sysgen_dut.to_register5_ce' => {
1327 
      'hdlType' => 'std_logic',
1328 
      'width' => 1,
1329 
    },
1330 
    'sysgen_dut.to_register5_clk' => {
1331 
      'hdlType' => 'std_logic',
1332 
      'width' => 1,
1333 
    },
1334 
    'sysgen_dut.to_register5_clr' => {
1335 
      'hdlType' => 'std_logic',
1336 
      'width' => 1,
1337 
    },
1338 
    'sysgen_dut.to_register5_data_in' => {
1339 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1340 
      'width' => 32,
1341 
    },
1342 
    'sysgen_dut.to_register5_en' => {
1343 
      'hdlType' => 'std_logic',
1344 
      'width' => 1,
1345 
    },
1346 
    'sysgen_dut.to_register6_ce' => {
1347 
      'hdlType' => 'std_logic',
1348 
      'width' => 1,
1349 
    },
1350 
    'sysgen_dut.to_register6_clk' => {
1351 
      'hdlType' => 'std_logic',
1352 
      'width' => 1,
1353 
    },
1354 
    'sysgen_dut.to_register6_clr' => {
1355 
      'hdlType' => 'std_logic',
1356 
      'width' => 1,
1357 
    },
1358 
    'sysgen_dut.to_register6_data_in' => {
1359 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1360 
      'width' => 32,
1361 
    },
1362 
    'sysgen_dut.to_register6_en' => {
1363 
      'hdlType' => 'std_logic',
1364 
      'width' => 1,
1365 
    },
1366 
    'sysgen_dut.to_register7_ce' => {
1367 
      'hdlType' => 'std_logic',
1368 
      'width' => 1,
1369 
    },
1370 
    'sysgen_dut.to_register7_clk' => {
1371 
      'hdlType' => 'std_logic',
1372 
      'width' => 1,
1373 
    },
1374 
    'sysgen_dut.to_register7_clr' => {
1375 
      'hdlType' => 'std_logic',
1376 
      'width' => 1,
1377 
    },
1378 
    'sysgen_dut.to_register7_data_in' => {
1379 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1380 
      'width' => 32,
1381 
    },
1382 
    'sysgen_dut.to_register7_en' => {
1383 
      'hdlType' => 'std_logic',
1384 
      'width' => 1,
1385 
    },
1386 
    'sysgen_dut.to_register8_ce' => {
1387 
      'hdlType' => 'std_logic',
1388 
      'width' => 1,
1389 
    },
1390 
    'sysgen_dut.to_register8_clk' => {
1391 
      'hdlType' => 'std_logic',
1392 
      'width' => 1,
1393 
    },
1394 
    'sysgen_dut.to_register8_clr' => {
1395 
      'hdlType' => 'std_logic',
1396 
      'width' => 1,
1397 
    },
1398 
    'sysgen_dut.to_register8_data_in' => {
1399 
      'hdlType' => 'std_logic',
1400 
      'width' => 1,
1401 
    },
1402 
    'sysgen_dut.to_register8_en' => {
1403 
      'hdlType' => 'std_logic',
1404 
      'width' => 1,
1405 
    },
1406 
    'sysgen_dut.to_register9_ce' => {
1407 
      'hdlType' => 'std_logic',
1408 
      'width' => 1,
1409 
    },
1410 
    'sysgen_dut.to_register9_clk' => {
1411 
      'hdlType' => 'std_logic',
1412 
      'width' => 1,
1413 
    },
1414 
    'sysgen_dut.to_register9_clr' => {
1415 
      'hdlType' => 'std_logic',
1416 
      'width' => 1,
1417 
    },
1418 
    'sysgen_dut.to_register9_data_in' => {
1419 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1420 
      'width' => 32,
1421 
    },
1422 
    'sysgen_dut.to_register9_en' => {
1423 
      'hdlType' => 'std_logic',
1424 
      'width' => 1,
1425 
    },
1426 
    'to_register1.dout' => {
1427 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1428 
      'width' => 32,
1429 
    },
1430 
    'to_register10.dout' => {
1431 
      'hdlType' => 'std_logic',
1432 
      'width' => 1,
1433 
    },
1434 
    'to_register11.dout' => {
1435 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1436 
      'width' => 32,
1437 
    },
1438 
    'to_register12.dout' => {
1439 
      'hdlType' => 'std_logic',
1440 
      'width' => 1,
1441 
    },
1442 
    'to_register13.dout' => {
1443 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1444 
      'width' => 32,
1445 
    },
1446 
    'to_register14.dout' => {
1447 
      'hdlType' => 'std_logic',
1448 
      'width' => 1,
1449 
    },
1450 
    'to_register15.dout' => {
1451 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1452 
      'width' => 32,
1453 
    },
1454 
    'to_register16.dout' => {
1455 
      'hdlType' => 'std_logic',
1456 
      'width' => 1,
1457 
    },
1458 
    'to_register17.dout' => {
1459 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1460 
      'width' => 32,
1461 
    },
1462 
    'to_register18.dout' => {
1463 
      'hdlType' => 'std_logic',
1464 
      'width' => 1,
1465 
    },
1466 
    'to_register19.dout' => {
1467 
      'hdlType' => 'std_logic',
1468 
      'width' => 1,
1469 
    },
1470 
    'to_register2.dout' => {
1471 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1472 
      'width' => 32,
1473 
    },
1474 
    'to_register20.dout' => {
1475 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1476 
      'width' => 32,
1477 
    },
1478 
    'to_register21.dout' => {
1479 
      'hdlType' => 'std_logic',
1480 
      'width' => 1,
1481 
    },
1482 
    'to_register22.dout' => {
1483 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1484 
      'width' => 32,
1485 
    },
1486 
    'to_register23.dout' => {
1487 
      'hdlType' => 'std_logic',
1488 
      'width' => 1,
1489 
    },
1490 
    'to_register24.dout' => {
1491 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1492 
      'width' => 32,
1493 
    },
1494 
    'to_register25.dout' => {
1495 
      'hdlType' => 'std_logic',
1496 
      'width' => 1,
1497 
    },
1498 
    'to_register26.dout' => {
1499 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1500 
      'width' => 32,
1501 
    },
1502 
    'to_register27.dout' => {
1503 
      'hdlType' => 'std_logic',
1504 
      'width' => 1,
1505 
    },
1506 
    'to_register28.dout' => {
1507 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1508 
      'width' => 32,
1509 
    },
1510 
    'to_register29.dout' => {
1511 
      'hdlType' => 'std_logic',
1512 
      'width' => 1,
1513 
    },
1514 
    'to_register3.dout' => {
1515 
      'hdlType' => 'std_logic',
1516 
      'width' => 1,
1517 
    },
1518 
    'to_register30.dout' => {
1519 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1520 
      'width' => 32,
1521 
    },
1522 
    'to_register31.dout' => {
1523 
      'hdlType' => 'std_logic',
1524 
      'width' => 1,
1525 
    },
1526 
    'to_register32.dout' => {
1527 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1528 
      'width' => 32,
1529 
    },
1530 
    'to_register33.dout' => {
1531 
      'hdlType' => 'std_logic',
1532 
      'width' => 1,
1533 
    },
1534 
    'to_register34.dout' => {
1535 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1536 
      'width' => 32,
1537 
    },
1538 
    'to_register4.dout' => {
1539 
      'hdlType' => 'std_logic',
1540 
      'width' => 1,
1541 
    },
1542 
    'to_register5.dout' => {
1543 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1544 
      'width' => 32,
1545 
    },
1546 
    'to_register6.dout' => {
1547 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1548 
      'width' => 32,
1549 
    },
1550 
    'to_register7.dout' => {
1551 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1552 
      'width' => 32,
1553 
    },
1554 
    'to_register8.dout' => {
1555 
      'hdlType' => 'std_logic',
1556 
      'width' => 1,
1557 
    },
1558 
    'to_register9.dout' => {
1559 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1560 
      'width' => 32,
1561 
    },
1562 
  },
1563 
  'subblocks' => {
1564 
    'debug_in_1i' => {
1565 
      'connections' => {
1566 
        'debug_in_1i' => '.debug_in_1i',
1567 
      },
1568 
      'entity' => {
1569 
        'attributes' => {
1570 
          'entityAlreadyNetlisted' => 1,
1571 
          'isGateway' => 1,
1572 
          'is_floating_block' => 1,
1573 
        },
1574 
        'entityName' => 'debug_in_1i',
1575 
        'ports' => {
1576 
          'debug_in_1i' => {
1577 
            'attributes' => {
1578 
              'bin_pt' => 0,
1579 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
1580 
              'is_floating_block' => 1,
1581 
              'is_gateway_port' => 1,
1582 
              'must_be_hdl_vector' => 1,
1583 
              'period' => 1,
1584 
              'port_id' => 0,
1585 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i/debug_in_1i',
1586 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i',
1587 
              'timingConstraint' => 'none',
1588 
              'type' => 'UFix_32_0',
1589 
            },
1590 
            'direction' => 'out',
1591 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1592 
            'width' => 32,
1593 
          },
1594 
        },
1595 
      },
1596 
      'entityName' => 'debug_in_1i',
1597 
    },
1598 
    'debug_in_2i' => {
1599 
      'connections' => {
1600 
        'debug_in_2i' => '.debug_in_2i',
1601 
      },
1602 
      'entity' => {
1603 
        'attributes' => {
1604 
          'entityAlreadyNetlisted' => 1,
1605 
          'isGateway' => 1,
1606 
          'is_floating_block' => 1,
1607 
        },
1608 
        'entityName' => 'debug_in_2i',
1609 
        'ports' => {
1610 
          'debug_in_2i' => {
1611 
            'attributes' => {
1612 
              'bin_pt' => 0,
1613 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
1614 
              'is_floating_block' => 1,
1615 
              'is_gateway_port' => 1,
1616 
              'must_be_hdl_vector' => 1,
1617 
              'period' => 1,
1618 
              'port_id' => 0,
1619 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i/debug_in_2i',
1620 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i',
1621 
              'timingConstraint' => 'none',
1622 
              'type' => 'UFix_32_0',
1623 
            },
1624 
            'direction' => 'out',
1625 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1626 
            'width' => 32,
1627 
          },
1628 
        },
1629 
      },
1630 
      'entityName' => 'debug_in_2i',
1631 
    },
1632 
    'debug_in_3i' => {
1633 
      'connections' => {
1634 
        'debug_in_3i' => '.debug_in_3i',
1635 
      },
1636 
      'entity' => {
1637 
        'attributes' => {
1638 
          'entityAlreadyNetlisted' => 1,
1639 
          'isGateway' => 1,
1640 
          'is_floating_block' => 1,
1641 
        },
1642 
        'entityName' => 'debug_in_3i',
1643 
        'ports' => {
1644 
          'debug_in_3i' => {
1645 
            'attributes' => {
1646 
              'bin_pt' => 0,
1647 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
1648 
              'is_floating_block' => 1,
1649 
              'is_gateway_port' => 1,
1650 
              'must_be_hdl_vector' => 1,
1651 
              'period' => 1,
1652 
              'port_id' => 0,
1653 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i/debug_in_3i',
1654 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i',
1655 
              'timingConstraint' => 'none',
1656 
              'type' => 'UFix_32_0',
1657 
            },
1658 
            'direction' => 'out',
1659 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1660 
            'width' => 32,
1661 
          },
1662 
        },
1663 
      },
1664 
      'entityName' => 'debug_in_3i',
1665 
    },
1666 
    'debug_in_4i' => {
1667 
      'connections' => {
1668 
        'debug_in_4i' => '.debug_in_4i',
1669 
      },
1670 
      'entity' => {
1671 
        'attributes' => {
1672 
          'entityAlreadyNetlisted' => 1,
1673 
          'isGateway' => 1,
1674 
          'is_floating_block' => 1,
1675 
        },
1676 
        'entityName' => 'debug_in_4i',
1677 
        'ports' => {
1678 
          'debug_in_4i' => {
1679 
            'attributes' => {
1680 
              'bin_pt' => 0,
1681 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
1682 
              'is_floating_block' => 1,
1683 
              'is_gateway_port' => 1,
1684 
              'must_be_hdl_vector' => 1,
1685 
              'period' => 1,
1686 
              'port_id' => 0,
1687 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
1688 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i',
1689 
              'timingConstraint' => 'none',
1690 
              'type' => 'UFix_32_0',
1691 
            },
1692 
            'direction' => 'out',
1693 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1694 
            'width' => 32,
1695 
          },
1696 
        },
1697 
      },
1698 
      'entityName' => 'debug_in_4i',
1699 
    },
1700 
    'dma_host2board_busy' => {
1701 
      'connections' => {
1702 
        'dma_host2board_busy' => '.dma_host2board_busy',
1703 
      },
1704 
      'entity' => {
1705 
        'attributes' => {
1706 
          'entityAlreadyNetlisted' => 1,
1707 
          'isGateway' => 1,
1708 
          'is_floating_block' => 1,
1709 
        },
1710 
        'entityName' => 'dma_host2board_busy',
1711 
        'ports' => {
1712 
          'dma_host2board_busy' => {
1713 
            'attributes' => {
1714 
              'bin_pt' => 0,
1715 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
1716 
              'is_floating_block' => 1,
1717 
              'is_gateway_port' => 1,
1718 
              'must_be_hdl_vector' => 1,
1719 
              'period' => 1,
1720 
              'port_id' => 0,
1721 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
1722 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
1723 
              'timingConstraint' => 'none',
1724 
              'type' => 'UFix_1_0',
1725 
            },
1726 
            'direction' => 'out',
1727 
            'hdlType' => 'std_logic',
1728 
            'width' => 1,
1729 
          },
1730 
        },
1731 
      },
1732 
      'entityName' => 'dma_host2board_busy',
1733 
    },
1734 
    'dma_host2board_done' => {
1735 
      'connections' => {
1736 
        'dma_host2board_done' => '.dma_host2board_done',
1737 
      },
1738 
      'entity' => {
1739 
        'attributes' => {
1740 
          'entityAlreadyNetlisted' => 1,
1741 
          'isGateway' => 1,
1742 
          'is_floating_block' => 1,
1743 
        },
1744 
        'entityName' => 'dma_host2board_done',
1745 
        'ports' => {
1746 
          'dma_host2board_done' => {
1747 
            'attributes' => {
1748 
              'bin_pt' => 0,
1749 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
1750 
              'is_floating_block' => 1,
1751 
              'is_gateway_port' => 1,
1752 
              'must_be_hdl_vector' => 1,
1753 
              'period' => 1,
1754 
              'port_id' => 0,
1755 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done/DMA_Host2Board_Done',
1756 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done',
1757 
              'timingConstraint' => 'none',
1758 
              'type' => 'UFix_1_0',
1759 
            },
1760 
            'direction' => 'out',
1761 
            'hdlType' => 'std_logic',
1762 
            'width' => 1,
1763 
          },
1764 
        },
1765 
      },
1766 
      'entityName' => 'dma_host2board_done',
1767 
    },
1768 
    'from_register1' => {
1769 
      'connections' => {
1770 
        'data_out' => 'from_register1.data_out',
1771 
      },
1772 
      'entity' => {
1773 
        'attributes' => {
1774 
          'entityAlreadyNetlisted' => 1,
1775 
          'generics' => [
1776 
          ],
1777 
          'is_floating_block' => 1,
1778 
          'mask' => {
1779 
            'Block_Handle' => 2090.00048828125,
1780 
            'Block_handle' => 2090.00048828125,
1781 
            'MDL_Handle' => 2083.00048828125,
1782 
            'MDL_handle' => 2083.00048828125,
1783 
            'arith_type' => 2,
1784 
            'bin_pt' => 0,
1785 
            'block_config' => 'sysgen_blockset:fromreg_config',
1786 
            'block_handle' => 2090.00048828125,
1787 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1',
1788 
            'block_type' => 'fromreg',
1789 
            'dbl_ovrd' => 0,
1790 
            'gui_display_data_type' => 1,
1791 
            'init' => 0,
1792 
            'init_bit_vector' => '\'b0',
1793 
            'mdl_handle' => 2083.00048828125,
1794 
            'model_handle' => 2083.00048828125,
1795 
            'n_bits' => 1,
1796 
            'ownership' => 2,
1797 
            'period' => '8e-009',
1798 
            'preci_type' => 1,
1799 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1800 
            'shared_memory_name' => 'register01rv',
1801 
          },
1802 
          'needs_vhdl_wrapper' => 0,
1803 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1',
1804 
        },
1805 
        'entityName' => 'x_x61',
1806 
        'ports' => {
1807 
          'data_out' => {
1808 
            'attributes' => {
1809 
              'bin_pt' => 0,
1810 
              'is_floating_block' => 1,
1811 
              'must_be_hdl_vector' => 1,
1812 
              'period' => 1,
1813 
              'port_id' => 0,
1814 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1/data_out',
1815 
              'type' => 'UFix_1_0',
1816 
            },
1817 
            'direction' => 'out',
1818 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1819 
            'width' => 1,
1820 
          },
1821 
        },
1822 
      },
1823 
      'entityName' => 'x_x61',
1824 
    },
1825 
    'from_register10' => {
1826 
      'connections' => {
1827 
        'data_out' => 'from_register10.data_out',
1828 
      },
1829 
      'entity' => {
1830 
        'attributes' => {
1831 
          'entityAlreadyNetlisted' => 1,
1832 
          'generics' => [
1833 
          ],
1834 
          'is_floating_block' => 1,
1835 
          'mask' => {
1836 
            'Block_Handle' => 2091.00048828125,
1837 
            'Block_handle' => 2091.00048828125,
1838 
            'MDL_Handle' => 2083.00048828125,
1839 
            'MDL_handle' => 2083.00048828125,
1840 
            'arith_type' => 2,
1841 
            'bin_pt' => 0,
1842 
            'block_config' => 'sysgen_blockset:fromreg_config',
1843 
            'block_handle' => 2091.00048828125,
1844 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10',
1845 
            'block_type' => 'fromreg',
1846 
            'dbl_ovrd' => 0,
1847 
            'gui_display_data_type' => 1,
1848 
            'init' => 0,
1849 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
1850 
            'mdl_handle' => 2083.00048828125,
1851 
            'model_handle' => 2083.00048828125,
1852 
            'n_bits' => 32,
1853 
            'ownership' => 2,
1854 
            'period' => '8e-009',
1855 
            'preci_type' => 1,
1856 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1857 
            'shared_memory_name' => 'register05rd',
1858 
          },
1859 
          'needs_vhdl_wrapper' => 0,
1860 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10',
1861 
        },
1862 
        'entityName' => 'x_x62',
1863 
        'ports' => {
1864 
          'data_out' => {
1865 
            'attributes' => {
1866 
              'bin_pt' => 0,
1867 
              'is_floating_block' => 1,
1868 
              'must_be_hdl_vector' => 1,
1869 
              'period' => 1,
1870 
              'port_id' => 0,
1871 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10/data_out',
1872 
              'type' => 'UFix_32_0',
1873 
            },
1874 
            'direction' => 'out',
1875 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1876 
            'width' => 32,
1877 
          },
1878 
        },
1879 
      },
1880 
      'entityName' => 'x_x62',
1881 
    },
1882 
    'from_register11' => {
1883 
      'connections' => {
1884 
        'data_out' => 'from_register11.data_out',
1885 
      },
1886 
      'entity' => {
1887 
        'attributes' => {
1888 
          'entityAlreadyNetlisted' => 1,
1889 
          'generics' => [
1890 
          ],
1891 
          'is_floating_block' => 1,
1892 
          'mask' => {
1893 
            'Block_Handle' => 2092.00048828125,
1894 
            'Block_handle' => 2092.00048828125,
1895 
            'MDL_Handle' => 2083.00048828125,
1896 
            'MDL_handle' => 2083.00048828125,
1897 
            'arith_type' => 2,
1898 
            'bin_pt' => 0,
1899 
            'block_config' => 'sysgen_blockset:fromreg_config',
1900 
            'block_handle' => 2092.00048828125,
1901 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11',
1902 
            'block_type' => 'fromreg',
1903 
            'dbl_ovrd' => 0,
1904 
            'gui_display_data_type' => 1,
1905 
            'init' => 0,
1906 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
1907 
            'mdl_handle' => 2083.00048828125,
1908 
            'model_handle' => 2083.00048828125,
1909 
            'n_bits' => 32,
1910 
            'ownership' => 2,
1911 
            'period' => '8e-009',
1912 
            'preci_type' => 1,
1913 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1914 
            'shared_memory_name' => 'register06rd',
1915 
          },
1916 
          'needs_vhdl_wrapper' => 0,
1917 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11',
1918 
        },
1919 
        'entityName' => 'x_x63',
1920 
        'ports' => {
1921 
          'data_out' => {
1922 
            'attributes' => {
1923 
              'bin_pt' => 0,
1924 
              'is_floating_block' => 1,
1925 
              'must_be_hdl_vector' => 1,
1926 
              'period' => 1,
1927 
              'port_id' => 0,
1928 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11/data_out',
1929 
              'type' => 'UFix_32_0',
1930 
            },
1931 
            'direction' => 'out',
1932 
            'hdlType' => 'std_logic_vector(31 downto 0)',
1933 
            'width' => 32,
1934 
          },
1935 
        },
1936 
      },
1937 
      'entityName' => 'x_x63',
1938 
    },
1939 
    'from_register12' => {
1940 
      'connections' => {
1941 
        'data_out' => 'from_register12.data_out',
1942 
      },
1943 
      'entity' => {
1944 
        'attributes' => {
1945 
          'entityAlreadyNetlisted' => 1,
1946 
          'generics' => [
1947 
          ],
1948 
          'is_floating_block' => 1,
1949 
          'mask' => {
1950 
            'Block_Handle' => 2093.00048828125,
1951 
            'Block_handle' => 2093.00048828125,
1952 
            'MDL_Handle' => 2083.00048828125,
1953 
            'MDL_handle' => 2083.00048828125,
1954 
            'arith_type' => 2,
1955 
            'bin_pt' => 0,
1956 
            'block_config' => 'sysgen_blockset:fromreg_config',
1957 
            'block_handle' => 2093.00048828125,
1958 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12',
1959 
            'block_type' => 'fromreg',
1960 
            'dbl_ovrd' => 0,
1961 
            'gui_display_data_type' => 1,
1962 
            'init' => 0,
1963 
            'init_bit_vector' => '\'b0',
1964 
            'mdl_handle' => 2083.00048828125,
1965 
            'model_handle' => 2083.00048828125,
1966 
            'n_bits' => 1,
1967 
            'ownership' => 2,
1968 
            'period' => '8e-009',
1969 
            'preci_type' => 1,
1970 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
1971 
            'shared_memory_name' => 'register06rv',
1972 
          },
1973 
          'needs_vhdl_wrapper' => 0,
1974 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12',
1975 
        },
1976 
        'entityName' => 'x_x64',
1977 
        'ports' => {
1978 
          'data_out' => {
1979 
            'attributes' => {
1980 
              'bin_pt' => 0,
1981 
              'is_floating_block' => 1,
1982 
              'must_be_hdl_vector' => 1,
1983 
              'period' => 1,
1984 
              'port_id' => 0,
1985 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12/data_out',
1986 
              'type' => 'UFix_1_0',
1987 
            },
1988 
            'direction' => 'out',
1989 
            'hdlType' => 'std_logic_vector(0 downto 0)',
1990 
            'width' => 1,
1991 
          },
1992 
        },
1993 
      },
1994 
      'entityName' => 'x_x64',
1995 
    },
1996 
    'from_register13' => {
1997 
      'connections' => {
1998 
        'data_out' => 'from_register13.data_out',
1999 
      },
2000 
      'entity' => {
2001 
        'attributes' => {
2002 
          'entityAlreadyNetlisted' => 1,
2003 
          'generics' => [
2004 
          ],
2005 
          'is_floating_block' => 1,
2006 
          'mask' => {
2007 
            'Block_Handle' => 2094.00048828125,
2008 
            'Block_handle' => 2094.00048828125,
2009 
            'MDL_Handle' => 2083.00048828125,
2010 
            'MDL_handle' => 2083.00048828125,
2011 
            'arith_type' => 2,
2012 
            'bin_pt' => 0,
2013 
            'block_config' => 'sysgen_blockset:fromreg_config',
2014 
            'block_handle' => 2094.00048828125,
2015 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13',
2016 
            'block_type' => 'fromreg',
2017 
            'dbl_ovrd' => 0,
2018 
            'gui_display_data_type' => 1,
2019 
            'init' => 0,
2020 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2021 
            'mdl_handle' => 2083.00048828125,
2022 
            'model_handle' => 2083.00048828125,
2023 
            'n_bits' => 32,
2024 
            'ownership' => 2,
2025 
            'period' => '8e-009',
2026 
            'preci_type' => 1,
2027 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2028 
            'shared_memory_name' => 'register07rd',
2029 
          },
2030 
          'needs_vhdl_wrapper' => 0,
2031 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13',
2032 
        },
2033 
        'entityName' => 'x_x65',
2034 
        'ports' => {
2035 
          'data_out' => {
2036 
            'attributes' => {
2037 
              'bin_pt' => 0,
2038 
              'is_floating_block' => 1,
2039 
              'must_be_hdl_vector' => 1,
2040 
              'period' => 1,
2041 
              'port_id' => 0,
2042 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13/data_out',
2043 
              'type' => 'UFix_32_0',
2044 
            },
2045 
            'direction' => 'out',
2046 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2047 
            'width' => 32,
2048 
          },
2049 
        },
2050 
      },
2051 
      'entityName' => 'x_x65',
2052 
    },
2053 
    'from_register14' => {
2054 
      'connections' => {
2055 
        'data_out' => 'from_register14.data_out',
2056 
      },
2057 
      'entity' => {
2058 
        'attributes' => {
2059 
          'entityAlreadyNetlisted' => 1,
2060 
          'generics' => [
2061 
          ],
2062 
          'is_floating_block' => 1,
2063 
          'mask' => {
2064 
            'Block_Handle' => 2095.00048828125,
2065 
            'Block_handle' => 2095.00048828125,
2066 
            'MDL_Handle' => 2083.00048828125,
2067 
            'MDL_handle' => 2083.00048828125,
2068 
            'arith_type' => 2,
2069 
            'bin_pt' => 0,
2070 
            'block_config' => 'sysgen_blockset:fromreg_config',
2071 
            'block_handle' => 2095.00048828125,
2072 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14',
2073 
            'block_type' => 'fromreg',
2074 
            'dbl_ovrd' => 0,
2075 
            'gui_display_data_type' => 1,
2076 
            'init' => 0,
2077 
            'init_bit_vector' => '\'b0',
2078 
            'mdl_handle' => 2083.00048828125,
2079 
            'model_handle' => 2083.00048828125,
2080 
            'n_bits' => 1,
2081 
            'ownership' => 2,
2082 
            'period' => '8e-009',
2083 
            'preci_type' => 1,
2084 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2085 
            'shared_memory_name' => 'register07rv',
2086 
          },
2087 
          'needs_vhdl_wrapper' => 0,
2088 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14',
2089 
        },
2090 
        'entityName' => 'x_x66',
2091 
        'ports' => {
2092 
          'data_out' => {
2093 
            'attributes' => {
2094 
              'bin_pt' => 0,
2095 
              'is_floating_block' => 1,
2096 
              'must_be_hdl_vector' => 1,
2097 
              'period' => 1,
2098 
              'port_id' => 0,
2099 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14/data_out',
2100 
              'type' => 'UFix_1_0',
2101 
            },
2102 
            'direction' => 'out',
2103 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2104 
            'width' => 1,
2105 
          },
2106 
        },
2107 
      },
2108 
      'entityName' => 'x_x66',
2109 
    },
2110 
    'from_register15' => {
2111 
      'connections' => {
2112 
        'data_out' => 'from_register15.data_out',
2113 
      },
2114 
      'entity' => {
2115 
        'attributes' => {
2116 
          'entityAlreadyNetlisted' => 1,
2117 
          'generics' => [
2118 
          ],
2119 
          'is_floating_block' => 1,
2120 
          'mask' => {
2121 
            'Block_Handle' => 2096.00048828125,
2122 
            'Block_handle' => 2096.00048828125,
2123 
            'MDL_Handle' => 2083.00048828125,
2124 
            'MDL_handle' => 2083.00048828125,
2125 
            'arith_type' => 2,
2126 
            'bin_pt' => 0,
2127 
            'block_config' => 'sysgen_blockset:fromreg_config',
2128 
            'block_handle' => 2096.00048828125,
2129 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15',
2130 
            'block_type' => 'fromreg',
2131 
            'dbl_ovrd' => 0,
2132 
            'gui_display_data_type' => 1,
2133 
            'init' => 0,
2134 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2135 
            'mdl_handle' => 2083.00048828125,
2136 
            'model_handle' => 2083.00048828125,
2137 
            'n_bits' => 32,
2138 
            'ownership' => 2,
2139 
            'period' => '8e-009',
2140 
            'preci_type' => 1,
2141 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2142 
            'shared_memory_name' => 'register08rd',
2143 
          },
2144 
          'needs_vhdl_wrapper' => 0,
2145 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15',
2146 
        },
2147 
        'entityName' => 'x_x67',
2148 
        'ports' => {
2149 
          'data_out' => {
2150 
            'attributes' => {
2151 
              'bin_pt' => 0,
2152 
              'is_floating_block' => 1,
2153 
              'must_be_hdl_vector' => 1,
2154 
              'period' => 1,
2155 
              'port_id' => 0,
2156 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15/data_out',
2157 
              'type' => 'UFix_32_0',
2158 
            },
2159 
            'direction' => 'out',
2160 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2161 
            'width' => 32,
2162 
          },
2163 
        },
2164 
      },
2165 
      'entityName' => 'x_x67',
2166 
    },
2167 
    'from_register16' => {
2168 
      'connections' => {
2169 
        'data_out' => 'from_register16.data_out',
2170 
      },
2171 
      'entity' => {
2172 
        'attributes' => {
2173 
          'entityAlreadyNetlisted' => 1,
2174 
          'generics' => [
2175 
          ],
2176 
          'is_floating_block' => 1,
2177 
          'mask' => {
2178 
            'Block_Handle' => 2097.00048828125,
2179 
            'Block_handle' => 2097.00048828125,
2180 
            'MDL_Handle' => 2083.00048828125,
2181 
            'MDL_handle' => 2083.00048828125,
2182 
            'arith_type' => 2,
2183 
            'bin_pt' => 0,
2184 
            'block_config' => 'sysgen_blockset:fromreg_config',
2185 
            'block_handle' => 2097.00048828125,
2186 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16',
2187 
            'block_type' => 'fromreg',
2188 
            'dbl_ovrd' => 0,
2189 
            'gui_display_data_type' => 1,
2190 
            'init' => 0,
2191 
            'init_bit_vector' => '\'b0',
2192 
            'mdl_handle' => 2083.00048828125,
2193 
            'model_handle' => 2083.00048828125,
2194 
            'n_bits' => 1,
2195 
            'ownership' => 2,
2196 
            'period' => '8e-009',
2197 
            'preci_type' => 1,
2198 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2199 
            'shared_memory_name' => 'register08rv',
2200 
          },
2201 
          'needs_vhdl_wrapper' => 0,
2202 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16',
2203 
        },
2204 
        'entityName' => 'x_x68',
2205 
        'ports' => {
2206 
          'data_out' => {
2207 
            'attributes' => {
2208 
              'bin_pt' => 0,
2209 
              'is_floating_block' => 1,
2210 
              'must_be_hdl_vector' => 1,
2211 
              'period' => 1,
2212 
              'port_id' => 0,
2213 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16/data_out',
2214 
              'type' => 'UFix_1_0',
2215 
            },
2216 
            'direction' => 'out',
2217 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2218 
            'width' => 1,
2219 
          },
2220 
        },
2221 
      },
2222 
      'entityName' => 'x_x68',
2223 
    },
2224 
    'from_register17' => {
2225 
      'connections' => {
2226 
        'data_out' => 'from_register17.data_out',
2227 
      },
2228 
      'entity' => {
2229 
        'attributes' => {
2230 
          'entityAlreadyNetlisted' => 1,
2231 
          'generics' => [
2232 
          ],
2233 
          'is_floating_block' => 1,
2234 
          'mask' => {
2235 
            'Block_Handle' => 2098.00048828125,
2236 
            'Block_handle' => 2098.00048828125,
2237 
            'MDL_Handle' => 2083.00048828125,
2238 
            'MDL_handle' => 2083.00048828125,
2239 
            'arith_type' => 2,
2240 
            'bin_pt' => 0,
2241 
            'block_config' => 'sysgen_blockset:fromreg_config',
2242 
            'block_handle' => 2098.00048828125,
2243 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17',
2244 
            'block_type' => 'fromreg',
2245 
            'dbl_ovrd' => 0,
2246 
            'gui_display_data_type' => 1,
2247 
            'init' => 0,
2248 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2249 
            'mdl_handle' => 2083.00048828125,
2250 
            'model_handle' => 2083.00048828125,
2251 
            'n_bits' => 32,
2252 
            'ownership' => 2,
2253 
            'period' => '8e-009',
2254 
            'preci_type' => 1,
2255 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2256 
            'shared_memory_name' => 'register09rd',
2257 
          },
2258 
          'needs_vhdl_wrapper' => 0,
2259 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17',
2260 
        },
2261 
        'entityName' => 'x_x69',
2262 
        'ports' => {
2263 
          'data_out' => {
2264 
            'attributes' => {
2265 
              'bin_pt' => 0,
2266 
              'is_floating_block' => 1,
2267 
              'must_be_hdl_vector' => 1,
2268 
              'period' => 1,
2269 
              'port_id' => 0,
2270 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17/data_out',
2271 
              'type' => 'UFix_32_0',
2272 
            },
2273 
            'direction' => 'out',
2274 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2275 
            'width' => 32,
2276 
          },
2277 
        },
2278 
      },
2279 
      'entityName' => 'x_x69',
2280 
    },
2281 
    'from_register18' => {
2282 
      'connections' => {
2283 
        'data_out' => 'from_register18.data_out',
2284 
      },
2285 
      'entity' => {
2286 
        'attributes' => {
2287 
          'entityAlreadyNetlisted' => 1,
2288 
          'generics' => [
2289 
          ],
2290 
          'is_floating_block' => 1,
2291 
          'mask' => {
2292 
            'Block_Handle' => 2099.00048828125,
2293 
            'Block_handle' => 2099.00048828125,
2294 
            'MDL_Handle' => 2083.00048828125,
2295 
            'MDL_handle' => 2083.00048828125,
2296 
            'arith_type' => 2,
2297 
            'bin_pt' => 0,
2298 
            'block_config' => 'sysgen_blockset:fromreg_config',
2299 
            'block_handle' => 2099.00048828125,
2300 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18',
2301 
            'block_type' => 'fromreg',
2302 
            'dbl_ovrd' => 0,
2303 
            'gui_display_data_type' => 1,
2304 
            'init' => 0,
2305 
            'init_bit_vector' => '\'b0',
2306 
            'mdl_handle' => 2083.00048828125,
2307 
            'model_handle' => 2083.00048828125,
2308 
            'n_bits' => 1,
2309 
            'ownership' => 2,
2310 
            'period' => '8e-009',
2311 
            'preci_type' => 1,
2312 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2313 
            'shared_memory_name' => 'register09rv',
2314 
          },
2315 
          'needs_vhdl_wrapper' => 0,
2316 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18',
2317 
        },
2318 
        'entityName' => 'x_x70',
2319 
        'ports' => {
2320 
          'data_out' => {
2321 
            'attributes' => {
2322 
              'bin_pt' => 0,
2323 
              'is_floating_block' => 1,
2324 
              'must_be_hdl_vector' => 1,
2325 
              'period' => 1,
2326 
              'port_id' => 0,
2327 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18/data_out',
2328 
              'type' => 'UFix_1_0',
2329 
            },
2330 
            'direction' => 'out',
2331 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2332 
            'width' => 1,
2333 
          },
2334 
        },
2335 
      },
2336 
      'entityName' => 'x_x70',
2337 
    },
2338 
    'from_register19' => {
2339 
      'connections' => {
2340 
        'data_out' => 'from_register19.data_out',
2341 
      },
2342 
      'entity' => {
2343 
        'attributes' => {
2344 
          'entityAlreadyNetlisted' => 1,
2345 
          'generics' => [
2346 
          ],
2347 
          'is_floating_block' => 1,
2348 
          'mask' => {
2349 
            'Block_Handle' => 2100.00048828125,
2350 
            'Block_handle' => 2100.00048828125,
2351 
            'MDL_Handle' => 2083.00048828125,
2352 
            'MDL_handle' => 2083.00048828125,
2353 
            'arith_type' => 2,
2354 
            'bin_pt' => 0,
2355 
            'block_config' => 'sysgen_blockset:fromreg_config',
2356 
            'block_handle' => 2100.00048828125,
2357 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19',
2358 
            'block_type' => 'fromreg',
2359 
            'dbl_ovrd' => 0,
2360 
            'gui_display_data_type' => 1,
2361 
            'init' => 0,
2362 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2363 
            'mdl_handle' => 2083.00048828125,
2364 
            'model_handle' => 2083.00048828125,
2365 
            'n_bits' => 32,
2366 
            'ownership' => 2,
2367 
            'period' => '8e-009',
2368 
            'preci_type' => 1,
2369 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2370 
            'shared_memory_name' => 'register10rd',
2371 
          },
2372 
          'needs_vhdl_wrapper' => 0,
2373 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19',
2374 
        },
2375 
        'entityName' => 'x_x71',
2376 
        'ports' => {
2377 
          'data_out' => {
2378 
            'attributes' => {
2379 
              'bin_pt' => 0,
2380 
              'is_floating_block' => 1,
2381 
              'must_be_hdl_vector' => 1,
2382 
              'period' => 1,
2383 
              'port_id' => 0,
2384 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19/data_out',
2385 
              'type' => 'UFix_32_0',
2386 
            },
2387 
            'direction' => 'out',
2388 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2389 
            'width' => 32,
2390 
          },
2391 
        },
2392 
      },
2393 
      'entityName' => 'x_x71',
2394 
    },
2395 
    'from_register2' => {
2396 
      'connections' => {
2397 
        'data_out' => 'from_register2.data_out',
2398 
      },
2399 
      'entity' => {
2400 
        'attributes' => {
2401 
          'entityAlreadyNetlisted' => 1,
2402 
          'generics' => [
2403 
          ],
2404 
          'is_floating_block' => 1,
2405 
          'mask' => {
2406 
            'Block_Handle' => 2101.00048828125,
2407 
            'Block_handle' => 2101.00048828125,
2408 
            'MDL_Handle' => 2083.00048828125,
2409 
            'MDL_handle' => 2083.00048828125,
2410 
            'arith_type' => 2,
2411 
            'bin_pt' => 0,
2412 
            'block_config' => 'sysgen_blockset:fromreg_config',
2413 
            'block_handle' => 2101.00048828125,
2414 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2',
2415 
            'block_type' => 'fromreg',
2416 
            'dbl_ovrd' => 0,
2417 
            'gui_display_data_type' => 1,
2418 
            'init' => 0,
2419 
            'init_bit_vector' => '\'b0',
2420 
            'mdl_handle' => 2083.00048828125,
2421 
            'model_handle' => 2083.00048828125,
2422 
            'n_bits' => 1,
2423 
            'ownership' => 2,
2424 
            'period' => '8e-009',
2425 
            'preci_type' => 1,
2426 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2427 
            'shared_memory_name' => 'register02rv',
2428 
          },
2429 
          'needs_vhdl_wrapper' => 0,
2430 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2',
2431 
        },
2432 
        'entityName' => 'x_x72',
2433 
        'ports' => {
2434 
          'data_out' => {
2435 
            'attributes' => {
2436 
              'bin_pt' => 0,
2437 
              'is_floating_block' => 1,
2438 
              'must_be_hdl_vector' => 1,
2439 
              'period' => 1,
2440 
              'port_id' => 0,
2441 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2/data_out',
2442 
              'type' => 'UFix_1_0',
2443 
            },
2444 
            'direction' => 'out',
2445 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2446 
            'width' => 1,
2447 
          },
2448 
        },
2449 
      },
2450 
      'entityName' => 'x_x72',
2451 
    },
2452 
    'from_register20' => {
2453 
      'connections' => {
2454 
        'data_out' => 'from_register20.data_out',
2455 
      },
2456 
      'entity' => {
2457 
        'attributes' => {
2458 
          'entityAlreadyNetlisted' => 1,
2459 
          'generics' => [
2460 
          ],
2461 
          'is_floating_block' => 1,
2462 
          'mask' => {
2463 
            'Block_Handle' => 2102.00048828125,
2464 
            'Block_handle' => 2102.00048828125,
2465 
            'MDL_Handle' => 2083.00048828125,
2466 
            'MDL_handle' => 2083.00048828125,
2467 
            'arith_type' => 2,
2468 
            'bin_pt' => 0,
2469 
            'block_config' => 'sysgen_blockset:fromreg_config',
2470 
            'block_handle' => 2102.00048828125,
2471 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20',
2472 
            'block_type' => 'fromreg',
2473 
            'dbl_ovrd' => 0,
2474 
            'gui_display_data_type' => 1,
2475 
            'init' => 0,
2476 
            'init_bit_vector' => '\'b0',
2477 
            'mdl_handle' => 2083.00048828125,
2478 
            'model_handle' => 2083.00048828125,
2479 
            'n_bits' => 1,
2480 
            'ownership' => 2,
2481 
            'period' => '8e-009',
2482 
            'preci_type' => 1,
2483 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2484 
            'shared_memory_name' => 'register10rv',
2485 
          },
2486 
          'needs_vhdl_wrapper' => 0,
2487 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20',
2488 
        },
2489 
        'entityName' => 'x_x73',
2490 
        'ports' => {
2491 
          'data_out' => {
2492 
            'attributes' => {
2493 
              'bin_pt' => 0,
2494 
              'is_floating_block' => 1,
2495 
              'must_be_hdl_vector' => 1,
2496 
              'period' => 1,
2497 
              'port_id' => 0,
2498 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20/data_out',
2499 
              'type' => 'UFix_1_0',
2500 
            },
2501 
            'direction' => 'out',
2502 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2503 
            'width' => 1,
2504 
          },
2505 
        },
2506 
      },
2507 
      'entityName' => 'x_x73',
2508 
    },
2509 
    'from_register21' => {
2510 
      'connections' => {
2511 
        'data_out' => 'from_register21.data_out',
2512 
      },
2513 
      'entity' => {
2514 
        'attributes' => {
2515 
          'entityAlreadyNetlisted' => 1,
2516 
          'generics' => [
2517 
          ],
2518 
          'is_floating_block' => 1,
2519 
          'mask' => {
2520 
            'Block_Handle' => 2103.00048828125,
2521 
            'Block_handle' => 2103.00048828125,
2522 
            'MDL_Handle' => 2083.00048828125,
2523 
            'MDL_handle' => 2083.00048828125,
2524 
            'arith_type' => 2,
2525 
            'bin_pt' => 0,
2526 
            'block_config' => 'sysgen_blockset:fromreg_config',
2527 
            'block_handle' => 2103.00048828125,
2528 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21',
2529 
            'block_type' => 'fromreg',
2530 
            'dbl_ovrd' => 0,
2531 
            'gui_display_data_type' => 1,
2532 
            'init' => 0,
2533 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2534 
            'mdl_handle' => 2083.00048828125,
2535 
            'model_handle' => 2083.00048828125,
2536 
            'n_bits' => 32,
2537 
            'ownership' => 2,
2538 
            'period' => '8e-009',
2539 
            'preci_type' => 1,
2540 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2541 
            'shared_memory_name' => 'register11rd',
2542 
          },
2543 
          'needs_vhdl_wrapper' => 0,
2544 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21',
2545 
        },
2546 
        'entityName' => 'x_x74',
2547 
        'ports' => {
2548 
          'data_out' => {
2549 
            'attributes' => {
2550 
              'bin_pt' => 0,
2551 
              'is_floating_block' => 1,
2552 
              'must_be_hdl_vector' => 1,
2553 
              'period' => 1,
2554 
              'port_id' => 0,
2555 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21/data_out',
2556 
              'type' => 'UFix_32_0',
2557 
            },
2558 
            'direction' => 'out',
2559 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2560 
            'width' => 32,
2561 
          },
2562 
        },
2563 
      },
2564 
      'entityName' => 'x_x74',
2565 
    },
2566 
    'from_register22' => {
2567 
      'connections' => {
2568 
        'data_out' => 'from_register22.data_out',
2569 
      },
2570 
      'entity' => {
2571 
        'attributes' => {
2572 
          'entityAlreadyNetlisted' => 1,
2573 
          'generics' => [
2574 
          ],
2575 
          'is_floating_block' => 1,
2576 
          'mask' => {
2577 
            'Block_Handle' => 2104.00048828125,
2578 
            'Block_handle' => 2104.00048828125,
2579 
            'MDL_Handle' => 2083.00048828125,
2580 
            'MDL_handle' => 2083.00048828125,
2581 
            'arith_type' => 2,
2582 
            'bin_pt' => 0,
2583 
            'block_config' => 'sysgen_blockset:fromreg_config',
2584 
            'block_handle' => 2104.00048828125,
2585 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22',
2586 
            'block_type' => 'fromreg',
2587 
            'dbl_ovrd' => 0,
2588 
            'gui_display_data_type' => 1,
2589 
            'init' => 0,
2590 
            'init_bit_vector' => '\'b0',
2591 
            'mdl_handle' => 2083.00048828125,
2592 
            'model_handle' => 2083.00048828125,
2593 
            'n_bits' => 1,
2594 
            'ownership' => 2,
2595 
            'period' => '8e-009',
2596 
            'preci_type' => 1,
2597 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2598 
            'shared_memory_name' => 'register11rv',
2599 
          },
2600 
          'needs_vhdl_wrapper' => 0,
2601 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22',
2602 
        },
2603 
        'entityName' => 'x_x75',
2604 
        'ports' => {
2605 
          'data_out' => {
2606 
            'attributes' => {
2607 
              'bin_pt' => 0,
2608 
              'is_floating_block' => 1,
2609 
              'must_be_hdl_vector' => 1,
2610 
              'period' => 1,
2611 
              'port_id' => 0,
2612 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22/data_out',
2613 
              'type' => 'UFix_1_0',
2614 
            },
2615 
            'direction' => 'out',
2616 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2617 
            'width' => 1,
2618 
          },
2619 
        },
2620 
      },
2621 
      'entityName' => 'x_x75',
2622 
    },
2623 
    'from_register23' => {
2624 
      'connections' => {
2625 
        'data_out' => 'from_register23.data_out',
2626 
      },
2627 
      'entity' => {
2628 
        'attributes' => {
2629 
          'entityAlreadyNetlisted' => 1,
2630 
          'generics' => [
2631 
          ],
2632 
          'is_floating_block' => 1,
2633 
          'mask' => {
2634 
            'Block_Handle' => 2105.00048828125,
2635 
            'Block_handle' => 2105.00048828125,
2636 
            'MDL_Handle' => 2083.00048828125,
2637 
            'MDL_handle' => 2083.00048828125,
2638 
            'arith_type' => 2,
2639 
            'bin_pt' => 0,
2640 
            'block_config' => 'sysgen_blockset:fromreg_config',
2641 
            'block_handle' => 2105.00048828125,
2642 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23',
2643 
            'block_type' => 'fromreg',
2644 
            'dbl_ovrd' => 0,
2645 
            'gui_display_data_type' => 1,
2646 
            'init' => 0,
2647 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2648 
            'mdl_handle' => 2083.00048828125,
2649 
            'model_handle' => 2083.00048828125,
2650 
            'n_bits' => 32,
2651 
            'ownership' => 2,
2652 
            'period' => '8e-009',
2653 
            'preci_type' => 1,
2654 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2655 
            'shared_memory_name' => 'register12rd',
2656 
          },
2657 
          'needs_vhdl_wrapper' => 0,
2658 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23',
2659 
        },
2660 
        'entityName' => 'x_x76',
2661 
        'ports' => {
2662 
          'data_out' => {
2663 
            'attributes' => {
2664 
              'bin_pt' => 0,
2665 
              'is_floating_block' => 1,
2666 
              'must_be_hdl_vector' => 1,
2667 
              'period' => 1,
2668 
              'port_id' => 0,
2669 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23/data_out',
2670 
              'type' => 'UFix_32_0',
2671 
            },
2672 
            'direction' => 'out',
2673 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2674 
            'width' => 32,
2675 
          },
2676 
        },
2677 
      },
2678 
      'entityName' => 'x_x76',
2679 
    },
2680 
    'from_register24' => {
2681 
      'connections' => {
2682 
        'data_out' => 'from_register24.data_out',
2683 
      },
2684 
      'entity' => {
2685 
        'attributes' => {
2686 
          'entityAlreadyNetlisted' => 1,
2687 
          'generics' => [
2688 
          ],
2689 
          'is_floating_block' => 1,
2690 
          'mask' => {
2691 
            'Block_Handle' => 2106.00048828125,
2692 
            'Block_handle' => 2106.00048828125,
2693 
            'MDL_Handle' => 2083.00048828125,
2694 
            'MDL_handle' => 2083.00048828125,
2695 
            'arith_type' => 2,
2696 
            'bin_pt' => 0,
2697 
            'block_config' => 'sysgen_blockset:fromreg_config',
2698 
            'block_handle' => 2106.00048828125,
2699 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24',
2700 
            'block_type' => 'fromreg',
2701 
            'dbl_ovrd' => 0,
2702 
            'gui_display_data_type' => 1,
2703 
            'init' => 0,
2704 
            'init_bit_vector' => '\'b0',
2705 
            'mdl_handle' => 2083.00048828125,
2706 
            'model_handle' => 2083.00048828125,
2707 
            'n_bits' => 1,
2708 
            'ownership' => 2,
2709 
            'period' => '8e-009',
2710 
            'preci_type' => 1,
2711 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2712 
            'shared_memory_name' => 'register12rv',
2713 
          },
2714 
          'needs_vhdl_wrapper' => 0,
2715 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24',
2716 
        },
2717 
        'entityName' => 'x_x77',
2718 
        'ports' => {
2719 
          'data_out' => {
2720 
            'attributes' => {
2721 
              'bin_pt' => 0,
2722 
              'is_floating_block' => 1,
2723 
              'must_be_hdl_vector' => 1,
2724 
              'period' => 1,
2725 
              'port_id' => 0,
2726 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24/data_out',
2727 
              'type' => 'UFix_1_0',
2728 
            },
2729 
            'direction' => 'out',
2730 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2731 
            'width' => 1,
2732 
          },
2733 
        },
2734 
      },
2735 
      'entityName' => 'x_x77',
2736 
    },
2737 
    'from_register25' => {
2738 
      'connections' => {
2739 
        'data_out' => 'from_register25.data_out',
2740 
      },
2741 
      'entity' => {
2742 
        'attributes' => {
2743 
          'entityAlreadyNetlisted' => 1,
2744 
          'generics' => [
2745 
          ],
2746 
          'is_floating_block' => 1,
2747 
          'mask' => {
2748 
            'Block_Handle' => 2107.00048828125,
2749 
            'Block_handle' => 2107.00048828125,
2750 
            'MDL_Handle' => 2083.00048828125,
2751 
            'MDL_handle' => 2083.00048828125,
2752 
            'arith_type' => 2,
2753 
            'bin_pt' => 0,
2754 
            'block_config' => 'sysgen_blockset:fromreg_config',
2755 
            'block_handle' => 2107.00048828125,
2756 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25',
2757 
            'block_type' => 'fromreg',
2758 
            'dbl_ovrd' => 0,
2759 
            'gui_display_data_type' => 1,
2760 
            'init' => 0,
2761 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2762 
            'mdl_handle' => 2083.00048828125,
2763 
            'model_handle' => 2083.00048828125,
2764 
            'n_bits' => 32,
2765 
            'ownership' => 2,
2766 
            'period' => '8e-009',
2767 
            'preci_type' => 1,
2768 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2769 
            'shared_memory_name' => 'register13rd',
2770 
          },
2771 
          'needs_vhdl_wrapper' => 0,
2772 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25',
2773 
        },
2774 
        'entityName' => 'x_x78',
2775 
        'ports' => {
2776 
          'data_out' => {
2777 
            'attributes' => {
2778 
              'bin_pt' => 0,
2779 
              'is_floating_block' => 1,
2780 
              'must_be_hdl_vector' => 1,
2781 
              'period' => 1,
2782 
              'port_id' => 0,
2783 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25/data_out',
2784 
              'type' => 'UFix_32_0',
2785 
            },
2786 
            'direction' => 'out',
2787 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2788 
            'width' => 32,
2789 
          },
2790 
        },
2791 
      },
2792 
      'entityName' => 'x_x78',
2793 
    },
2794 
    'from_register26' => {
2795 
      'connections' => {
2796 
        'data_out' => 'from_register26.data_out',
2797 
      },
2798 
      'entity' => {
2799 
        'attributes' => {
2800 
          'entityAlreadyNetlisted' => 1,
2801 
          'generics' => [
2802 
          ],
2803 
          'is_floating_block' => 1,
2804 
          'mask' => {
2805 
            'Block_Handle' => 2108.00048828125,
2806 
            'Block_handle' => 2108.00048828125,
2807 
            'MDL_Handle' => 2083.00048828125,
2808 
            'MDL_handle' => 2083.00048828125,
2809 
            'arith_type' => 2,
2810 
            'bin_pt' => 0,
2811 
            'block_config' => 'sysgen_blockset:fromreg_config',
2812 
            'block_handle' => 2108.00048828125,
2813 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26',
2814 
            'block_type' => 'fromreg',
2815 
            'dbl_ovrd' => 0,
2816 
            'gui_display_data_type' => 1,
2817 
            'init' => 0,
2818 
            'init_bit_vector' => '\'b0',
2819 
            'mdl_handle' => 2083.00048828125,
2820 
            'model_handle' => 2083.00048828125,
2821 
            'n_bits' => 1,
2822 
            'ownership' => 2,
2823 
            'period' => '8e-009',
2824 
            'preci_type' => 1,
2825 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2826 
            'shared_memory_name' => 'register13rv',
2827 
          },
2828 
          'needs_vhdl_wrapper' => 0,
2829 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26',
2830 
        },
2831 
        'entityName' => 'x_x79',
2832 
        'ports' => {
2833 
          'data_out' => {
2834 
            'attributes' => {
2835 
              'bin_pt' => 0,
2836 
              'is_floating_block' => 1,
2837 
              'must_be_hdl_vector' => 1,
2838 
              'period' => 1,
2839 
              'port_id' => 0,
2840 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26/data_out',
2841 
              'type' => 'UFix_1_0',
2842 
            },
2843 
            'direction' => 'out',
2844 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2845 
            'width' => 1,
2846 
          },
2847 
        },
2848 
      },
2849 
      'entityName' => 'x_x79',
2850 
    },
2851 
    'from_register27' => {
2852 
      'connections' => {
2853 
        'data_out' => 'from_register27.data_out',
2854 
      },
2855 
      'entity' => {
2856 
        'attributes' => {
2857 
          'entityAlreadyNetlisted' => 1,
2858 
          'generics' => [
2859 
          ],
2860 
          'is_floating_block' => 1,
2861 
          'mask' => {
2862 
            'Block_Handle' => 2109.00048828125,
2863 
            'Block_handle' => 2109.00048828125,
2864 
            'MDL_Handle' => 2083.00048828125,
2865 
            'MDL_handle' => 2083.00048828125,
2866 
            'arith_type' => 2,
2867 
            'bin_pt' => 0,
2868 
            'block_config' => 'sysgen_blockset:fromreg_config',
2869 
            'block_handle' => 2109.00048828125,
2870 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27',
2871 
            'block_type' => 'fromreg',
2872 
            'dbl_ovrd' => 0,
2873 
            'gui_display_data_type' => 1,
2874 
            'init' => 0,
2875 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2876 
            'mdl_handle' => 2083.00048828125,
2877 
            'model_handle' => 2083.00048828125,
2878 
            'n_bits' => 32,
2879 
            'ownership' => 2,
2880 
            'period' => '8e-009',
2881 
            'preci_type' => 1,
2882 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2883 
            'shared_memory_name' => 'register14rd',
2884 
          },
2885 
          'needs_vhdl_wrapper' => 0,
2886 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27',
2887 
        },
2888 
        'entityName' => 'x_x80',
2889 
        'ports' => {
2890 
          'data_out' => {
2891 
            'attributes' => {
2892 
              'bin_pt' => 0,
2893 
              'is_floating_block' => 1,
2894 
              'must_be_hdl_vector' => 1,
2895 
              'period' => 1,
2896 
              'port_id' => 0,
2897 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27/data_out',
2898 
              'type' => 'UFix_32_0',
2899 
            },
2900 
            'direction' => 'out',
2901 
            'hdlType' => 'std_logic_vector(31 downto 0)',
2902 
            'width' => 32,
2903 
          },
2904 
        },
2905 
      },
2906 
      'entityName' => 'x_x80',
2907 
    },
2908 
    'from_register28' => {
2909 
      'connections' => {
2910 
        'data_out' => 'from_register28.data_out',
2911 
      },
2912 
      'entity' => {
2913 
        'attributes' => {
2914 
          'entityAlreadyNetlisted' => 1,
2915 
          'generics' => [
2916 
          ],
2917 
          'is_floating_block' => 1,
2918 
          'mask' => {
2919 
            'Block_Handle' => 2110.00048828125,
2920 
            'Block_handle' => 2110.00048828125,
2921 
            'MDL_Handle' => 2083.00048828125,
2922 
            'MDL_handle' => 2083.00048828125,
2923 
            'arith_type' => 2,
2924 
            'bin_pt' => 0,
2925 
            'block_config' => 'sysgen_blockset:fromreg_config',
2926 
            'block_handle' => 2110.00048828125,
2927 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28',
2928 
            'block_type' => 'fromreg',
2929 
            'dbl_ovrd' => 0,
2930 
            'gui_display_data_type' => 1,
2931 
            'init' => 0,
2932 
            'init_bit_vector' => '\'b0',
2933 
            'mdl_handle' => 2083.00048828125,
2934 
            'model_handle' => 2083.00048828125,
2935 
            'n_bits' => 1,
2936 
            'ownership' => 2,
2937 
            'period' => '8e-009',
2938 
            'preci_type' => 1,
2939 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2940 
            'shared_memory_name' => 'register14rv',
2941 
          },
2942 
          'needs_vhdl_wrapper' => 0,
2943 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28',
2944 
        },
2945 
        'entityName' => 'x_x81',
2946 
        'ports' => {
2947 
          'data_out' => {
2948 
            'attributes' => {
2949 
              'bin_pt' => 0,
2950 
              'is_floating_block' => 1,
2951 
              'must_be_hdl_vector' => 1,
2952 
              'period' => 1,
2953 
              'port_id' => 0,
2954 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28/data_out',
2955 
              'type' => 'UFix_1_0',
2956 
            },
2957 
            'direction' => 'out',
2958 
            'hdlType' => 'std_logic_vector(0 downto 0)',
2959 
            'width' => 1,
2960 
          },
2961 
        },
2962 
      },
2963 
      'entityName' => 'x_x81',
2964 
    },
2965 
    'from_register3' => {
2966 
      'connections' => {
2967 
        'data_out' => 'from_register3.data_out',
2968 
      },
2969 
      'entity' => {
2970 
        'attributes' => {
2971 
          'entityAlreadyNetlisted' => 1,
2972 
          'generics' => [
2973 
          ],
2974 
          'is_floating_block' => 1,
2975 
          'mask' => {
2976 
            'Block_Handle' => 2111.00048828125,
2977 
            'Block_handle' => 2111.00048828125,
2978 
            'MDL_Handle' => 2083.00048828125,
2979 
            'MDL_handle' => 2083.00048828125,
2980 
            'arith_type' => 2,
2981 
            'bin_pt' => 0,
2982 
            'block_config' => 'sysgen_blockset:fromreg_config',
2983 
            'block_handle' => 2111.00048828125,
2984 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3',
2985 
            'block_type' => 'fromreg',
2986 
            'dbl_ovrd' => 0,
2987 
            'gui_display_data_type' => 1,
2988 
            'init' => 0,
2989 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
2990 
            'mdl_handle' => 2083.00048828125,
2991 
            'model_handle' => 2083.00048828125,
2992 
            'n_bits' => 32,
2993 
            'ownership' => 2,
2994 
            'period' => '8e-009',
2995 
            'preci_type' => 1,
2996 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
2997 
            'shared_memory_name' => 'register01rd',
2998 
          },
2999 
          'needs_vhdl_wrapper' => 0,
3000 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3',
3001 
        },
3002 
        'entityName' => 'x_x82',
3003 
        'ports' => {
3004 
          'data_out' => {
3005 
            'attributes' => {
3006 
              'bin_pt' => 0,
3007 
              'is_floating_block' => 1,
3008 
              'must_be_hdl_vector' => 1,
3009 
              'period' => 1,
3010 
              'port_id' => 0,
3011 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3/data_out',
3012 
              'type' => 'UFix_32_0',
3013 
            },
3014 
            'direction' => 'out',
3015 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3016 
            'width' => 32,
3017 
          },
3018 
        },
3019 
      },
3020 
      'entityName' => 'x_x82',
3021 
    },
3022 
    'from_register4' => {
3023 
      'connections' => {
3024 
        'data_out' => 'from_register4.data_out',
3025 
      },
3026 
      'entity' => {
3027 
        'attributes' => {
3028 
          'entityAlreadyNetlisted' => 1,
3029 
          'generics' => [
3030 
          ],
3031 
          'is_floating_block' => 1,
3032 
          'mask' => {
3033 
            'Block_Handle' => 2112.00048828125,
3034 
            'Block_handle' => 2112.00048828125,
3035 
            'MDL_Handle' => 2083.00048828125,
3036 
            'MDL_handle' => 2083.00048828125,
3037 
            'arith_type' => 2,
3038 
            'bin_pt' => 0,
3039 
            'block_config' => 'sysgen_blockset:fromreg_config',
3040 
            'block_handle' => 2112.00048828125,
3041 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4',
3042 
            'block_type' => 'fromreg',
3043 
            'dbl_ovrd' => 0,
3044 
            'gui_display_data_type' => 1,
3045 
            'init' => 0,
3046 
            'init_bit_vector' => '\'b0',
3047 
            'mdl_handle' => 2083.00048828125,
3048 
            'model_handle' => 2083.00048828125,
3049 
            'n_bits' => 1,
3050 
            'ownership' => 2,
3051 
            'period' => '8e-009',
3052 
            'preci_type' => 1,
3053 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3054 
            'shared_memory_name' => 'register04rv',
3055 
          },
3056 
          'needs_vhdl_wrapper' => 0,
3057 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4',
3058 
        },
3059 
        'entityName' => 'x_x83',
3060 
        'ports' => {
3061 
          'data_out' => {
3062 
            'attributes' => {
3063 
              'bin_pt' => 0,
3064 
              'is_floating_block' => 1,
3065 
              'must_be_hdl_vector' => 1,
3066 
              'period' => 1,
3067 
              'port_id' => 0,
3068 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4/data_out',
3069 
              'type' => 'UFix_1_0',
3070 
            },
3071 
            'direction' => 'out',
3072 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3073 
            'width' => 1,
3074 
          },
3075 
        },
3076 
      },
3077 
      'entityName' => 'x_x83',
3078 
    },
3079 
    'from_register5' => {
3080 
      'connections' => {
3081 
        'data_out' => 'from_register5.data_out',
3082 
      },
3083 
      'entity' => {
3084 
        'attributes' => {
3085 
          'entityAlreadyNetlisted' => 1,
3086 
          'generics' => [
3087 
          ],
3088 
          'is_floating_block' => 1,
3089 
          'mask' => {
3090 
            'Block_Handle' => 2113.00048828125,
3091 
            'Block_handle' => 2113.00048828125,
3092 
            'MDL_Handle' => 2083.00048828125,
3093 
            'MDL_handle' => 2083.00048828125,
3094 
            'arith_type' => 2,
3095 
            'bin_pt' => 0,
3096 
            'block_config' => 'sysgen_blockset:fromreg_config',
3097 
            'block_handle' => 2113.00048828125,
3098 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5',
3099 
            'block_type' => 'fromreg',
3100 
            'dbl_ovrd' => 0,
3101 
            'gui_display_data_type' => 1,
3102 
            'init' => 0,
3103 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
3104 
            'mdl_handle' => 2083.00048828125,
3105 
            'model_handle' => 2083.00048828125,
3106 
            'n_bits' => 32,
3107 
            'ownership' => 2,
3108 
            'period' => '8e-009',
3109 
            'preci_type' => 1,
3110 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3111 
            'shared_memory_name' => 'register02rd',
3112 
          },
3113 
          'needs_vhdl_wrapper' => 0,
3114 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5',
3115 
        },
3116 
        'entityName' => 'x_x84',
3117 
        'ports' => {
3118 
          'data_out' => {
3119 
            'attributes' => {
3120 
              'bin_pt' => 0,
3121 
              'is_floating_block' => 1,
3122 
              'must_be_hdl_vector' => 1,
3123 
              'period' => 1,
3124 
              'port_id' => 0,
3125 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5/data_out',
3126 
              'type' => 'UFix_32_0',
3127 
            },
3128 
            'direction' => 'out',
3129 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3130 
            'width' => 32,
3131 
          },
3132 
        },
3133 
      },
3134 
      'entityName' => 'x_x84',
3135 
    },
3136 
    'from_register6' => {
3137 
      'connections' => {
3138 
        'data_out' => 'from_register6.data_out',
3139 
      },
3140 
      'entity' => {
3141 
        'attributes' => {
3142 
          'entityAlreadyNetlisted' => 1,
3143 
          'generics' => [
3144 
          ],
3145 
          'is_floating_block' => 1,
3146 
          'mask' => {
3147 
            'Block_Handle' => 2114.00048828125,
3148 
            'Block_handle' => 2114.00048828125,
3149 
            'MDL_Handle' => 2083.00048828125,
3150 
            'MDL_handle' => 2083.00048828125,
3151 
            'arith_type' => 2,
3152 
            'bin_pt' => 0,
3153 
            'block_config' => 'sysgen_blockset:fromreg_config',
3154 
            'block_handle' => 2114.00048828125,
3155 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6',
3156 
            'block_type' => 'fromreg',
3157 
            'dbl_ovrd' => 0,
3158 
            'gui_display_data_type' => 1,
3159 
            'init' => 0,
3160 
            'init_bit_vector' => '\'b0',
3161 
            'mdl_handle' => 2083.00048828125,
3162 
            'model_handle' => 2083.00048828125,
3163 
            'n_bits' => 1,
3164 
            'ownership' => 2,
3165 
            'period' => '8e-009',
3166 
            'preci_type' => 1,
3167 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3168 
            'shared_memory_name' => 'register03rv',
3169 
          },
3170 
          'needs_vhdl_wrapper' => 0,
3171 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6',
3172 
        },
3173 
        'entityName' => 'x_x85',
3174 
        'ports' => {
3175 
          'data_out' => {
3176 
            'attributes' => {
3177 
              'bin_pt' => 0,
3178 
              'is_floating_block' => 1,
3179 
              'must_be_hdl_vector' => 1,
3180 
              'period' => 1,
3181 
              'port_id' => 0,
3182 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6/data_out',
3183 
              'type' => 'UFix_1_0',
3184 
            },
3185 
            'direction' => 'out',
3186 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3187 
            'width' => 1,
3188 
          },
3189 
        },
3190 
      },
3191 
      'entityName' => 'x_x85',
3192 
    },
3193 
    'from_register7' => {
3194 
      'connections' => {
3195 
        'data_out' => 'from_register7.data_out',
3196 
      },
3197 
      'entity' => {
3198 
        'attributes' => {
3199 
          'entityAlreadyNetlisted' => 1,
3200 
          'generics' => [
3201 
          ],
3202 
          'is_floating_block' => 1,
3203 
          'mask' => {
3204 
            'Block_Handle' => 2115.00048828125,
3205 
            'Block_handle' => 2115.00048828125,
3206 
            'MDL_Handle' => 2083.00048828125,
3207 
            'MDL_handle' => 2083.00048828125,
3208 
            'arith_type' => 2,
3209 
            'bin_pt' => 0,
3210 
            'block_config' => 'sysgen_blockset:fromreg_config',
3211 
            'block_handle' => 2115.00048828125,
3212 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7',
3213 
            'block_type' => 'fromreg',
3214 
            'dbl_ovrd' => 0,
3215 
            'gui_display_data_type' => 1,
3216 
            'init' => 0,
3217 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
3218 
            'mdl_handle' => 2083.00048828125,
3219 
            'model_handle' => 2083.00048828125,
3220 
            'n_bits' => 32,
3221 
            'ownership' => 2,
3222 
            'period' => '8e-009',
3223 
            'preci_type' => 1,
3224 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3225 
            'shared_memory_name' => 'register03rd',
3226 
          },
3227 
          'needs_vhdl_wrapper' => 0,
3228 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7',
3229 
        },
3230 
        'entityName' => 'x_x86',
3231 
        'ports' => {
3232 
          'data_out' => {
3233 
            'attributes' => {
3234 
              'bin_pt' => 0,
3235 
              'is_floating_block' => 1,
3236 
              'must_be_hdl_vector' => 1,
3237 
              'period' => 1,
3238 
              'port_id' => 0,
3239 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7/data_out',
3240 
              'type' => 'UFix_32_0',
3241 
            },
3242 
            'direction' => 'out',
3243 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3244 
            'width' => 32,
3245 
          },
3246 
        },
3247 
      },
3248 
      'entityName' => 'x_x86',
3249 
    },
3250 
    'from_register8' => {
3251 
      'connections' => {
3252 
        'data_out' => 'from_register8.data_out',
3253 
      },
3254 
      'entity' => {
3255 
        'attributes' => {
3256 
          'entityAlreadyNetlisted' => 1,
3257 
          'generics' => [
3258 
          ],
3259 
          'is_floating_block' => 1,
3260 
          'mask' => {
3261 
            'Block_Handle' => 2116.00048828125,
3262 
            'Block_handle' => 2116.00048828125,
3263 
            'MDL_Handle' => 2083.00048828125,
3264 
            'MDL_handle' => 2083.00048828125,
3265 
            'arith_type' => 2,
3266 
            'bin_pt' => 0,
3267 
            'block_config' => 'sysgen_blockset:fromreg_config',
3268 
            'block_handle' => 2116.00048828125,
3269 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8',
3270 
            'block_type' => 'fromreg',
3271 
            'dbl_ovrd' => 0,
3272 
            'gui_display_data_type' => 1,
3273 
            'init' => 0,
3274 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
3275 
            'mdl_handle' => 2083.00048828125,
3276 
            'model_handle' => 2083.00048828125,
3277 
            'n_bits' => 32,
3278 
            'ownership' => 2,
3279 
            'period' => '8e-009',
3280 
            'preci_type' => 1,
3281 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3282 
            'shared_memory_name' => 'register04rd',
3283 
          },
3284 
          'needs_vhdl_wrapper' => 0,
3285 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8',
3286 
        },
3287 
        'entityName' => 'x_x87',
3288 
        'ports' => {
3289 
          'data_out' => {
3290 
            'attributes' => {
3291 
              'bin_pt' => 0,
3292 
              'is_floating_block' => 1,
3293 
              'must_be_hdl_vector' => 1,
3294 
              'period' => 1,
3295 
              'port_id' => 0,
3296 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8/data_out',
3297 
              'type' => 'UFix_32_0',
3298 
            },
3299 
            'direction' => 'out',
3300 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3301 
            'width' => 32,
3302 
          },
3303 
        },
3304 
      },
3305 
      'entityName' => 'x_x87',
3306 
    },
3307 
    'from_register9' => {
3308 
      'connections' => {
3309 
        'data_out' => 'from_register9.data_out',
3310 
      },
3311 
      'entity' => {
3312 
        'attributes' => {
3313 
          'entityAlreadyNetlisted' => 1,
3314 
          'generics' => [
3315 
          ],
3316 
          'is_floating_block' => 1,
3317 
          'mask' => {
3318 
            'Block_Handle' => 2117.00048828125,
3319 
            'Block_handle' => 2117.00048828125,
3320 
            'MDL_Handle' => 2083.00048828125,
3321 
            'MDL_handle' => 2083.00048828125,
3322 
            'arith_type' => 2,
3323 
            'bin_pt' => 0,
3324 
            'block_config' => 'sysgen_blockset:fromreg_config',
3325 
            'block_handle' => 2117.00048828125,
3326 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9',
3327 
            'block_type' => 'fromreg',
3328 
            'dbl_ovrd' => 0,
3329 
            'gui_display_data_type' => 1,
3330 
            'init' => 0,
3331 
            'init_bit_vector' => '\'b0',
3332 
            'mdl_handle' => 2083.00048828125,
3333 
            'model_handle' => 2083.00048828125,
3334 
            'n_bits' => 1,
3335 
            'ownership' => 2,
3336 
            'period' => '8e-009',
3337 
            'preci_type' => 1,
3338 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3339 
            'shared_memory_name' => 'register05rv',
3340 
          },
3341 
          'needs_vhdl_wrapper' => 0,
3342 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9',
3343 
        },
3344 
        'entityName' => 'x_x88',
3345 
        'ports' => {
3346 
          'data_out' => {
3347 
            'attributes' => {
3348 
              'bin_pt' => 0,
3349 
              'is_floating_block' => 1,
3350 
              'must_be_hdl_vector' => 1,
3351 
              'period' => 1,
3352 
              'port_id' => 0,
3353 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9/data_out',
3354 
              'type' => 'UFix_1_0',
3355 
            },
3356 
            'direction' => 'out',
3357 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3358 
            'width' => 1,
3359 
          },
3360 
        },
3361 
      },
3362 
      'entityName' => 'x_x88',
3363 
    },
3364 
    'reg01_rd' => {
3365 
      'connections' => {
3366 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
3367 
      },
3368 
      'entity' => {
3369 
        'attributes' => {
3370 
          'entityAlreadyNetlisted' => 1,
3371 
          'isGateway' => 1,
3372 
          'is_floating_block' => 1,
3373 
        },
3374 
        'entityName' => 'reg01_rd',
3375 
        'ports' => {
3376 
          'reg01_rd' => {
3377 
            'attributes' => {
3378 
              'bin_pt' => 0,
3379 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
3380 
              'is_floating_block' => 1,
3381 
              'is_gateway_port' => 1,
3382 
              'must_be_hdl_vector' => 1,
3383 
              'period' => 1,
3384 
              'port_id' => 0,
3385 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
3386 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
3387 
              'timingConstraint' => 'none',
3388 
              'type' => 'UFix_32_0',
3389 
            },
3390 
            'direction' => 'in',
3391 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3392 
            'width' => 32,
3393 
          },
3394 
        },
3395 
      },
3396 
      'entityName' => 'reg01_rd',
3397 
    },
3398 
    'reg01_rv' => {
3399 
      'connections' => {
3400 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
3401 
      },
3402 
      'entity' => {
3403 
        'attributes' => {
3404 
          'entityAlreadyNetlisted' => 1,
3405 
          'isGateway' => 1,
3406 
          'is_floating_block' => 1,
3407 
        },
3408 
        'entityName' => 'reg01_rv',
3409 
        'ports' => {
3410 
          'reg01_rv' => {
3411 
            'attributes' => {
3412 
              'bin_pt' => 0,
3413 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
3414 
              'is_floating_block' => 1,
3415 
              'is_gateway_port' => 1,
3416 
              'must_be_hdl_vector' => 1,
3417 
              'period' => 1,
3418 
              'port_id' => 0,
3419 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
3420 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
3421 
              'timingConstraint' => 'none',
3422 
              'type' => 'UFix_1_0',
3423 
            },
3424 
            'direction' => 'in',
3425 
            'hdlType' => 'std_logic',
3426 
            'width' => 1,
3427 
          },
3428 
        },
3429 
      },
3430 
      'entityName' => 'reg01_rv',
3431 
    },
3432 
    'reg01_td' => {
3433 
      'connections' => {
3434 
        'reg01_td' => '.reg01_td',
3435 
      },
3436 
      'entity' => {
3437 
        'attributes' => {
3438 
          'entityAlreadyNetlisted' => 1,
3439 
          'isGateway' => 1,
3440 
          'is_floating_block' => 1,
3441 
        },
3442 
        'entityName' => 'reg01_td',
3443 
        'ports' => {
3444 
          'reg01_td' => {
3445 
            'attributes' => {
3446 
              'bin_pt' => 0,
3447 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
3448 
              'is_floating_block' => 1,
3449 
              'is_gateway_port' => 1,
3450 
              'must_be_hdl_vector' => 1,
3451 
              'period' => 1,
3452 
              'port_id' => 0,
3453 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
3454 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
3455 
              'timingConstraint' => 'none',
3456 
              'type' => 'UFix_32_0',
3457 
            },
3458 
            'direction' => 'out',
3459 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3460 
            'width' => 32,
3461 
          },
3462 
        },
3463 
      },
3464 
      'entityName' => 'reg01_td',
3465 
    },
3466 
    'reg01_tv' => {
3467 
      'connections' => {
3468 
        'reg01_tv' => '.reg01_tv',
3469 
      },
3470 
      'entity' => {
3471 
        'attributes' => {
3472 
          'entityAlreadyNetlisted' => 1,
3473 
          'isGateway' => 1,
3474 
          'is_floating_block' => 1,
3475 
        },
3476 
        'entityName' => 'reg01_tv',
3477 
        'ports' => {
3478 
          'reg01_tv' => {
3479 
            'attributes' => {
3480 
              'bin_pt' => 0,
3481 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
3482 
              'is_floating_block' => 1,
3483 
              'is_gateway_port' => 1,
3484 
              'must_be_hdl_vector' => 1,
3485 
              'period' => 1,
3486 
              'port_id' => 0,
3487 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
3488 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
3489 
              'timingConstraint' => 'none',
3490 
              'type' => 'Bool',
3491 
            },
3492 
            'direction' => 'out',
3493 
            'hdlType' => 'std_logic',
3494 
            'width' => 1,
3495 
          },
3496 
        },
3497 
      },
3498 
      'entityName' => 'reg01_tv',
3499 
    },
3500 
    'reg02_rd' => {
3501 
      'connections' => {
3502 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
3503 
      },
3504 
      'entity' => {
3505 
        'attributes' => {
3506 
          'entityAlreadyNetlisted' => 1,
3507 
          'isGateway' => 1,
3508 
          'is_floating_block' => 1,
3509 
        },
3510 
        'entityName' => 'reg02_rd',
3511 
        'ports' => {
3512 
          'reg02_rd' => {
3513 
            'attributes' => {
3514 
              'bin_pt' => 0,
3515 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
3516 
              'is_floating_block' => 1,
3517 
              'is_gateway_port' => 1,
3518 
              'must_be_hdl_vector' => 1,
3519 
              'period' => 1,
3520 
              'port_id' => 0,
3521 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
3522 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
3523 
              'timingConstraint' => 'none',
3524 
              'type' => 'UFix_32_0',
3525 
            },
3526 
            'direction' => 'in',
3527 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3528 
            'width' => 32,
3529 
          },
3530 
        },
3531 
      },
3532 
      'entityName' => 'reg02_rd',
3533 
    },
3534 
    'reg02_rv' => {
3535 
      'connections' => {
3536 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
3537 
      },
3538 
      'entity' => {
3539 
        'attributes' => {
3540 
          'entityAlreadyNetlisted' => 1,
3541 
          'isGateway' => 1,
3542 
          'is_floating_block' => 1,
3543 
        },
3544 
        'entityName' => 'reg02_rv',
3545 
        'ports' => {
3546 
          'reg02_rv' => {
3547 
            'attributes' => {
3548 
              'bin_pt' => 0,
3549 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
3550 
              'is_floating_block' => 1,
3551 
              'is_gateway_port' => 1,
3552 
              'must_be_hdl_vector' => 1,
3553 
              'period' => 1,
3554 
              'port_id' => 0,
3555 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
3556 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
3557 
              'timingConstraint' => 'none',
3558 
              'type' => 'UFix_1_0',
3559 
            },
3560 
            'direction' => 'in',
3561 
            'hdlType' => 'std_logic',
3562 
            'width' => 1,
3563 
          },
3564 
        },
3565 
      },
3566 
      'entityName' => 'reg02_rv',
3567 
    },
3568 
    'reg02_td' => {
3569 
      'connections' => {
3570 
        'reg02_td' => '.reg02_td',
3571 
      },
3572 
      'entity' => {
3573 
        'attributes' => {
3574 
          'entityAlreadyNetlisted' => 1,
3575 
          'isGateway' => 1,
3576 
          'is_floating_block' => 1,
3577 
        },
3578 
        'entityName' => 'reg02_td',
3579 
        'ports' => {
3580 
          'reg02_td' => {
3581 
            'attributes' => {
3582 
              'bin_pt' => 0,
3583 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
3584 
              'is_floating_block' => 1,
3585 
              'is_gateway_port' => 1,
3586 
              'must_be_hdl_vector' => 1,
3587 
              'period' => 1,
3588 
              'port_id' => 0,
3589 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
3590 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
3591 
              'timingConstraint' => 'none',
3592 
              'type' => 'UFix_32_0',
3593 
            },
3594 
            'direction' => 'out',
3595 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3596 
            'width' => 32,
3597 
          },
3598 
        },
3599 
      },
3600 
      'entityName' => 'reg02_td',
3601 
    },
3602 
    'reg02_tv' => {
3603 
      'connections' => {
3604 
        'reg02_tv' => '.reg02_tv',
3605 
      },
3606 
      'entity' => {
3607 
        'attributes' => {
3608 
          'entityAlreadyNetlisted' => 1,
3609 
          'isGateway' => 1,
3610 
          'is_floating_block' => 1,
3611 
        },
3612 
        'entityName' => 'reg02_tv',
3613 
        'ports' => {
3614 
          'reg02_tv' => {
3615 
            'attributes' => {
3616 
              'bin_pt' => 0,
3617 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
3618 
              'is_floating_block' => 1,
3619 
              'is_gateway_port' => 1,
3620 
              'must_be_hdl_vector' => 1,
3621 
              'period' => 1,
3622 
              'port_id' => 0,
3623 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
3624 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
3625 
              'timingConstraint' => 'none',
3626 
              'type' => 'Bool',
3627 
            },
3628 
            'direction' => 'out',
3629 
            'hdlType' => 'std_logic',
3630 
            'width' => 1,
3631 
          },
3632 
        },
3633 
      },
3634 
      'entityName' => 'reg02_tv',
3635 
    },
3636 
    'reg03_rd' => {
3637 
      'connections' => {
3638 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
3639 
      },
3640 
      'entity' => {
3641 
        'attributes' => {
3642 
          'entityAlreadyNetlisted' => 1,
3643 
          'isGateway' => 1,
3644 
          'is_floating_block' => 1,
3645 
        },
3646 
        'entityName' => 'reg03_rd',
3647 
        'ports' => {
3648 
          'reg03_rd' => {
3649 
            'attributes' => {
3650 
              'bin_pt' => 0,
3651 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
3652 
              'is_floating_block' => 1,
3653 
              'is_gateway_port' => 1,
3654 
              'must_be_hdl_vector' => 1,
3655 
              'period' => 1,
3656 
              'port_id' => 0,
3657 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
3658 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
3659 
              'timingConstraint' => 'none',
3660 
              'type' => 'UFix_32_0',
3661 
            },
3662 
            'direction' => 'in',
3663 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3664 
            'width' => 32,
3665 
          },
3666 
        },
3667 
      },
3668 
      'entityName' => 'reg03_rd',
3669 
    },
3670 
    'reg03_rv' => {
3671 
      'connections' => {
3672 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
3673 
      },
3674 
      'entity' => {
3675 
        'attributes' => {
3676 
          'entityAlreadyNetlisted' => 1,
3677 
          'isGateway' => 1,
3678 
          'is_floating_block' => 1,
3679 
        },
3680 
        'entityName' => 'reg03_rv',
3681 
        'ports' => {
3682 
          'reg03_rv' => {
3683 
            'attributes' => {
3684 
              'bin_pt' => 0,
3685 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
3686 
              'is_floating_block' => 1,
3687 
              'is_gateway_port' => 1,
3688 
              'must_be_hdl_vector' => 1,
3689 
              'period' => 1,
3690 
              'port_id' => 0,
3691 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
3692 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
3693 
              'timingConstraint' => 'none',
3694 
              'type' => 'UFix_1_0',
3695 
            },
3696 
            'direction' => 'in',
3697 
            'hdlType' => 'std_logic',
3698 
            'width' => 1,
3699 
          },
3700 
        },
3701 
      },
3702 
      'entityName' => 'reg03_rv',
3703 
    },
3704 
    'reg03_td' => {
3705 
      'connections' => {
3706 
        'reg03_td' => '.reg03_td',
3707 
      },
3708 
      'entity' => {
3709 
        'attributes' => {
3710 
          'entityAlreadyNetlisted' => 1,
3711 
          'isGateway' => 1,
3712 
          'is_floating_block' => 1,
3713 
        },
3714 
        'entityName' => 'reg03_td',
3715 
        'ports' => {
3716 
          'reg03_td' => {
3717 
            'attributes' => {
3718 
              'bin_pt' => 0,
3719 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
3720 
              'is_floating_block' => 1,
3721 
              'is_gateway_port' => 1,
3722 
              'must_be_hdl_vector' => 1,
3723 
              'period' => 1,
3724 
              'port_id' => 0,
3725 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
3726 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
3727 
              'timingConstraint' => 'none',
3728 
              'type' => 'UFix_32_0',
3729 
            },
3730 
            'direction' => 'out',
3731 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3732 
            'width' => 32,
3733 
          },
3734 
        },
3735 
      },
3736 
      'entityName' => 'reg03_td',
3737 
    },
3738 
    'reg03_tv' => {
3739 
      'connections' => {
3740 
        'reg03_tv' => '.reg03_tv',
3741 
      },
3742 
      'entity' => {
3743 
        'attributes' => {
3744 
          'entityAlreadyNetlisted' => 1,
3745 
          'isGateway' => 1,
3746 
          'is_floating_block' => 1,
3747 
        },
3748 
        'entityName' => 'reg03_tv',
3749 
        'ports' => {
3750 
          'reg03_tv' => {
3751 
            'attributes' => {
3752 
              'bin_pt' => 0,
3753 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
3754 
              'is_floating_block' => 1,
3755 
              'is_gateway_port' => 1,
3756 
              'must_be_hdl_vector' => 1,
3757 
              'period' => 1,
3758 
              'port_id' => 0,
3759 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
3760 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
3761 
              'timingConstraint' => 'none',
3762 
              'type' => 'Bool',
3763 
            },
3764 
            'direction' => 'out',
3765 
            'hdlType' => 'std_logic',
3766 
            'width' => 1,
3767 
          },
3768 
        },
3769 
      },
3770 
      'entityName' => 'reg03_tv',
3771 
    },
3772 
    'reg04_rd' => {
3773 
      'connections' => {
3774 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
3775 
      },
3776 
      'entity' => {
3777 
        'attributes' => {
3778 
          'entityAlreadyNetlisted' => 1,
3779 
          'isGateway' => 1,
3780 
          'is_floating_block' => 1,
3781 
        },
3782 
        'entityName' => 'reg04_rd',
3783 
        'ports' => {
3784 
          'reg04_rd' => {
3785 
            'attributes' => {
3786 
              'bin_pt' => 0,
3787 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
3788 
              'is_floating_block' => 1,
3789 
              'is_gateway_port' => 1,
3790 
              'must_be_hdl_vector' => 1,
3791 
              'period' => 1,
3792 
              'port_id' => 0,
3793 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
3794 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
3795 
              'timingConstraint' => 'none',
3796 
              'type' => 'UFix_32_0',
3797 
            },
3798 
            'direction' => 'in',
3799 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3800 
            'width' => 32,
3801 
          },
3802 
        },
3803 
      },
3804 
      'entityName' => 'reg04_rd',
3805 
    },
3806 
    'reg04_rv' => {
3807 
      'connections' => {
3808 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
3809 
      },
3810 
      'entity' => {
3811 
        'attributes' => {
3812 
          'entityAlreadyNetlisted' => 1,
3813 
          'isGateway' => 1,
3814 
          'is_floating_block' => 1,
3815 
        },
3816 
        'entityName' => 'reg04_rv',
3817 
        'ports' => {
3818 
          'reg04_rv' => {
3819 
            'attributes' => {
3820 
              'bin_pt' => 0,
3821 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
3822 
              'is_floating_block' => 1,
3823 
              'is_gateway_port' => 1,
3824 
              'must_be_hdl_vector' => 1,
3825 
              'period' => 1,
3826 
              'port_id' => 0,
3827 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
3828 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
3829 
              'timingConstraint' => 'none',
3830 
              'type' => 'UFix_1_0',
3831 
            },
3832 
            'direction' => 'in',
3833 
            'hdlType' => 'std_logic',
3834 
            'width' => 1,
3835 
          },
3836 
        },
3837 
      },
3838 
      'entityName' => 'reg04_rv',
3839 
    },
3840 
    'reg04_td' => {
3841 
      'connections' => {
3842 
        'reg04_td' => '.reg04_td',
3843 
      },
3844 
      'entity' => {
3845 
        'attributes' => {
3846 
          'entityAlreadyNetlisted' => 1,
3847 
          'isGateway' => 1,
3848 
          'is_floating_block' => 1,
3849 
        },
3850 
        'entityName' => 'reg04_td',
3851 
        'ports' => {
3852 
          'reg04_td' => {
3853 
            'attributes' => {
3854 
              'bin_pt' => 0,
3855 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
3856 
              'is_floating_block' => 1,
3857 
              'is_gateway_port' => 1,
3858 
              'must_be_hdl_vector' => 1,
3859 
              'period' => 1,
3860 
              'port_id' => 0,
3861 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
3862 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
3863 
              'timingConstraint' => 'none',
3864 
              'type' => 'UFix_32_0',
3865 
            },
3866 
            'direction' => 'out',
3867 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3868 
            'width' => 32,
3869 
          },
3870 
        },
3871 
      },
3872 
      'entityName' => 'reg04_td',
3873 
    },
3874 
    'reg04_tv' => {
3875 
      'connections' => {
3876 
        'reg04_tv' => '.reg04_tv',
3877 
      },
3878 
      'entity' => {
3879 
        'attributes' => {
3880 
          'entityAlreadyNetlisted' => 1,
3881 
          'isGateway' => 1,
3882 
          'is_floating_block' => 1,
3883 
        },
3884 
        'entityName' => 'reg04_tv',
3885 
        'ports' => {
3886 
          'reg04_tv' => {
3887 
            'attributes' => {
3888 
              'bin_pt' => 0,
3889 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
3890 
              'is_floating_block' => 1,
3891 
              'is_gateway_port' => 1,
3892 
              'must_be_hdl_vector' => 1,
3893 
              'period' => 1,
3894 
              'port_id' => 0,
3895 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
3896 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
3897 
              'timingConstraint' => 'none',
3898 
              'type' => 'Bool',
3899 
            },
3900 
            'direction' => 'out',
3901 
            'hdlType' => 'std_logic',
3902 
            'width' => 1,
3903 
          },
3904 
        },
3905 
      },
3906 
      'entityName' => 'reg04_tv',
3907 
    },
3908 
    'reg05_rd' => {
3909 
      'connections' => {
3910 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
3911 
      },
3912 
      'entity' => {
3913 
        'attributes' => {
3914 
          'entityAlreadyNetlisted' => 1,
3915 
          'isGateway' => 1,
3916 
          'is_floating_block' => 1,
3917 
        },
3918 
        'entityName' => 'reg05_rd',
3919 
        'ports' => {
3920 
          'reg05_rd' => {
3921 
            'attributes' => {
3922 
              'bin_pt' => 0,
3923 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
3924 
              'is_floating_block' => 1,
3925 
              'is_gateway_port' => 1,
3926 
              'must_be_hdl_vector' => 1,
3927 
              'period' => 1,
3928 
              'port_id' => 0,
3929 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
3930 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
3931 
              'timingConstraint' => 'none',
3932 
              'type' => 'UFix_32_0',
3933 
            },
3934 
            'direction' => 'in',
3935 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3936 
            'width' => 32,
3937 
          },
3938 
        },
3939 
      },
3940 
      'entityName' => 'reg05_rd',
3941 
    },
3942 
    'reg05_rv' => {
3943 
      'connections' => {
3944 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
3945 
      },
3946 
      'entity' => {
3947 
        'attributes' => {
3948 
          'entityAlreadyNetlisted' => 1,
3949 
          'isGateway' => 1,
3950 
          'is_floating_block' => 1,
3951 
        },
3952 
        'entityName' => 'reg05_rv',
3953 
        'ports' => {
3954 
          'reg05_rv' => {
3955 
            'attributes' => {
3956 
              'bin_pt' => 0,
3957 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
3958 
              'is_floating_block' => 1,
3959 
              'is_gateway_port' => 1,
3960 
              'must_be_hdl_vector' => 1,
3961 
              'period' => 1,
3962 
              'port_id' => 0,
3963 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
3964 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
3965 
              'timingConstraint' => 'none',
3966 
              'type' => 'UFix_1_0',
3967 
            },
3968 
            'direction' => 'in',
3969 
            'hdlType' => 'std_logic',
3970 
            'width' => 1,
3971 
          },
3972 
        },
3973 
      },
3974 
      'entityName' => 'reg05_rv',
3975 
    },
3976 
    'reg05_td' => {
3977 
      'connections' => {
3978 
        'reg05_td' => '.reg05_td',
3979 
      },
3980 
      'entity' => {
3981 
        'attributes' => {
3982 
          'entityAlreadyNetlisted' => 1,
3983 
          'isGateway' => 1,
3984 
          'is_floating_block' => 1,
3985 
        },
3986 
        'entityName' => 'reg05_td',
3987 
        'ports' => {
3988 
          'reg05_td' => {
3989 
            'attributes' => {
3990 
              'bin_pt' => 0,
3991 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
3992 
              'is_floating_block' => 1,
3993 
              'is_gateway_port' => 1,
3994 
              'must_be_hdl_vector' => 1,
3995 
              'period' => 1,
3996 
              'port_id' => 0,
3997 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td/reg05_td',
3998 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
3999 
              'timingConstraint' => 'none',
4000 
              'type' => 'UFix_32_0',
4001 
            },
4002 
            'direction' => 'out',
4003 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4004 
            'width' => 32,
4005 
          },
4006 
        },
4007 
      },
4008 
      'entityName' => 'reg05_td',
4009 
    },
4010 
    'reg05_tv' => {
4011 
      'connections' => {
4012 
        'reg05_tv' => '.reg05_tv',
4013 
      },
4014 
      'entity' => {
4015 
        'attributes' => {
4016 
          'entityAlreadyNetlisted' => 1,
4017 
          'isGateway' => 1,
4018 
          'is_floating_block' => 1,
4019 
        },
4020 
        'entityName' => 'reg05_tv',
4021 
        'ports' => {
4022 
          'reg05_tv' => {
4023 
            'attributes' => {
4024 
              'bin_pt' => 0,
4025 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
4026 
              'is_floating_block' => 1,
4027 
              'is_gateway_port' => 1,
4028 
              'must_be_hdl_vector' => 1,
4029 
              'period' => 1,
4030 
              'port_id' => 0,
4031 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
4032 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
4033 
              'timingConstraint' => 'none',
4034 
              'type' => 'Bool',
4035 
            },
4036 
            'direction' => 'out',
4037 
            'hdlType' => 'std_logic',
4038 
            'width' => 1,
4039 
          },
4040 
        },
4041 
      },
4042 
      'entityName' => 'reg05_tv',
4043 
    },
4044 
    'reg06_rd' => {
4045 
      'connections' => {
4046 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
4047 
      },
4048 
      'entity' => {
4049 
        'attributes' => {
4050 
          'entityAlreadyNetlisted' => 1,
4051 
          'isGateway' => 1,
4052 
          'is_floating_block' => 1,
4053 
        },
4054 
        'entityName' => 'reg06_rd',
4055 
        'ports' => {
4056 
          'reg06_rd' => {
4057 
            'attributes' => {
4058 
              'bin_pt' => 0,
4059 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
4060 
              'is_floating_block' => 1,
4061 
              'is_gateway_port' => 1,
4062 
              'must_be_hdl_vector' => 1,
4063 
              'period' => 1,
4064 
              'port_id' => 0,
4065 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
4066 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
4067 
              'timingConstraint' => 'none',
4068 
              'type' => 'UFix_32_0',
4069 
            },
4070 
            'direction' => 'in',
4071 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4072 
            'width' => 32,
4073 
          },
4074 
        },
4075 
      },
4076 
      'entityName' => 'reg06_rd',
4077 
    },
4078 
    'reg06_rv' => {
4079 
      'connections' => {
4080 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
4081 
      },
4082 
      'entity' => {
4083 
        'attributes' => {
4084 
          'entityAlreadyNetlisted' => 1,
4085 
          'isGateway' => 1,
4086 
          'is_floating_block' => 1,
4087 
        },
4088 
        'entityName' => 'reg06_rv',
4089 
        'ports' => {
4090 
          'reg06_rv' => {
4091 
            'attributes' => {
4092 
              'bin_pt' => 0,
4093 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
4094 
              'is_floating_block' => 1,
4095 
              'is_gateway_port' => 1,
4096 
              'must_be_hdl_vector' => 1,
4097 
              'period' => 1,
4098 
              'port_id' => 0,
4099 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
4100 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
4101 
              'timingConstraint' => 'none',
4102 
              'type' => 'UFix_1_0',
4103 
            },
4104 
            'direction' => 'in',
4105 
            'hdlType' => 'std_logic',
4106 
            'width' => 1,
4107 
          },
4108 
        },
4109 
      },
4110 
      'entityName' => 'reg06_rv',
4111 
    },
4112 
    'reg06_td' => {
4113 
      'connections' => {
4114 
        'reg06_td' => '.reg06_td',
4115 
      },
4116 
      'entity' => {
4117 
        'attributes' => {
4118 
          'entityAlreadyNetlisted' => 1,
4119 
          'isGateway' => 1,
4120 
          'is_floating_block' => 1,
4121 
        },
4122 
        'entityName' => 'reg06_td',
4123 
        'ports' => {
4124 
          'reg06_td' => {
4125 
            'attributes' => {
4126 
              'bin_pt' => 0,
4127 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
4128 
              'is_floating_block' => 1,
4129 
              'is_gateway_port' => 1,
4130 
              'must_be_hdl_vector' => 1,
4131 
              'period' => 1,
4132 
              'port_id' => 0,
4133 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
4134 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
4135 
              'timingConstraint' => 'none',
4136 
              'type' => 'UFix_32_0',
4137 
            },
4138 
            'direction' => 'out',
4139 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4140 
            'width' => 32,
4141 
          },
4142 
        },
4143 
      },
4144 
      'entityName' => 'reg06_td',
4145 
    },
4146 
    'reg06_tv' => {
4147 
      'connections' => {
4148 
        'reg06_tv' => '.reg06_tv',
4149 
      },
4150 
      'entity' => {
4151 
        'attributes' => {
4152 
          'entityAlreadyNetlisted' => 1,
4153 
          'isGateway' => 1,
4154 
          'is_floating_block' => 1,
4155 
        },
4156 
        'entityName' => 'reg06_tv',
4157 
        'ports' => {
4158 
          'reg06_tv' => {
4159 
            'attributes' => {
4160 
              'bin_pt' => 0,
4161 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
4162 
              'is_floating_block' => 1,
4163 
              'is_gateway_port' => 1,
4164 
              'must_be_hdl_vector' => 1,
4165 
              'period' => 1,
4166 
              'port_id' => 0,
4167 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
4168 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
4169 
              'timingConstraint' => 'none',
4170 
              'type' => 'Bool',
4171 
            },
4172 
            'direction' => 'out',
4173 
            'hdlType' => 'std_logic',
4174 
            'width' => 1,
4175 
          },
4176 
        },
4177 
      },
4178 
      'entityName' => 'reg06_tv',
4179 
    },
4180 
    'reg07_rd' => {
4181 
      'connections' => {
4182 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
4183 
      },
4184 
      'entity' => {
4185 
        'attributes' => {
4186 
          'entityAlreadyNetlisted' => 1,
4187 
          'isGateway' => 1,
4188 
          'is_floating_block' => 1,
4189 
        },
4190 
        'entityName' => 'reg07_rd',
4191 
        'ports' => {
4192 
          'reg07_rd' => {
4193 
            'attributes' => {
4194 
              'bin_pt' => 0,
4195 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
4196 
              'is_floating_block' => 1,
4197 
              'is_gateway_port' => 1,
4198 
              'must_be_hdl_vector' => 1,
4199 
              'period' => 1,
4200 
              'port_id' => 0,
4201 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
4202 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
4203 
              'timingConstraint' => 'none',
4204 
              'type' => 'UFix_32_0',
4205 
            },
4206 
            'direction' => 'in',
4207 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4208 
            'width' => 32,
4209 
          },
4210 
        },
4211 
      },
4212 
      'entityName' => 'reg07_rd',
4213 
    },
4214 
    'reg07_rv' => {
4215 
      'connections' => {
4216 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
4217 
      },
4218 
      'entity' => {
4219 
        'attributes' => {
4220 
          'entityAlreadyNetlisted' => 1,
4221 
          'isGateway' => 1,
4222 
          'is_floating_block' => 1,
4223 
        },
4224 
        'entityName' => 'reg07_rv',
4225 
        'ports' => {
4226 
          'reg07_rv' => {
4227 
            'attributes' => {
4228 
              'bin_pt' => 0,
4229 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
4230 
              'is_floating_block' => 1,
4231 
              'is_gateway_port' => 1,
4232 
              'must_be_hdl_vector' => 1,
4233 
              'period' => 1,
4234 
              'port_id' => 0,
4235 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
4236 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
4237 
              'timingConstraint' => 'none',
4238 
              'type' => 'UFix_1_0',
4239 
            },
4240 
            'direction' => 'in',
4241 
            'hdlType' => 'std_logic',
4242 
            'width' => 1,
4243 
          },
4244 
        },
4245 
      },
4246 
      'entityName' => 'reg07_rv',
4247 
    },
4248 
    'reg07_td' => {
4249 
      'connections' => {
4250 
        'reg07_td' => '.reg07_td',
4251 
      },
4252 
      'entity' => {
4253 
        'attributes' => {
4254 
          'entityAlreadyNetlisted' => 1,
4255 
          'isGateway' => 1,
4256 
          'is_floating_block' => 1,
4257 
        },
4258 
        'entityName' => 'reg07_td',
4259 
        'ports' => {
4260 
          'reg07_td' => {
4261 
            'attributes' => {
4262 
              'bin_pt' => 0,
4263 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
4264 
              'is_floating_block' => 1,
4265 
              'is_gateway_port' => 1,
4266 
              'must_be_hdl_vector' => 1,
4267 
              'period' => 1,
4268 
              'port_id' => 0,
4269 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
4270 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
4271 
              'timingConstraint' => 'none',
4272 
              'type' => 'UFix_32_0',
4273 
            },
4274 
            'direction' => 'out',
4275 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4276 
            'width' => 32,
4277 
          },
4278 
        },
4279 
      },
4280 
      'entityName' => 'reg07_td',
4281 
    },
4282 
    'reg07_tv' => {
4283 
      'connections' => {
4284 
        'reg07_tv' => '.reg07_tv',
4285 
      },
4286 
      'entity' => {
4287 
        'attributes' => {
4288 
          'entityAlreadyNetlisted' => 1,
4289 
          'isGateway' => 1,
4290 
          'is_floating_block' => 1,
4291 
        },
4292 
        'entityName' => 'reg07_tv',
4293 
        'ports' => {
4294 
          'reg07_tv' => {
4295 
            'attributes' => {
4296 
              'bin_pt' => 0,
4297 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
4298 
              'is_floating_block' => 1,
4299 
              'is_gateway_port' => 1,
4300 
              'must_be_hdl_vector' => 1,
4301 
              'period' => 1,
4302 
              'port_id' => 0,
4303 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
4304 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
4305 
              'timingConstraint' => 'none',
4306 
              'type' => 'Bool',
4307 
            },
4308 
            'direction' => 'out',
4309 
            'hdlType' => 'std_logic',
4310 
            'width' => 1,
4311 
          },
4312 
        },
4313 
      },
4314 
      'entityName' => 'reg07_tv',
4315 
    },
4316 
    'reg08_rd' => {
4317 
      'connections' => {
4318 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
4319 
      },
4320 
      'entity' => {
4321 
        'attributes' => {
4322 
          'entityAlreadyNetlisted' => 1,
4323 
          'isGateway' => 1,
4324 
          'is_floating_block' => 1,
4325 
        },
4326 
        'entityName' => 'reg08_rd',
4327 
        'ports' => {
4328 
          'reg08_rd' => {
4329 
            'attributes' => {
4330 
              'bin_pt' => 0,
4331 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
4332 
              'is_floating_block' => 1,
4333 
              'is_gateway_port' => 1,
4334 
              'must_be_hdl_vector' => 1,
4335 
              'period' => 1,
4336 
              'port_id' => 0,
4337 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
4338 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
4339 
              'timingConstraint' => 'none',
4340 
              'type' => 'UFix_32_0',
4341 
            },
4342 
            'direction' => 'in',
4343 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4344 
            'width' => 32,
4345 
          },
4346 
        },
4347 
      },
4348 
      'entityName' => 'reg08_rd',
4349 
    },
4350 
    'reg08_rv' => {
4351 
      'connections' => {
4352 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
4353 
      },
4354 
      'entity' => {
4355 
        'attributes' => {
4356 
          'entityAlreadyNetlisted' => 1,
4357 
          'isGateway' => 1,
4358 
          'is_floating_block' => 1,
4359 
        },
4360 
        'entityName' => 'reg08_rv',
4361 
        'ports' => {
4362 
          'reg08_rv' => {
4363 
            'attributes' => {
4364 
              'bin_pt' => 0,
4365 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
4366 
              'is_floating_block' => 1,
4367 
              'is_gateway_port' => 1,
4368 
              'must_be_hdl_vector' => 1,
4369 
              'period' => 1,
4370 
              'port_id' => 0,
4371 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
4372 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
4373 
              'timingConstraint' => 'none',
4374 
              'type' => 'UFix_1_0',
4375 
            },
4376 
            'direction' => 'in',
4377 
            'hdlType' => 'std_logic',
4378 
            'width' => 1,
4379 
          },
4380 
        },
4381 
      },
4382 
      'entityName' => 'reg08_rv',
4383 
    },
4384 
    'reg08_td' => {
4385 
      'connections' => {
4386 
        'reg08_td' => '.reg08_td',
4387 
      },
4388 
      'entity' => {
4389 
        'attributes' => {
4390 
          'entityAlreadyNetlisted' => 1,
4391 
          'isGateway' => 1,
4392 
          'is_floating_block' => 1,
4393 
        },
4394 
        'entityName' => 'reg08_td',
4395 
        'ports' => {
4396 
          'reg08_td' => {
4397 
            'attributes' => {
4398 
              'bin_pt' => 0,
4399 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
4400 
              'is_floating_block' => 1,
4401 
              'is_gateway_port' => 1,
4402 
              'must_be_hdl_vector' => 1,
4403 
              'period' => 1,
4404 
              'port_id' => 0,
4405 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
4406 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
4407 
              'timingConstraint' => 'none',
4408 
              'type' => 'UFix_32_0',
4409 
            },
4410 
            'direction' => 'out',
4411 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4412 
            'width' => 32,
4413 
          },
4414 
        },
4415 
      },
4416 
      'entityName' => 'reg08_td',
4417 
    },
4418 
    'reg08_tv' => {
4419 
      'connections' => {
4420 
        'reg08_tv' => '.reg08_tv',
4421 
      },
4422 
      'entity' => {
4423 
        'attributes' => {
4424 
          'entityAlreadyNetlisted' => 1,
4425 
          'isGateway' => 1,
4426 
          'is_floating_block' => 1,
4427 
        },
4428 
        'entityName' => 'reg08_tv',
4429 
        'ports' => {
4430 
          'reg08_tv' => {
4431 
            'attributes' => {
4432 
              'bin_pt' => 0,
4433 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
4434 
              'is_floating_block' => 1,
4435 
              'is_gateway_port' => 1,
4436 
              'must_be_hdl_vector' => 1,
4437 
              'period' => 1,
4438 
              'port_id' => 0,
4439 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
4440 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
4441 
              'timingConstraint' => 'none',
4442 
              'type' => 'Bool',
4443 
            },
4444 
            'direction' => 'out',
4445 
            'hdlType' => 'std_logic',
4446 
            'width' => 1,
4447 
          },
4448 
        },
4449 
      },
4450 
      'entityName' => 'reg08_tv',
4451 
    },
4452 
    'reg09_rd' => {
4453 
      'connections' => {
4454 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
4455 
      },
4456 
      'entity' => {
4457 
        'attributes' => {
4458 
          'entityAlreadyNetlisted' => 1,
4459 
          'isGateway' => 1,
4460 
          'is_floating_block' => 1,
4461 
        },
4462 
        'entityName' => 'reg09_rd',
4463 
        'ports' => {
4464 
          'reg09_rd' => {
4465 
            'attributes' => {
4466 
              'bin_pt' => 0,
4467 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
4468 
              'is_floating_block' => 1,
4469 
              'is_gateway_port' => 1,
4470 
              'must_be_hdl_vector' => 1,
4471 
              'period' => 1,
4472 
              'port_id' => 0,
4473 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
4474 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
4475 
              'timingConstraint' => 'none',
4476 
              'type' => 'UFix_32_0',
4477 
            },
4478 
            'direction' => 'in',
4479 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4480 
            'width' => 32,
4481 
          },
4482 
        },
4483 
      },
4484 
      'entityName' => 'reg09_rd',
4485 
    },
4486 
    'reg09_rv' => {
4487 
      'connections' => {
4488 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
4489 
      },
4490 
      'entity' => {
4491 
        'attributes' => {
4492 
          'entityAlreadyNetlisted' => 1,
4493 
          'isGateway' => 1,
4494 
          'is_floating_block' => 1,
4495 
        },
4496 
        'entityName' => 'reg09_rv',
4497 
        'ports' => {
4498 
          'reg09_rv' => {
4499 
            'attributes' => {
4500 
              'bin_pt' => 0,
4501 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
4502 
              'is_floating_block' => 1,
4503 
              'is_gateway_port' => 1,
4504 
              'must_be_hdl_vector' => 1,
4505 
              'period' => 1,
4506 
              'port_id' => 0,
4507 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
4508 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
4509 
              'timingConstraint' => 'none',
4510 
              'type' => 'UFix_1_0',
4511 
            },
4512 
            'direction' => 'in',
4513 
            'hdlType' => 'std_logic',
4514 
            'width' => 1,
4515 
          },
4516 
        },
4517 
      },
4518 
      'entityName' => 'reg09_rv',
4519 
    },
4520 
    'reg09_td' => {
4521 
      'connections' => {
4522 
        'reg09_td' => '.reg09_td',
4523 
      },
4524 
      'entity' => {
4525 
        'attributes' => {
4526 
          'entityAlreadyNetlisted' => 1,
4527 
          'isGateway' => 1,
4528 
          'is_floating_block' => 1,
4529 
        },
4530 
        'entityName' => 'reg09_td',
4531 
        'ports' => {
4532 
          'reg09_td' => {
4533 
            'attributes' => {
4534 
              'bin_pt' => 0,
4535 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
4536 
              'is_floating_block' => 1,
4537 
              'is_gateway_port' => 1,
4538 
              'must_be_hdl_vector' => 1,
4539 
              'period' => 1,
4540 
              'port_id' => 0,
4541 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
4542 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
4543 
              'timingConstraint' => 'none',
4544 
              'type' => 'UFix_32_0',
4545 
            },
4546 
            'direction' => 'out',
4547 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4548 
            'width' => 32,
4549 
          },
4550 
        },
4551 
      },
4552 
      'entityName' => 'reg09_td',
4553 
    },
4554 
    'reg09_tv' => {
4555 
      'connections' => {
4556 
        'reg09_tv' => '.reg09_tv',
4557 
      },
4558 
      'entity' => {
4559 
        'attributes' => {
4560 
          'entityAlreadyNetlisted' => 1,
4561 
          'isGateway' => 1,
4562 
          'is_floating_block' => 1,
4563 
        },
4564 
        'entityName' => 'reg09_tv',
4565 
        'ports' => {
4566 
          'reg09_tv' => {
4567 
            'attributes' => {
4568 
              'bin_pt' => 0,
4569 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
4570 
              'is_floating_block' => 1,
4571 
              'is_gateway_port' => 1,
4572 
              'must_be_hdl_vector' => 1,
4573 
              'period' => 1,
4574 
              'port_id' => 0,
4575 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
4576 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
4577 
              'timingConstraint' => 'none',
4578 
              'type' => 'Bool',
4579 
            },
4580 
            'direction' => 'out',
4581 
            'hdlType' => 'std_logic',
4582 
            'width' => 1,
4583 
          },
4584 
        },
4585 
      },
4586 
      'entityName' => 'reg09_tv',
4587 
    },
4588 
    'reg10_rd' => {
4589 
      'connections' => {
4590 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
4591 
      },
4592 
      'entity' => {
4593 
        'attributes' => {
4594 
          'entityAlreadyNetlisted' => 1,
4595 
          'isGateway' => 1,
4596 
          'is_floating_block' => 1,
4597 
        },
4598 
        'entityName' => 'reg10_rd',
4599 
        'ports' => {
4600 
          'reg10_rd' => {
4601 
            'attributes' => {
4602 
              'bin_pt' => 0,
4603 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
4604 
              'is_floating_block' => 1,
4605 
              'is_gateway_port' => 1,
4606 
              'must_be_hdl_vector' => 1,
4607 
              'period' => 1,
4608 
              'port_id' => 0,
4609 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
4610 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
4611 
              'timingConstraint' => 'none',
4612 
              'type' => 'UFix_32_0',
4613 
            },
4614 
            'direction' => 'in',
4615 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4616 
            'width' => 32,
4617 
          },
4618 
        },
4619 
      },
4620 
      'entityName' => 'reg10_rd',
4621 
    },
4622 
    'reg10_rv' => {
4623 
      'connections' => {
4624 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
4625 
      },
4626 
      'entity' => {
4627 
        'attributes' => {
4628 
          'entityAlreadyNetlisted' => 1,
4629 
          'isGateway' => 1,
4630 
          'is_floating_block' => 1,
4631 
        },
4632 
        'entityName' => 'reg10_rv',
4633 
        'ports' => {
4634 
          'reg10_rv' => {
4635 
            'attributes' => {
4636 
              'bin_pt' => 0,
4637 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
4638 
              'is_floating_block' => 1,
4639 
              'is_gateway_port' => 1,
4640 
              'must_be_hdl_vector' => 1,
4641 
              'period' => 1,
4642 
              'port_id' => 0,
4643 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
4644 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
4645 
              'timingConstraint' => 'none',
4646 
              'type' => 'UFix_1_0',
4647 
            },
4648 
            'direction' => 'in',
4649 
            'hdlType' => 'std_logic',
4650 
            'width' => 1,
4651 
          },
4652 
        },
4653 
      },
4654 
      'entityName' => 'reg10_rv',
4655 
    },
4656 
    'reg10_td' => {
4657 
      'connections' => {
4658 
        'reg10_td' => '.reg10_td',
4659 
      },
4660 
      'entity' => {
4661 
        'attributes' => {
4662 
          'entityAlreadyNetlisted' => 1,
4663 
          'isGateway' => 1,
4664 
          'is_floating_block' => 1,
4665 
        },
4666 
        'entityName' => 'reg10_td',
4667 
        'ports' => {
4668 
          'reg10_td' => {
4669 
            'attributes' => {
4670 
              'bin_pt' => 0,
4671 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
4672 
              'is_floating_block' => 1,
4673 
              'is_gateway_port' => 1,
4674 
              'must_be_hdl_vector' => 1,
4675 
              'period' => 1,
4676 
              'port_id' => 0,
4677 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td/reg10_td',
4678 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
4679 
              'timingConstraint' => 'none',
4680 
              'type' => 'UFix_32_0',
4681 
            },
4682 
            'direction' => 'out',
4683 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4684 
            'width' => 32,
4685 
          },
4686 
        },
4687 
      },
4688 
      'entityName' => 'reg10_td',
4689 
    },
4690 
    'reg10_tv' => {
4691 
      'connections' => {
4692 
        'reg10_tv' => '.reg10_tv',
4693 
      },
4694 
      'entity' => {
4695 
        'attributes' => {
4696 
          'entityAlreadyNetlisted' => 1,
4697 
          'isGateway' => 1,
4698 
          'is_floating_block' => 1,
4699 
        },
4700 
        'entityName' => 'reg10_tv',
4701 
        'ports' => {
4702 
          'reg10_tv' => {
4703 
            'attributes' => {
4704 
              'bin_pt' => 0,
4705 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
4706 
              'is_floating_block' => 1,
4707 
              'is_gateway_port' => 1,
4708 
              'must_be_hdl_vector' => 1,
4709 
              'period' => 1,
4710 
              'port_id' => 0,
4711 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
4712 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
4713 
              'timingConstraint' => 'none',
4714 
              'type' => 'Bool',
4715 
            },
4716 
            'direction' => 'out',
4717 
            'hdlType' => 'std_logic',
4718 
            'width' => 1,
4719 
          },
4720 
        },
4721 
      },
4722 
      'entityName' => 'reg10_tv',
4723 
    },
4724 
    'reg11_rd' => {
4725 
      'connections' => {
4726 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
4727 
      },
4728 
      'entity' => {
4729 
        'attributes' => {
4730 
          'entityAlreadyNetlisted' => 1,
4731 
          'isGateway' => 1,
4732 
          'is_floating_block' => 1,
4733 
        },
4734 
        'entityName' => 'reg11_rd',
4735 
        'ports' => {
4736 
          'reg11_rd' => {
4737 
            'attributes' => {
4738 
              'bin_pt' => 0,
4739 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
4740 
              'is_floating_block' => 1,
4741 
              'is_gateway_port' => 1,
4742 
              'must_be_hdl_vector' => 1,
4743 
              'period' => 1,
4744 
              'port_id' => 0,
4745 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
4746 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
4747 
              'timingConstraint' => 'none',
4748 
              'type' => 'UFix_32_0',
4749 
            },
4750 
            'direction' => 'in',
4751 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4752 
            'width' => 32,
4753 
          },
4754 
        },
4755 
      },
4756 
      'entityName' => 'reg11_rd',
4757 
    },
4758 
    'reg11_rv' => {
4759 
      'connections' => {
4760 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
4761 
      },
4762 
      'entity' => {
4763 
        'attributes' => {
4764 
          'entityAlreadyNetlisted' => 1,
4765 
          'isGateway' => 1,
4766 
          'is_floating_block' => 1,
4767 
        },
4768 
        'entityName' => 'reg11_rv',
4769 
        'ports' => {
4770 
          'reg11_rv' => {
4771 
            'attributes' => {
4772 
              'bin_pt' => 0,
4773 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
4774 
              'is_floating_block' => 1,
4775 
              'is_gateway_port' => 1,
4776 
              'must_be_hdl_vector' => 1,
4777 
              'period' => 1,
4778 
              'port_id' => 0,
4779 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv/reg11_rv',
4780 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
4781 
              'timingConstraint' => 'none',
4782 
              'type' => 'UFix_1_0',
4783 
            },
4784 
            'direction' => 'in',
4785 
            'hdlType' => 'std_logic',
4786 
            'width' => 1,
4787 
          },
4788 
        },
4789 
      },
4790 
      'entityName' => 'reg11_rv',
4791 
    },
4792 
    'reg11_td' => {
4793 
      'connections' => {
4794 
        'reg11_td' => '.reg11_td',
4795 
      },
4796 
      'entity' => {
4797 
        'attributes' => {
4798 
          'entityAlreadyNetlisted' => 1,
4799 
          'isGateway' => 1,
4800 
          'is_floating_block' => 1,
4801 
        },
4802 
        'entityName' => 'reg11_td',
4803 
        'ports' => {
4804 
          'reg11_td' => {
4805 
            'attributes' => {
4806 
              'bin_pt' => 0,
4807 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
4808 
              'is_floating_block' => 1,
4809 
              'is_gateway_port' => 1,
4810 
              'must_be_hdl_vector' => 1,
4811 
              'period' => 1,
4812 
              'port_id' => 0,
4813 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td/reg11_td',
4814 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
4815 
              'timingConstraint' => 'none',
4816 
              'type' => 'UFix_32_0',
4817 
            },
4818 
            'direction' => 'out',
4819 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4820 
            'width' => 32,
4821 
          },
4822 
        },
4823 
      },
4824 
      'entityName' => 'reg11_td',
4825 
    },
4826 
    'reg11_tv' => {
4827 
      'connections' => {
4828 
        'reg11_tv' => '.reg11_tv',
4829 
      },
4830 
      'entity' => {
4831 
        'attributes' => {
4832 
          'entityAlreadyNetlisted' => 1,
4833 
          'isGateway' => 1,
4834 
          'is_floating_block' => 1,
4835 
        },
4836 
        'entityName' => 'reg11_tv',
4837 
        'ports' => {
4838 
          'reg11_tv' => {
4839 
            'attributes' => {
4840 
              'bin_pt' => 0,
4841 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
4842 
              'is_floating_block' => 1,
4843 
              'is_gateway_port' => 1,
4844 
              'must_be_hdl_vector' => 1,
4845 
              'period' => 1,
4846 
              'port_id' => 0,
4847 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv/reg11_tv',
4848 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
4849 
              'timingConstraint' => 'none',
4850 
              'type' => 'Bool',
4851 
            },
4852 
            'direction' => 'out',
4853 
            'hdlType' => 'std_logic',
4854 
            'width' => 1,
4855 
          },
4856 
        },
4857 
      },
4858 
      'entityName' => 'reg11_tv',
4859 
    },
4860 
    'reg12_rd' => {
4861 
      'connections' => {
4862 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
4863 
      },
4864 
      'entity' => {
4865 
        'attributes' => {
4866 
          'entityAlreadyNetlisted' => 1,
4867 
          'isGateway' => 1,
4868 
          'is_floating_block' => 1,
4869 
        },
4870 
        'entityName' => 'reg12_rd',
4871 
        'ports' => {
4872 
          'reg12_rd' => {
4873 
            'attributes' => {
4874 
              'bin_pt' => 0,
4875 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
4876 
              'is_floating_block' => 1,
4877 
              'is_gateway_port' => 1,
4878 
              'must_be_hdl_vector' => 1,
4879 
              'period' => 1,
4880 
              'port_id' => 0,
4881 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd/reg12_rd',
4882 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
4883 
              'timingConstraint' => 'none',
4884 
              'type' => 'UFix_32_0',
4885 
            },
4886 
            'direction' => 'in',
4887 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4888 
            'width' => 32,
4889 
          },
4890 
        },
4891 
      },
4892 
      'entityName' => 'reg12_rd',
4893 
    },
4894 
    'reg12_rv' => {
4895 
      'connections' => {
4896 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
4897 
      },
4898 
      'entity' => {
4899 
        'attributes' => {
4900 
          'entityAlreadyNetlisted' => 1,
4901 
          'isGateway' => 1,
4902 
          'is_floating_block' => 1,
4903 
        },
4904 
        'entityName' => 'reg12_rv',
4905 
        'ports' => {
4906 
          'reg12_rv' => {
4907 
            'attributes' => {
4908 
              'bin_pt' => 0,
4909 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
4910 
              'is_floating_block' => 1,
4911 
              'is_gateway_port' => 1,
4912 
              'must_be_hdl_vector' => 1,
4913 
              'period' => 1,
4914 
              'port_id' => 0,
4915 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv/reg12_rv',
4916 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
4917 
              'timingConstraint' => 'none',
4918 
              'type' => 'UFix_1_0',
4919 
            },
4920 
            'direction' => 'in',
4921 
            'hdlType' => 'std_logic',
4922 
            'width' => 1,
4923 
          },
4924 
        },
4925 
      },
4926 
      'entityName' => 'reg12_rv',
4927 
    },
4928 
    'reg12_td' => {
4929 
      'connections' => {
4930 
        'reg12_td' => '.reg12_td',
4931 
      },
4932 
      'entity' => {
4933 
        'attributes' => {
4934 
          'entityAlreadyNetlisted' => 1,
4935 
          'isGateway' => 1,
4936 
          'is_floating_block' => 1,
4937 
        },
4938 
        'entityName' => 'reg12_td',
4939 
        'ports' => {
4940 
          'reg12_td' => {
4941 
            'attributes' => {
4942 
              'bin_pt' => 0,
4943 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
4944 
              'is_floating_block' => 1,
4945 
              'is_gateway_port' => 1,
4946 
              'must_be_hdl_vector' => 1,
4947 
              'period' => 1,
4948 
              'port_id' => 0,
4949 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td/reg12_td',
4950 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td',
4951 
              'timingConstraint' => 'none',
4952 
              'type' => 'UFix_32_0',
4953 
            },
4954 
            'direction' => 'out',
4955 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4956 
            'width' => 32,
4957 
          },
4958 
        },
4959 
      },
4960 
      'entityName' => 'reg12_td',
4961 
    },
4962 
    'reg12_tv' => {
4963 
      'connections' => {
4964 
        'reg12_tv' => '.reg12_tv',
4965 
      },
4966 
      'entity' => {
4967 
        'attributes' => {
4968 
          'entityAlreadyNetlisted' => 1,
4969 
          'isGateway' => 1,
4970 
          'is_floating_block' => 1,
4971 
        },
4972 
        'entityName' => 'reg12_tv',
4973 
        'ports' => {
4974 
          'reg12_tv' => {
4975 
            'attributes' => {
4976 
              'bin_pt' => 0,
4977 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
4978 
              'is_floating_block' => 1,
4979 
              'is_gateway_port' => 1,
4980 
              'must_be_hdl_vector' => 1,
4981 
              'period' => 1,
4982 
              'port_id' => 0,
4983 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv/reg12_tv',
4984 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
4985 
              'timingConstraint' => 'none',
4986 
              'type' => 'Bool',
4987 
            },
4988 
            'direction' => 'out',
4989 
            'hdlType' => 'std_logic',
4990 
            'width' => 1,
4991 
          },
4992 
        },
4993 
      },
4994 
      'entityName' => 'reg12_tv',
4995 
    },
4996 
    'reg13_rd' => {
4997 
      'connections' => {
4998 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
4999 
      },
5000 
      'entity' => {
5001 
        'attributes' => {
5002 
          'entityAlreadyNetlisted' => 1,
5003 
          'isGateway' => 1,
5004 
          'is_floating_block' => 1,
5005 
        },
5006 
        'entityName' => 'reg13_rd',
5007 
        'ports' => {
5008 
          'reg13_rd' => {
5009 
            'attributes' => {
5010 
              'bin_pt' => 0,
5011 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
5012 
              'is_floating_block' => 1,
5013 
              'is_gateway_port' => 1,
5014 
              'must_be_hdl_vector' => 1,
5015 
              'period' => 1,
5016 
              'port_id' => 0,
5017 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd/reg13_rd',
5018 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
5019 
              'timingConstraint' => 'none',
5020 
              'type' => 'UFix_32_0',
5021 
            },
5022 
            'direction' => 'in',
5023 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5024 
            'width' => 32,
5025 
          },
5026 
        },
5027 
      },
5028 
      'entityName' => 'reg13_rd',
5029 
    },
5030 
    'reg13_rv' => {
5031 
      'connections' => {
5032 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
5033 
      },
5034 
      'entity' => {
5035 
        'attributes' => {
5036 
          'entityAlreadyNetlisted' => 1,
5037 
          'isGateway' => 1,
5038 
          'is_floating_block' => 1,
5039 
        },
5040 
        'entityName' => 'reg13_rv',
5041 
        'ports' => {
5042 
          'reg13_rv' => {
5043 
            'attributes' => {
5044 
              'bin_pt' => 0,
5045 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
5046 
              'is_floating_block' => 1,
5047 
              'is_gateway_port' => 1,
5048 
              'must_be_hdl_vector' => 1,
5049 
              'period' => 1,
5050 
              'port_id' => 0,
5051 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
5052 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
5053 
              'timingConstraint' => 'none',
5054 
              'type' => 'UFix_1_0',
5055 
            },
5056 
            'direction' => 'in',
5057 
            'hdlType' => 'std_logic',
5058 
            'width' => 1,
5059 
          },
5060 
        },
5061 
      },
5062 
      'entityName' => 'reg13_rv',
5063 
    },
5064 
    'reg13_td' => {
5065 
      'connections' => {
5066 
        'reg13_td' => '.reg13_td',
5067 
      },
5068 
      'entity' => {
5069 
        'attributes' => {
5070 
          'entityAlreadyNetlisted' => 1,
5071 
          'isGateway' => 1,
5072 
          'is_floating_block' => 1,
5073 
        },
5074 
        'entityName' => 'reg13_td',
5075 
        'ports' => {
5076 
          'reg13_td' => {
5077 
            'attributes' => {
5078 
              'bin_pt' => 0,
5079 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
5080 
              'is_floating_block' => 1,
5081 
              'is_gateway_port' => 1,
5082 
              'must_be_hdl_vector' => 1,
5083 
              'period' => 1,
5084 
              'port_id' => 0,
5085 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
5086 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
5087 
              'timingConstraint' => 'none',
5088 
              'type' => 'UFix_32_0',
5089 
            },
5090 
            'direction' => 'out',
5091 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5092 
            'width' => 32,
5093 
          },
5094 
        },
5095 
      },
5096 
      'entityName' => 'reg13_td',
5097 
    },
5098 
    'reg13_tv' => {
5099 
      'connections' => {
5100 
        'reg13_tv' => '.reg13_tv',
5101 
      },
5102 
      'entity' => {
5103 
        'attributes' => {
5104 
          'entityAlreadyNetlisted' => 1,
5105 
          'isGateway' => 1,
5106 
          'is_floating_block' => 1,
5107 
        },
5108 
        'entityName' => 'reg13_tv',
5109 
        'ports' => {
5110 
          'reg13_tv' => {
5111 
            'attributes' => {
5112 
              'bin_pt' => 0,
5113 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
5114 
              'is_floating_block' => 1,
5115 
              'is_gateway_port' => 1,
5116 
              'must_be_hdl_vector' => 1,
5117 
              'period' => 1,
5118 
              'port_id' => 0,
5119 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
5120 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
5121 
              'timingConstraint' => 'none',
5122 
              'type' => 'Bool',
5123 
            },
5124 
            'direction' => 'out',
5125 
            'hdlType' => 'std_logic',
5126 
            'width' => 1,
5127 
          },
5128 
        },
5129 
      },
5130 
      'entityName' => 'reg13_tv',
5131 
    },
5132 
    'reg14_rd' => {
5133 
      'connections' => {
5134 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5135 
      },
5136 
      'entity' => {
5137 
        'attributes' => {
5138 
          'entityAlreadyNetlisted' => 1,
5139 
          'isGateway' => 1,
5140 
          'is_floating_block' => 1,
5141 
        },
5142 
        'entityName' => 'reg14_rd',
5143 
        'ports' => {
5144 
          'reg14_rd' => {
5145 
            'attributes' => {
5146 
              'bin_pt' => 0,
5147 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
5148 
              'is_floating_block' => 1,
5149 
              'is_gateway_port' => 1,
5150 
              'must_be_hdl_vector' => 1,
5151 
              'period' => 1,
5152 
              'port_id' => 0,
5153 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
5154 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
5155 
              'timingConstraint' => 'none',
5156 
              'type' => 'UFix_32_0',
5157 
            },
5158 
            'direction' => 'in',
5159 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5160 
            'width' => 32,
5161 
          },
5162 
        },
5163 
      },
5164 
      'entityName' => 'reg14_rd',
5165 
    },
5166 
    'reg14_rv' => {
5167 
      'connections' => {
5168 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5169 
      },
5170 
      'entity' => {
5171 
        'attributes' => {
5172 
          'entityAlreadyNetlisted' => 1,
5173 
          'isGateway' => 1,
5174 
          'is_floating_block' => 1,
5175 
        },
5176 
        'entityName' => 'reg14_rv',
5177 
        'ports' => {
5178 
          'reg14_rv' => {
5179 
            'attributes' => {
5180 
              'bin_pt' => 0,
5181 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
5182 
              'is_floating_block' => 1,
5183 
              'is_gateway_port' => 1,
5184 
              'must_be_hdl_vector' => 1,
5185 
              'period' => 1,
5186 
              'port_id' => 0,
5187 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
5188 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
5189 
              'timingConstraint' => 'none',
5190 
              'type' => 'UFix_1_0',
5191 
            },
5192 
            'direction' => 'in',
5193 
            'hdlType' => 'std_logic',
5194 
            'width' => 1,
5195 
          },
5196 
        },
5197 
      },
5198 
      'entityName' => 'reg14_rv',
5199 
    },
5200 
    'reg14_td' => {
5201 
      'connections' => {
5202 
        'reg14_td' => '.reg14_td',
5203 
      },
5204 
      'entity' => {
5205 
        'attributes' => {
5206 
          'entityAlreadyNetlisted' => 1,
5207 
          'isGateway' => 1,
5208 
          'is_floating_block' => 1,
5209 
        },
5210 
        'entityName' => 'reg14_td',
5211 
        'ports' => {
5212 
          'reg14_td' => {
5213 
            'attributes' => {
5214 
              'bin_pt' => 0,
5215 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
5216 
              'is_floating_block' => 1,
5217 
              'is_gateway_port' => 1,
5218 
              'must_be_hdl_vector' => 1,
5219 
              'period' => 1,
5220 
              'port_id' => 0,
5221 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
5222 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
5223 
              'timingConstraint' => 'none',
5224 
              'type' => 'UFix_32_0',
5225 
            },
5226 
            'direction' => 'out',
5227 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5228 
            'width' => 32,
5229 
          },
5230 
        },
5231 
      },
5232 
      'entityName' => 'reg14_td',
5233 
    },
5234 
    'reg14_tv' => {
5235 
      'connections' => {
5236 
        'reg14_tv' => '.reg14_tv',
5237 
      },
5238 
      'entity' => {
5239 
        'attributes' => {
5240 
          'entityAlreadyNetlisted' => 1,
5241 
          'isGateway' => 1,
5242 
          'is_floating_block' => 1,
5243 
        },
5244 
        'entityName' => 'reg14_tv',
5245 
        'ports' => {
5246 
          'reg14_tv' => {
5247 
            'attributes' => {
5248 
              'bin_pt' => 0,
5249 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
5250 
              'is_floating_block' => 1,
5251 
              'is_gateway_port' => 1,
5252 
              'must_be_hdl_vector' => 1,
5253 
              'period' => 1,
5254 
              'port_id' => 0,
5255 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
5256 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
5257 
              'timingConstraint' => 'none',
5258 
              'type' => 'Bool',
5259 
            },
5260 
            'direction' => 'out',
5261 
            'hdlType' => 'std_logic',
5262 
            'width' => 1,
5263 
          },
5264 
        },
5265 
      },
5266 
      'entityName' => 'reg14_tv',
5267 
    },
5268 
    'sysgen_dut' => {
5269 
      'connections' => {
5270 
        'clk' => '.clk',
5271 
        'debug_in_1i' => '.debug_in_1i',
5272 
        'debug_in_2i' => '.debug_in_2i',
5273 
        'debug_in_3i' => '.debug_in_3i',
5274 
        'debug_in_4i' => '.debug_in_4i',
5275 
        'dma_host2board_busy' => '.dma_host2board_busy',
5276 
        'dma_host2board_done' => '.dma_host2board_done',
5277 
        'from_register10_data_out' => 'from_register10.data_out',
5278 
        'from_register11_data_out' => 'from_register11.data_out',
5279 
        'from_register12_data_out' => 'from_register12.data_out',
5280 
        'from_register13_data_out' => 'from_register13.data_out',
5281 
        'from_register14_data_out' => 'from_register14.data_out',
5282 
        'from_register15_data_out' => 'from_register15.data_out',
5283 
        'from_register16_data_out' => 'from_register16.data_out',
5284 
        'from_register17_data_out' => 'from_register17.data_out',
5285 
        'from_register18_data_out' => 'from_register18.data_out',
5286 
        'from_register19_data_out' => 'from_register19.data_out',
5287 
        'from_register1_data_out' => 'from_register1.data_out',
5288 
        'from_register20_data_out' => 'from_register20.data_out',
5289 
        'from_register21_data_out' => 'from_register21.data_out',
5290 
        'from_register22_data_out' => 'from_register22.data_out',
5291 
        'from_register23_data_out' => 'from_register23.data_out',
5292 
        'from_register24_data_out' => 'from_register24.data_out',
5293 
        'from_register25_data_out' => 'from_register25.data_out',
5294 
        'from_register26_data_out' => 'from_register26.data_out',
5295 
        'from_register27_data_out' => 'from_register27.data_out',
5296 
        'from_register28_data_out' => 'from_register28.data_out',
5297 
        'from_register2_data_out' => 'from_register2.data_out',
5298 
        'from_register3_data_out' => 'from_register3.data_out',
5299 
        'from_register4_data_out' => 'from_register4.data_out',
5300 
        'from_register5_data_out' => 'from_register5.data_out',
5301 
        'from_register6_data_out' => 'from_register6.data_out',
5302 
        'from_register7_data_out' => 'from_register7.data_out',
5303 
        'from_register8_data_out' => 'from_register8.data_out',
5304 
        'from_register9_data_out' => 'from_register9.data_out',
5305 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
5306 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
5307 
        'reg01_td' => '.reg01_td',
5308 
        'reg01_tv' => '.reg01_tv',
5309 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
5310 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
5311 
        'reg02_td' => '.reg02_td',
5312 
        'reg02_tv' => '.reg02_tv',
5313 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
5314 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
5315 
        'reg03_td' => '.reg03_td',
5316 
        'reg03_tv' => '.reg03_tv',
5317 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
5318 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
5319 
        'reg04_td' => '.reg04_td',
5320 
        'reg04_tv' => '.reg04_tv',
5321 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
5322 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
5323 
        'reg05_td' => '.reg05_td',
5324 
        'reg05_tv' => '.reg05_tv',
5325 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
5326 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
5327 
        'reg06_td' => '.reg06_td',
5328 
        'reg06_tv' => '.reg06_tv',
5329 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
5330 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
5331 
        'reg07_td' => '.reg07_td',
5332 
        'reg07_tv' => '.reg07_tv',
5333 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
5334 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
5335 
        'reg08_td' => '.reg08_td',
5336 
        'reg08_tv' => '.reg08_tv',
5337 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
5338 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
5339 
        'reg09_td' => '.reg09_td',
5340 
        'reg09_tv' => '.reg09_tv',
5341 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
5342 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
5343 
        'reg10_td' => '.reg10_td',
5344 
        'reg10_tv' => '.reg10_tv',
5345 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
5346 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
5347 
        'reg11_td' => '.reg11_td',
5348 
        'reg11_tv' => '.reg11_tv',
5349 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
5350 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
5351 
        'reg12_td' => '.reg12_td',
5352 
        'reg12_tv' => '.reg12_tv',
5353 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
5354 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
5355 
        'reg13_td' => '.reg13_td',
5356 
        'reg13_tv' => '.reg13_tv',
5357 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5358 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5359 
        'reg14_td' => '.reg14_td',
5360 
        'reg14_tv' => '.reg14_tv',
5361 
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
5362 
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
5363 
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
5364 
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
5365 
        'to_register10_dout' => 'to_register10.dout',
5366 
        'to_register10_en' => 'sysgen_dut.to_register10_en',
5367 
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
5368 
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
5369 
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
5370 
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
5371 
        'to_register11_dout' => 'to_register11.dout',
5372 
        'to_register11_en' => 'sysgen_dut.to_register11_en',
5373 
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
5374 
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
5375 
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
5376 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
5377 
        'to_register12_dout' => 'to_register12.dout',
5378 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
5379 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
5380 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
5381 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
5382 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
5383 
        'to_register13_dout' => 'to_register13.dout',
5384 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
5385 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
5386 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
5387 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
5388 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
5389 
        'to_register14_dout' => 'to_register14.dout',
5390 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
5391 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
5392 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
5393 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
5394 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
5395 
        'to_register15_dout' => 'to_register15.dout',
5396 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
5397 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
5398 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
5399 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
5400 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
5401 
        'to_register16_dout' => 'to_register16.dout',
5402 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
5403 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
5404 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
5405 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
5406 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
5407 
        'to_register17_dout' => 'to_register17.dout',
5408 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
5409 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
5410 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
5411 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
5412 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
5413 
        'to_register18_dout' => 'to_register18.dout',
5414 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
5415 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
5416 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
5417 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
5418 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
5419 
        'to_register19_dout' => 'to_register19.dout',
5420 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
5421 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
5422 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
5423 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
5424 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
5425 
        'to_register1_dout' => 'to_register1.dout',
5426 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
5427 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
5428 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
5429 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
5430 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
5431 
        'to_register20_dout' => 'to_register20.dout',
5432 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
5433 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
5434 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
5435 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
5436 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
5437 
        'to_register21_dout' => 'to_register21.dout',
5438 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
5439 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
5440 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
5441 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
5442 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
5443 
        'to_register22_dout' => 'to_register22.dout',
5444 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
5445 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
5446 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
5447 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
5448 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
5449 
        'to_register23_dout' => 'to_register23.dout',
5450 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
5451 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
5452 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
5453 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
5454 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
5455 
        'to_register24_dout' => 'to_register24.dout',
5456 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
5457 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
5458 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
5459 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
5460 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
5461 
        'to_register25_dout' => 'to_register25.dout',
5462 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
5463 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
5464 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
5465 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
5466 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
5467 
        'to_register26_dout' => 'to_register26.dout',
5468 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
5469 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
5470 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
5471 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
5472 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
5473 
        'to_register27_dout' => 'to_register27.dout',
5474 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
5475 
        'to_register28_ce' => 'sysgen_dut.to_register28_ce',
5476 
        'to_register28_clk' => 'sysgen_dut.to_register28_clk',
5477 
        'to_register28_clr' => 'sysgen_dut.to_register28_clr',
5478 
        'to_register28_data_in' => 'sysgen_dut.to_register28_data_in',
5479 
        'to_register28_dout' => 'to_register28.dout',
5480 
        'to_register28_en' => 'sysgen_dut.to_register28_en',
5481 
        'to_register29_ce' => 'sysgen_dut.to_register29_ce',
5482 
        'to_register29_clk' => 'sysgen_dut.to_register29_clk',
5483 
        'to_register29_clr' => 'sysgen_dut.to_register29_clr',
5484 
        'to_register29_data_in' => 'sysgen_dut.to_register29_data_in',
5485 
        'to_register29_dout' => 'to_register29.dout',
5486 
        'to_register29_en' => 'sysgen_dut.to_register29_en',
5487 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
5488 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
5489 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
5490 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
5491 
        'to_register2_dout' => 'to_register2.dout',
5492 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
5493 
        'to_register30_ce' => 'sysgen_dut.to_register30_ce',
5494 
        'to_register30_clk' => 'sysgen_dut.to_register30_clk',
5495 
        'to_register30_clr' => 'sysgen_dut.to_register30_clr',
5496 
        'to_register30_data_in' => 'sysgen_dut.to_register30_data_in',
5497 
        'to_register30_dout' => 'to_register30.dout',
5498 
        'to_register30_en' => 'sysgen_dut.to_register30_en',
5499 
        'to_register31_ce' => 'sysgen_dut.to_register31_ce',
5500 
        'to_register31_clk' => 'sysgen_dut.to_register31_clk',
5501 
        'to_register31_clr' => 'sysgen_dut.to_register31_clr',
5502 
        'to_register31_data_in' => 'sysgen_dut.to_register31_data_in',
5503 
        'to_register31_dout' => 'to_register31.dout',
5504 
        'to_register31_en' => 'sysgen_dut.to_register31_en',
5505 
        'to_register32_ce' => 'sysgen_dut.to_register32_ce',
5506 
        'to_register32_clk' => 'sysgen_dut.to_register32_clk',
5507 
        'to_register32_clr' => 'sysgen_dut.to_register32_clr',
5508 
        'to_register32_data_in' => 'sysgen_dut.to_register32_data_in',
5509 
        'to_register32_dout' => 'to_register32.dout',
5510 
        'to_register32_en' => 'sysgen_dut.to_register32_en',
5511 
        'to_register33_ce' => 'sysgen_dut.to_register33_ce',
5512 
        'to_register33_clk' => 'sysgen_dut.to_register33_clk',
5513 
        'to_register33_clr' => 'sysgen_dut.to_register33_clr',
5514 
        'to_register33_data_in' => 'sysgen_dut.to_register33_data_in',
5515 
        'to_register33_dout' => 'to_register33.dout',
5516 
        'to_register33_en' => 'sysgen_dut.to_register33_en',
5517 
        'to_register34_ce' => 'sysgen_dut.to_register34_ce',
5518 
        'to_register34_clk' => 'sysgen_dut.to_register34_clk',
5519 
        'to_register34_clr' => 'sysgen_dut.to_register34_clr',
5520 
        'to_register34_data_in' => 'sysgen_dut.to_register34_data_in',
5521 
        'to_register34_dout' => 'to_register34.dout',
5522 
        'to_register34_en' => 'sysgen_dut.to_register34_en',
5523 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
5524 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
5525 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
5526 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
5527 
        'to_register3_dout' => 'to_register3.dout',
5528 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
5529 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
5530 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
5531 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
5532 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
5533 
        'to_register4_dout' => 'to_register4.dout',
5534 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
5535 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
5536 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
5537 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
5538 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
5539 
        'to_register5_dout' => 'to_register5.dout',
5540 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
5541 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
5542 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
5543 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
5544 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
5545 
        'to_register6_dout' => 'to_register6.dout',
5546 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
5547 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
5548 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
5549 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
5550 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
5551 
        'to_register7_dout' => 'to_register7.dout',
5552 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
5553 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
5554 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
5555 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
5556 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
5557 
        'to_register8_dout' => 'to_register8.dout',
5558 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
5559 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
5560 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
5561 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
5562 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
5563 
        'to_register9_dout' => 'to_register9.dout',
5564 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
5565 
      },
5566 
      'entity' => {
5567 
        'attributes' => {
5568 
          'entityAlreadyNetlisted' => 1,
5569 
          'hdlArchAttributes' => [
5570 
          ],
5571 
          'hdlEntityAttributes' => [
5572 
          ],
5573 
          'isClkWrapper' => 1,
5574 
        },
5575 
        'connections' => {
5576 
          'clk' => 'clkNet',
5577 
          'debug_in_1i' => 'debug_in_1i_net',
5578 
          'debug_in_2i' => 'debug_in_2i_net',
5579 
          'debug_in_3i' => 'debug_in_3i_net',
5580 
          'debug_in_4i' => 'debug_in_4i_net',
5581 
          'dma_host2board_busy' => 'dma_host2board_busy_net',
5582 
          'dma_host2board_done' => 'dma_host2board_done_net',
5583 
          'from_register10_data_out' => 'from_register10_data_out_net',
5584 
          'from_register11_data_out' => 'from_register11_data_out_net',
5585 
          'from_register12_data_out' => 'from_register12_data_out_net',
5586 
          'from_register13_data_out' => 'from_register13_data_out_net',
5587 
          'from_register14_data_out' => 'from_register14_data_out_net',
5588 
          'from_register15_data_out' => 'from_register15_data_out_net',
5589 
          'from_register16_data_out' => 'from_register16_data_out_net',
5590 
          'from_register17_data_out' => 'from_register17_data_out_net',
5591 
          'from_register18_data_out' => 'from_register18_data_out_net',
5592 
          'from_register19_data_out' => 'from_register19_data_out_net',
5593 
          'from_register1_data_out' => 'from_register1_data_out_net',
5594 
          'from_register20_data_out' => 'from_register20_data_out_net',
5595 
          'from_register21_data_out' => 'from_register21_data_out_net',
5596 
          'from_register22_data_out' => 'from_register22_data_out_net',
5597 
          'from_register23_data_out' => 'from_register23_data_out_net',
5598 
          'from_register24_data_out' => 'from_register24_data_out_net',
5599 
          'from_register25_data_out' => 'from_register25_data_out_net',
5600 
          'from_register26_data_out' => 'from_register26_data_out_net',
5601 
          'from_register27_data_out' => 'from_register27_data_out_net',
5602 
          'from_register28_data_out' => 'from_register28_data_out_net',
5603 
          'from_register2_data_out' => 'from_register2_data_out_net',
5604 
          'from_register3_data_out' => 'from_register3_data_out_net',
5605 
          'from_register4_data_out' => 'from_register4_data_out_net',
5606 
          'from_register5_data_out' => 'from_register5_data_out_net',
5607 
          'from_register6_data_out' => 'from_register6_data_out_net',
5608 
          'from_register7_data_out' => 'from_register7_data_out_net',
5609 
          'from_register8_data_out' => 'from_register8_data_out_net',
5610 
          'from_register9_data_out' => 'from_register9_data_out_net',
5611 
          'reg01_rd' => 'from_register3_data_out_net_x0',
5612 
          'reg01_rv' => 'from_register1_data_out_net_x0',
5613 
          'reg01_td' => 'reg01_td_net',
5614 
          'reg01_tv' => 'reg01_tv_net',
5615 
          'reg02_rd' => 'from_register5_data_out_net_x0',
5616 
          'reg02_rv' => 'from_register2_data_out_net_x0',
5617 
          'reg02_td' => 'reg02_td_net',
5618 
          'reg02_tv' => 'reg02_tv_net',
5619 
          'reg03_rd' => 'from_register7_data_out_net_x0',
5620 
          'reg03_rv' => 'from_register6_data_out_net_x0',
5621 
          'reg03_td' => 'reg03_td_net',
5622 
          'reg03_tv' => 'reg03_tv_net',
5623 
          'reg04_rd' => 'from_register8_data_out_net_x0',
5624 
          'reg04_rv' => 'from_register4_data_out_net_x0',
5625 
          'reg04_td' => 'reg04_td_net',
5626 
          'reg04_tv' => 'reg04_tv_net',
5627 
          'reg05_rd' => 'from_register10_data_out_net_x0',
5628 
          'reg05_rv' => 'from_register9_data_out_net_x0',
5629 
          'reg05_td' => 'reg05_td_net',
5630 
          'reg05_tv' => 'reg05_tv_net',
5631 
          'reg06_rd' => 'from_register11_data_out_net_x0',
5632 
          'reg06_rv' => 'from_register12_data_out_net_x0',
5633 
          'reg06_td' => 'reg06_td_net',
5634 
          'reg06_tv' => 'reg06_tv_net',
5635 
          'reg07_rd' => 'from_register13_data_out_net_x0',
5636 
          'reg07_rv' => 'from_register14_data_out_net_x0',
5637 
          'reg07_td' => 'reg07_td_net',
5638 
          'reg07_tv' => 'reg07_tv_net',
5639 
          'reg08_rd' => 'from_register15_data_out_net_x0',
5640 
          'reg08_rv' => 'from_register16_data_out_net_x0',
5641 
          'reg08_td' => 'reg08_td_net',
5642 
          'reg08_tv' => 'reg08_tv_net',
5643 
          'reg09_rd' => 'from_register17_data_out_net_x0',
5644 
          'reg09_rv' => 'from_register18_data_out_net_x0',
5645 
          'reg09_td' => 'reg09_td_net',
5646 
          'reg09_tv' => 'reg09_tv_net',
5647 
          'reg10_rd' => 'from_register19_data_out_net_x0',
5648 
          'reg10_rv' => 'from_register20_data_out_net_x0',
5649 
          'reg10_td' => 'reg10_td_net',
5650 
          'reg10_tv' => 'reg10_tv_net',
5651 
          'reg11_rd' => 'from_register21_data_out_net_x0',
5652 
          'reg11_rv' => 'from_register22_data_out_net_x0',
5653 
          'reg11_td' => 'reg11_td_net',
5654 
          'reg11_tv' => 'reg11_tv_net',
5655 
          'reg12_rd' => 'from_register23_data_out_net_x0',
5656 
          'reg12_rv' => 'from_register24_data_out_net_x0',
5657 
          'reg12_td' => 'reg12_td_net',
5658 
          'reg12_tv' => 'reg12_tv_net',
5659 
          'reg13_rd' => 'from_register25_data_out_net_x0',
5660 
          'reg13_rv' => 'from_register26_data_out_net_x0',
5661 
          'reg13_td' => 'reg13_td_net',
5662 
          'reg13_tv' => 'reg13_tv_net',
5663 
          'reg14_rd' => 'from_register27_data_out_net_x0',
5664 
          'reg14_rv' => 'from_register28_data_out_net_x0',
5665 
          'reg14_td' => 'reg14_td_net',
5666 
          'reg14_tv' => 'reg14_tv_net',
5667 
          'to_register10_ce' => 'ce_1_sg',
5668 
          'to_register10_clk' => 'clk_1_sg',
5669 
          'to_register10_clr' => [
5670 
            'constant',
5671 
            '\'0\'',
5672 
          ],
5673 
          'to_register10_data_in' => 'reg04_tv_net_x0',
5674 
          'to_register10_dout' => 'to_register10_dout_net',
5675 
          'to_register10_en' => 'constant5_op_net_x1',
5676 
          'to_register11_ce' => 'ce_1_sg',
5677 
          'to_register11_clk' => 'clk_1_sg',
5678 
          'to_register11_clr' => [
5679 
            'constant',
5680 
            '\'0\'',
5681 
          ],
5682 
          'to_register11_data_in' => 'reg04_td_net_x0',
5683 
          'to_register11_dout' => 'to_register11_dout_net',
5684 
          'to_register11_en' => 'constant5_op_net_x2',
5685 
          'to_register12_ce' => 'ce_1_sg',
5686 
          'to_register12_clk' => 'clk_1_sg',
5687 
          'to_register12_clr' => [
5688 
            'constant',
5689 
            '\'0\'',
5690 
          ],
5691 
          'to_register12_data_in' => 'reg05_tv_net_x0',
5692 
          'to_register12_dout' => 'to_register12_dout_net',
5693 
          'to_register12_en' => 'constant5_op_net_x3',
5694 
          'to_register13_ce' => 'ce_1_sg',
5695 
          'to_register13_clk' => 'clk_1_sg',
5696 
          'to_register13_clr' => [
5697 
            'constant',
5698 
            '\'0\'',
5699 
          ],
5700 
          'to_register13_data_in' => 'reg05_td_net_x0',
5701 
          'to_register13_dout' => 'to_register13_dout_net',
5702 
          'to_register13_en' => 'constant5_op_net_x4',
5703 
          'to_register14_ce' => 'ce_1_sg',
5704 
          'to_register14_clk' => 'clk_1_sg',
5705 
          'to_register14_clr' => [
5706 
            'constant',
5707 
            '\'0\'',
5708 
          ],
5709 
          'to_register14_data_in' => 'reg06_tv_net_x0',
5710 
          'to_register14_dout' => 'to_register14_dout_net',
5711 
          'to_register14_en' => 'constant5_op_net_x5',
5712 
          'to_register15_ce' => 'ce_1_sg',
5713 
          'to_register15_clk' => 'clk_1_sg',
5714 
          'to_register15_clr' => [
5715 
            'constant',
5716 
            '\'0\'',
5717 
          ],
5718 
          'to_register15_data_in' => 'reg06_td_net_x0',
5719 
          'to_register15_dout' => 'to_register15_dout_net',
5720 
          'to_register15_en' => 'constant5_op_net_x6',
5721 
          'to_register16_ce' => 'ce_1_sg',
5722 
          'to_register16_clk' => 'clk_1_sg',
5723 
          'to_register16_clr' => [
5724 
            'constant',
5725 
            '\'0\'',
5726 
          ],
5727 
          'to_register16_data_in' => 'reg07_tv_net_x0',
5728 
          'to_register16_dout' => 'to_register16_dout_net',
5729 
          'to_register16_en' => 'constant5_op_net_x7',
5730 
          'to_register17_ce' => 'ce_1_sg',
5731 
          'to_register17_clk' => 'clk_1_sg',
5732 
          'to_register17_clr' => [
5733 
            'constant',
5734 
            '\'0\'',
5735 
          ],
5736 
          'to_register17_data_in' => 'reg07_td_net_x0',
5737 
          'to_register17_dout' => 'to_register17_dout_net',
5738 
          'to_register17_en' => 'constant5_op_net_x8',
5739 
          'to_register18_ce' => 'ce_1_sg',
5740 
          'to_register18_clk' => 'clk_1_sg',
5741 
          'to_register18_clr' => [
5742 
            'constant',
5743 
            '\'0\'',
5744 
          ],
5745 
          'to_register18_data_in' => 'dma_host2board_busy_net_x0',
5746 
          'to_register18_dout' => 'to_register18_dout_net',
5747 
          'to_register18_en' => 'constant5_op_net_x9',
5748 
          'to_register19_ce' => 'ce_1_sg',
5749 
          'to_register19_clk' => 'clk_1_sg',
5750 
          'to_register19_clr' => [
5751 
            'constant',
5752 
            '\'0\'',
5753 
          ],
5754 
          'to_register19_data_in' => 'dma_host2board_done_net_x0',
5755 
          'to_register19_dout' => 'to_register19_dout_net',
5756 
          'to_register19_en' => 'constant5_op_net_x10',
5757 
          'to_register1_ce' => 'ce_1_sg',
5758 
          'to_register1_clk' => 'clk_1_sg',
5759 
          'to_register1_clr' => [
5760 
            'constant',
5761 
            '\'0\'',
5762 
          ],
5763 
          'to_register1_data_in' => 'debug_in_2i_net_x0',
5764 
          'to_register1_dout' => 'to_register1_dout_net',
5765 
          'to_register1_en' => 'constant5_op_net_x0',
5766 
          'to_register20_ce' => 'ce_1_sg',
5767 
          'to_register20_clk' => 'clk_1_sg',
5768 
          'to_register20_clr' => [
5769 
            'constant',
5770 
            '\'0\'',
5771 
          ],
5772 
          'to_register20_data_in' => 'debug_in_4i_net_x0',
5773 
          'to_register20_dout' => 'to_register20_dout_net',
5774 
          'to_register20_en' => 'constant5_op_net_x12',
5775 
          'to_register21_ce' => 'ce_1_sg',
5776 
          'to_register21_clk' => 'clk_1_sg',
5777 
          'to_register21_clr' => [
5778 
            'constant',
5779 
            '\'0\'',
5780 
          ],
5781 
          'to_register21_data_in' => 'reg09_tv_net_x0',
5782 
          'to_register21_dout' => 'to_register21_dout_net',
5783 
          'to_register21_en' => 'constant1_op_net_x0',
5784 
          'to_register22_ce' => 'ce_1_sg',
5785 
          'to_register22_clk' => 'clk_1_sg',
5786 
          'to_register22_clr' => [
5787 
            'constant',
5788 
            '\'0\'',
5789 
          ],
5790 
          'to_register22_data_in' => 'reg09_td_net_x0',
5791 
          'to_register22_dout' => 'to_register22_dout_net',
5792 
          'to_register22_en' => 'constant1_op_net_x1',
5793 
          'to_register23_ce' => 'ce_1_sg',
5794 
          'to_register23_clk' => 'clk_1_sg',
5795 
          'to_register23_clr' => [
5796 
            'constant',
5797 
            '\'0\'',
5798 
          ],
5799 
          'to_register23_data_in' => 'reg10_tv_net_x0',
5800 
          'to_register23_dout' => 'to_register23_dout_net',
5801 
          'to_register23_en' => 'constant1_op_net_x2',
5802 
          'to_register24_ce' => 'ce_1_sg',
5803 
          'to_register24_clk' => 'clk_1_sg',
5804 
          'to_register24_clr' => [
5805 
            'constant',
5806 
            '\'0\'',
5807 
          ],
5808 
          'to_register24_data_in' => 'reg10_td_net_x0',
5809 
          'to_register24_dout' => 'to_register24_dout_net',
5810 
          'to_register24_en' => 'constant1_op_net_x3',
5811 
          'to_register25_ce' => 'ce_1_sg',
5812 
          'to_register25_clk' => 'clk_1_sg',
5813 
          'to_register25_clr' => [
5814 
            'constant',
5815 
            '\'0\'',
5816 
          ],
5817 
          'to_register25_data_in' => 'reg08_tv_net_x0',
5818 
          'to_register25_dout' => 'to_register25_dout_net',
5819 
          'to_register25_en' => 'constant1_op_net_x4',
5820 
          'to_register26_ce' => 'ce_1_sg',
5821 
          'to_register26_clk' => 'clk_1_sg',
5822 
          'to_register26_clr' => [
5823 
            'constant',
5824 
            '\'0\'',
5825 
          ],
5826 
          'to_register26_data_in' => 'reg08_td_net_x0',
5827 
          'to_register26_dout' => 'to_register26_dout_net',
5828 
          'to_register26_en' => 'constant1_op_net_x5',
5829 
          'to_register27_ce' => 'ce_1_sg',
5830 
          'to_register27_clk' => 'clk_1_sg',
5831 
          'to_register27_clr' => [
5832 
            'constant',
5833 
            '\'0\'',
5834 
          ],
5835 
          'to_register27_data_in' => 'reg11_tv_net_x0',
5836 
          'to_register27_dout' => 'to_register27_dout_net',
5837 
          'to_register27_en' => 'constant1_op_net_x6',
5838 
          'to_register28_ce' => 'ce_1_sg',
5839 
          'to_register28_clk' => 'clk_1_sg',
5840 
          'to_register28_clr' => [
5841 
            'constant',
5842 
            '\'0\'',
5843 
          ],
5844 
          'to_register28_data_in' => 'reg11_td_net_x0',
5845 
          'to_register28_dout' => 'to_register28_dout_net',
5846 
          'to_register28_en' => 'constant1_op_net_x7',
5847 
          'to_register29_ce' => 'ce_1_sg',
5848 
          'to_register29_clk' => 'clk_1_sg',
5849 
          'to_register29_clr' => [
5850 
            'constant',
5851 
            '\'0\'',
5852 
          ],
5853 
          'to_register29_data_in' => 'reg12_tv_net_x0',
5854 
          'to_register29_dout' => 'to_register29_dout_net',
5855 
          'to_register29_en' => 'constant1_op_net_x8',
5856 
          'to_register2_ce' => 'ce_1_sg',
5857 
          'to_register2_clk' => 'clk_1_sg',
5858 
          'to_register2_clr' => [
5859 
            'constant',
5860 
            '\'0\'',
5861 
          ],
5862 
          'to_register2_data_in' => 'debug_in_3i_net_x0',
5863 
          'to_register2_dout' => 'to_register2_dout_net',
5864 
          'to_register2_en' => 'constant5_op_net_x11',
5865 
          'to_register30_ce' => 'ce_1_sg',
5866 
          'to_register30_clk' => 'clk_1_sg',
5867 
          'to_register30_clr' => [
5868 
            'constant',
5869 
            '\'0\'',
5870 
          ],
5871 
          'to_register30_data_in' => 'reg12_td_net_x0',
5872 
          'to_register30_dout' => 'to_register30_dout_net',
5873 
          'to_register30_en' => 'constant1_op_net_x9',
5874 
          'to_register31_ce' => 'ce_1_sg',
5875 
          'to_register31_clk' => 'clk_1_sg',
5876 
          'to_register31_clr' => [
5877 
            'constant',
5878 
            '\'0\'',
5879 
          ],
5880 
          'to_register31_data_in' => 'reg13_tv_net_x0',
5881 
          'to_register31_dout' => 'to_register31_dout_net',
5882 
          'to_register31_en' => 'constant1_op_net_x10',
5883 
          'to_register32_ce' => 'ce_1_sg',
5884 
          'to_register32_clk' => 'clk_1_sg',
5885 
          'to_register32_clr' => [
5886 
            'constant',
5887 
            '\'0\'',
5888 
          ],
5889 
          'to_register32_data_in' => 'reg13_td_net_x0',
5890 
          'to_register32_dout' => 'to_register32_dout_net',
5891 
          'to_register32_en' => 'constant1_op_net_x11',
5892 
          'to_register33_ce' => 'ce_1_sg',
5893 
          'to_register33_clk' => 'clk_1_sg',
5894 
          'to_register33_clr' => [
5895 
            'constant',
5896 
            '\'0\'',
5897 
          ],
5898 
          'to_register33_data_in' => 'reg14_tv_net_x0',
5899 
          'to_register33_dout' => 'to_register33_dout_net',
5900 
          'to_register33_en' => 'constant1_op_net_x12',
5901 
          'to_register34_ce' => 'ce_1_sg',
5902 
          'to_register34_clk' => 'clk_1_sg',
5903 
          'to_register34_clr' => [
5904 
            'constant',
5905 
            '\'0\'',
5906 
          ],
5907 
          'to_register34_data_in' => 'reg14_td_net_x0',
5908 
          'to_register34_dout' => 'to_register34_dout_net',
5909 
          'to_register34_en' => 'constant1_op_net_x13',
5910 
          'to_register3_ce' => 'ce_1_sg',
5911 
          'to_register3_clk' => 'clk_1_sg',
5912 
          'to_register3_clr' => [
5913 
            'constant',
5914 
            '\'0\'',
5915 
          ],
5916 
          'to_register3_data_in' => 'reg01_tv_net_x0',
5917 
          'to_register3_dout' => 'to_register3_dout_net',
5918 
          'to_register3_en' => 'constant5_op_net_x13',
5919 
          'to_register4_ce' => 'ce_1_sg',
5920 
          'to_register4_clk' => 'clk_1_sg',
5921 
          'to_register4_clr' => [
5922 
            'constant',
5923 
            '\'0\'',
5924 
          ],
5925 
          'to_register4_data_in' => 'reg02_tv_net_x0',
5926 
          'to_register4_dout' => 'to_register4_dout_net',
5927 
          'to_register4_en' => 'constant5_op_net_x14',
5928 
          'to_register5_ce' => 'ce_1_sg',
5929 
          'to_register5_clk' => 'clk_1_sg',
5930 
          'to_register5_clr' => [
5931 
            'constant',
5932 
            '\'0\'',
5933 
          ],
5934 
          'to_register5_data_in' => 'reg02_td_net_x0',
5935 
          'to_register5_dout' => 'to_register5_dout_net',
5936 
          'to_register5_en' => 'constant5_op_net_x15',
5937 
          'to_register6_ce' => 'ce_1_sg',
5938 
          'to_register6_clk' => 'clk_1_sg',
5939 
          'to_register6_clr' => [
5940 
            'constant',
5941 
            '\'0\'',
5942 
          ],
5943 
          'to_register6_data_in' => 'debug_in_1i_net_x0',
5944 
          'to_register6_dout' => 'to_register6_dout_net',
5945 
          'to_register6_en' => 'constant5_op_net_x16',
5946 
          'to_register7_ce' => 'ce_1_sg',
5947 
          'to_register7_clk' => 'clk_1_sg',
5948 
          'to_register7_clr' => [
5949 
            'constant',
5950 
            '\'0\'',
5951 
          ],
5952 
          'to_register7_data_in' => 'reg01_td_net_x0',
5953 
          'to_register7_dout' => 'to_register7_dout_net',
5954 
          'to_register7_en' => 'constant5_op_net_x17',
5955 
          'to_register8_ce' => 'ce_1_sg',
5956 
          'to_register8_clk' => 'clk_1_sg',
5957 
          'to_register8_clr' => [
5958 
            'constant',
5959 
            '\'0\'',
5960 
          ],
5961 
          'to_register8_data_in' => 'reg03_tv_net_x0',
5962 
          'to_register8_dout' => 'to_register8_dout_net',
5963 
          'to_register8_en' => 'constant5_op_net_x18',
5964 
          'to_register9_ce' => 'ce_1_sg',
5965 
          'to_register9_clk' => 'clk_1_sg',
5966 
          'to_register9_clr' => [
5967 
            'constant',
5968 
            '\'0\'',
5969 
          ],
5970 
          'to_register9_data_in' => 'reg03_td_net_x0',
5971 
          'to_register9_dout' => 'to_register9_dout_net',
5972 
          'to_register9_en' => 'constant5_op_net_x19',
5973 
        },
5974 
        'entityName' => 'inout_logic_cw',
5975 
        'nets' => {
5976 
          'ce_1_sg' => {
5977 
            'attributes' => {
5978 
              'hdlNetAttributes' => [
5979 
                [
5980 
                  'MAX_FANOUT',
5981 
                  'string',
5982 
                  '"REDUCE"',
5983 
                ],
5984 
              ],
5985 
            },
5986 
            'hdlType' => 'std_logic',
5987 
            'width' => 1,
5988 
          },
5989 
          'clkNet' => {
5990 
            'attributes' => {
5991 
              'hdlNetAttributes' => [
5992 
              ],
5993 
            },
5994 
            'hdlType' => 'std_logic',
5995 
            'width' => 1,
5996 
          },
5997 
          'clk_1_sg' => {
5998 
            'attributes' => {
5999 
              'hdlNetAttributes' => [
6000 
              ],
6001 
            },
6002 
            'hdlType' => 'std_logic',
6003 
            'width' => 1,
6004 
          },
6005 
          'constant1_op_net_x0' => {
6006 
            'attributes' => {
6007 
              'hdlNetAttributes' => [
6008 
              ],
6009 
            },
6010 
            'hdlType' => 'std_logic',
6011 
            'width' => 1,
6012 
          },
6013 
          'constant1_op_net_x1' => {
6014 
            'attributes' => {
6015 
              'hdlNetAttributes' => [
6016 
              ],
6017 
            },
6018 
            'hdlType' => 'std_logic',
6019 
            'width' => 1,
6020 
          },
6021 
          'constant1_op_net_x10' => {
6022 
            'attributes' => {
6023 
              'hdlNetAttributes' => [
6024 
              ],
6025 
            },
6026 
            'hdlType' => 'std_logic',
6027 
            'width' => 1,
6028 
          },
6029 
          'constant1_op_net_x11' => {
6030 
            'attributes' => {
6031 
              'hdlNetAttributes' => [
6032 
              ],
6033 
            },
6034 
            'hdlType' => 'std_logic',
6035 
            'width' => 1,
6036 
          },
6037 
          'constant1_op_net_x12' => {
6038 
            'attributes' => {
6039 
              'hdlNetAttributes' => [
6040 
              ],
6041 
            },
6042 
            'hdlType' => 'std_logic',
6043 
            'width' => 1,
6044 
          },
6045 
          'constant1_op_net_x13' => {
6046 
            'attributes' => {
6047 
              'hdlNetAttributes' => [
6048 
              ],
6049 
            },
6050 
            'hdlType' => 'std_logic',
6051 
            'width' => 1,
6052 
          },
6053 
          'constant1_op_net_x2' => {
6054 
            'attributes' => {
6055 
              'hdlNetAttributes' => [
6056 
              ],
6057 
            },
6058 
            'hdlType' => 'std_logic',
6059 
            'width' => 1,
6060 
          },
6061 
          'constant1_op_net_x3' => {
6062 
            'attributes' => {
6063 
              'hdlNetAttributes' => [
6064 
              ],
6065 
            },
6066 
            'hdlType' => 'std_logic',
6067 
            'width' => 1,
6068 
          },
6069 
          'constant1_op_net_x4' => {
6070 
            'attributes' => {
6071 
              'hdlNetAttributes' => [
6072 
              ],
6073 
            },
6074 
            'hdlType' => 'std_logic',
6075 
            'width' => 1,
6076 
          },
6077 
          'constant1_op_net_x5' => {
6078 
            'attributes' => {
6079 
              'hdlNetAttributes' => [
6080 
              ],
6081 
            },
6082 
            'hdlType' => 'std_logic',
6083 
            'width' => 1,
6084 
          },
6085 
          'constant1_op_net_x6' => {
6086 
            'attributes' => {
6087 
              'hdlNetAttributes' => [
6088 
              ],
6089 
            },
6090 
            'hdlType' => 'std_logic',
6091 
            'width' => 1,
6092 
          },
6093 
          'constant1_op_net_x7' => {
6094 
            'attributes' => {
6095 
              'hdlNetAttributes' => [
6096 
              ],
6097 
            },
6098 
            'hdlType' => 'std_logic',
6099 
            'width' => 1,
6100 
          },
6101 
          'constant1_op_net_x8' => {
6102 
            'attributes' => {
6103 
              'hdlNetAttributes' => [
6104 
              ],
6105 
            },
6106 
            'hdlType' => 'std_logic',
6107 
            'width' => 1,
6108 
          },
6109 
          'constant1_op_net_x9' => {
6110 
            'attributes' => {
6111 
              'hdlNetAttributes' => [
6112 
              ],
6113 
            },
6114 
            'hdlType' => 'std_logic',
6115 
            'width' => 1,
6116 
          },
6117 
          'constant5_op_net_x0' => {
6118 
            'attributes' => {
6119 
              'hdlNetAttributes' => [
6120 
              ],
6121 
            },
6122 
            'hdlType' => 'std_logic',
6123 
            'width' => 1,
6124 
          },
6125 
          'constant5_op_net_x1' => {
6126 
            'attributes' => {
6127 
              'hdlNetAttributes' => [
6128 
              ],
6129 
            },
6130 
            'hdlType' => 'std_logic',
6131 
            'width' => 1,
6132 
          },
6133 
          'constant5_op_net_x10' => {
6134 
            'attributes' => {
6135 
              'hdlNetAttributes' => [
6136 
              ],
6137 
            },
6138 
            'hdlType' => 'std_logic',
6139 
            'width' => 1,
6140 
          },
6141 
          'constant5_op_net_x11' => {
6142 
            'attributes' => {
6143 
              'hdlNetAttributes' => [
6144 
              ],
6145 
            },
6146 
            'hdlType' => 'std_logic',
6147 
            'width' => 1,
6148 
          },
6149 
          'constant5_op_net_x12' => {
6150 
            'attributes' => {
6151 
              'hdlNetAttributes' => [
6152 
              ],
6153 
            },
6154 
            'hdlType' => 'std_logic',
6155 
            'width' => 1,
6156 
          },
6157 
          'constant5_op_net_x13' => {
6158 
            'attributes' => {
6159 
              'hdlNetAttributes' => [
6160 
              ],
6161 
            },
6162 
            'hdlType' => 'std_logic',
6163 
            'width' => 1,
6164 
          },
6165 
          'constant5_op_net_x14' => {
6166 
            'attributes' => {
6167 
              'hdlNetAttributes' => [
6168 
              ],
6169 
            },
6170 
            'hdlType' => 'std_logic',
6171 
            'width' => 1,
6172 
          },
6173 
          'constant5_op_net_x15' => {
6174 
            'attributes' => {
6175 
              'hdlNetAttributes' => [
6176 
              ],
6177 
            },
6178 
            'hdlType' => 'std_logic',
6179 
            'width' => 1,
6180 
          },
6181 
          'constant5_op_net_x16' => {
6182 
            'attributes' => {
6183 
              'hdlNetAttributes' => [
6184 
              ],
6185 
            },
6186 
            'hdlType' => 'std_logic',
6187 
            'width' => 1,
6188 
          },
6189 
          'constant5_op_net_x17' => {
6190 
            'attributes' => {
6191 
              'hdlNetAttributes' => [
6192 
              ],
6193 
            },
6194 
            'hdlType' => 'std_logic',
6195 
            'width' => 1,
6196 
          },
6197 
          'constant5_op_net_x18' => {
6198 
            'attributes' => {
6199 
              'hdlNetAttributes' => [
6200 
              ],
6201 
            },
6202 
            'hdlType' => 'std_logic',
6203 
            'width' => 1,
6204 
          },
6205 
          'constant5_op_net_x19' => {
6206 
            'attributes' => {
6207 
              'hdlNetAttributes' => [
6208 
              ],
6209 
            },
6210 
            'hdlType' => 'std_logic',
6211 
            'width' => 1,
6212 
          },
6213 
          'constant5_op_net_x2' => {
6214 
            'attributes' => {
6215 
              'hdlNetAttributes' => [
6216 
              ],
6217 
            },
6218 
            'hdlType' => 'std_logic',
6219 
            'width' => 1,
6220 
          },
6221 
          'constant5_op_net_x3' => {
6222 
            'attributes' => {
6223 
              'hdlNetAttributes' => [
6224 
              ],
6225 
            },
6226 
            'hdlType' => 'std_logic',
6227 
            'width' => 1,
6228 
          },
6229 
          'constant5_op_net_x4' => {
6230 
            'attributes' => {
6231 
              'hdlNetAttributes' => [
6232 
              ],
6233 
            },
6234 
            'hdlType' => 'std_logic',
6235 
            'width' => 1,
6236 
          },
6237 
          'constant5_op_net_x5' => {
6238 
            'attributes' => {
6239 
              'hdlNetAttributes' => [
6240 
              ],
6241 
            },
6242 
            'hdlType' => 'std_logic',
6243 
            'width' => 1,
6244 
          },
6245 
          'constant5_op_net_x6' => {
6246 
            'attributes' => {
6247 
              'hdlNetAttributes' => [
6248 
              ],
6249 
            },
6250 
            'hdlType' => 'std_logic',
6251 
            'width' => 1,
6252 
          },
6253 
          'constant5_op_net_x7' => {
6254 
            'attributes' => {
6255 
              'hdlNetAttributes' => [
6256 
              ],
6257 
            },
6258 
            'hdlType' => 'std_logic',
6259 
            'width' => 1,
6260 
          },
6261 
          'constant5_op_net_x8' => {
6262 
            'attributes' => {
6263 
              'hdlNetAttributes' => [
6264 
              ],
6265 
            },
6266 
            'hdlType' => 'std_logic',
6267 
            'width' => 1,
6268 
          },
6269 
          'constant5_op_net_x9' => {
6270 
            'attributes' => {
6271 
              'hdlNetAttributes' => [
6272 
              ],
6273 
            },
6274 
            'hdlType' => 'std_logic',
6275 
            'width' => 1,
6276 
          },
6277 
          'debug_in_1i_net' => {
6278 
            'attributes' => {
6279 
              'hdlNetAttributes' => [
6280 
              ],
6281 
            },
6282 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6283 
            'width' => 32,
6284 
          },
6285 
          'debug_in_1i_net_x0' => {
6286 
            'attributes' => {
6287 
              'hdlNetAttributes' => [
6288 
              ],
6289 
            },
6290 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6291 
            'width' => 32,
6292 
          },
6293 
          'debug_in_2i_net' => {
6294 
            'attributes' => {
6295 
              'hdlNetAttributes' => [
6296 
              ],
6297 
            },
6298 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6299 
            'width' => 32,
6300 
          },
6301 
          'debug_in_2i_net_x0' => {
6302 
            'attributes' => {
6303 
              'hdlNetAttributes' => [
6304 
              ],
6305 
            },
6306 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6307 
            'width' => 32,
6308 
          },
6309 
          'debug_in_3i_net' => {
6310 
            'attributes' => {
6311 
              'hdlNetAttributes' => [
6312 
              ],
6313 
            },
6314 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6315 
            'width' => 32,
6316 
          },
6317 
          'debug_in_3i_net_x0' => {
6318 
            'attributes' => {
6319 
              'hdlNetAttributes' => [
6320 
              ],
6321 
            },
6322 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6323 
            'width' => 32,
6324 
          },
6325 
          'debug_in_4i_net' => {
6326 
            'attributes' => {
6327 
              'hdlNetAttributes' => [
6328 
              ],
6329 
            },
6330 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6331 
            'width' => 32,
6332 
          },
6333 
          'debug_in_4i_net_x0' => {
6334 
            'attributes' => {
6335 
              'hdlNetAttributes' => [
6336 
              ],
6337 
            },
6338 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6339 
            'width' => 32,
6340 
          },
6341 
          'dma_host2board_busy_net' => {
6342 
            'attributes' => {
6343 
              'hdlNetAttributes' => [
6344 
              ],
6345 
            },
6346 
            'hdlType' => 'std_logic',
6347 
            'width' => 1,
6348 
          },
6349 
          'dma_host2board_busy_net_x0' => {
6350 
            'attributes' => {
6351 
              'hdlNetAttributes' => [
6352 
              ],
6353 
            },
6354 
            'hdlType' => 'std_logic',
6355 
            'width' => 1,
6356 
          },
6357 
          'dma_host2board_done_net' => {
6358 
            'attributes' => {
6359 
              'hdlNetAttributes' => [
6360 
              ],
6361 
            },
6362 
            'hdlType' => 'std_logic',
6363 
            'width' => 1,
6364 
          },
6365 
          'dma_host2board_done_net_x0' => {
6366 
            'attributes' => {
6367 
              'hdlNetAttributes' => [
6368 
              ],
6369 
            },
6370 
            'hdlType' => 'std_logic',
6371 
            'width' => 1,
6372 
          },
6373 
          'from_register10_data_out_net' => {
6374 
            'attributes' => {
6375 
              'hdlNetAttributes' => [
6376 
              ],
6377 
            },
6378 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6379 
            'width' => 32,
6380 
          },
6381 
          'from_register10_data_out_net_x0' => {
6382 
            'attributes' => {
6383 
              'hdlNetAttributes' => [
6384 
              ],
6385 
            },
6386 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6387 
            'width' => 32,
6388 
          },
6389 
          'from_register11_data_out_net' => {
6390 
            'attributes' => {
6391 
              'hdlNetAttributes' => [
6392 
              ],
6393 
            },
6394 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6395 
            'width' => 32,
6396 
          },
6397 
          'from_register11_data_out_net_x0' => {
6398 
            'attributes' => {
6399 
              'hdlNetAttributes' => [
6400 
              ],
6401 
            },
6402 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6403 
            'width' => 32,
6404 
          },
6405 
          'from_register12_data_out_net' => {
6406 
            'attributes' => {
6407 
              'hdlNetAttributes' => [
6408 
              ],
6409 
            },
6410 
            'hdlType' => 'std_logic',
6411 
            'width' => 1,
6412 
          },
6413 
          'from_register12_data_out_net_x0' => {
6414 
            'attributes' => {
6415 
              'hdlNetAttributes' => [
6416 
              ],
6417 
            },
6418 
            'hdlType' => 'std_logic',
6419 
            'width' => 1,
6420 
          },
6421 
          'from_register13_data_out_net' => {
6422 
            'attributes' => {
6423 
              'hdlNetAttributes' => [
6424 
              ],
6425 
            },
6426 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6427 
            'width' => 32,
6428 
          },
6429 
          'from_register13_data_out_net_x0' => {
6430 
            'attributes' => {
6431 
              'hdlNetAttributes' => [
6432 
              ],
6433 
            },
6434 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6435 
            'width' => 32,
6436 
          },
6437 
          'from_register14_data_out_net' => {
6438 
            'attributes' => {
6439 
              'hdlNetAttributes' => [
6440 
              ],
6441 
            },
6442 
            'hdlType' => 'std_logic',
6443 
            'width' => 1,
6444 
          },
6445 
          'from_register14_data_out_net_x0' => {
6446 
            'attributes' => {
6447 
              'hdlNetAttributes' => [
6448 
              ],
6449 
            },
6450 
            'hdlType' => 'std_logic',
6451 
            'width' => 1,
6452 
          },
6453 
          'from_register15_data_out_net' => {
6454 
            'attributes' => {
6455 
              'hdlNetAttributes' => [
6456 
              ],
6457 
            },
6458 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6459 
            'width' => 32,
6460 
          },
6461 
          'from_register15_data_out_net_x0' => {
6462 
            'attributes' => {
6463 
              'hdlNetAttributes' => [
6464 
              ],
6465 
            },
6466 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6467 
            'width' => 32,
6468 
          },
6469 
          'from_register16_data_out_net' => {
6470 
            'attributes' => {
6471 
              'hdlNetAttributes' => [
6472 
              ],
6473 
            },
6474 
            'hdlType' => 'std_logic',
6475 
            'width' => 1,
6476 
          },
6477 
          'from_register16_data_out_net_x0' => {
6478 
            'attributes' => {
6479 
              'hdlNetAttributes' => [
6480 
              ],
6481 
            },
6482 
            'hdlType' => 'std_logic',
6483 
            'width' => 1,
6484 
          },
6485 
          'from_register17_data_out_net' => {
6486 
            'attributes' => {
6487 
              'hdlNetAttributes' => [
6488 
              ],
6489 
            },
6490 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6491 
            'width' => 32,
6492 
          },
6493 
          'from_register17_data_out_net_x0' => {
6494 
            'attributes' => {
6495 
              'hdlNetAttributes' => [
6496 
              ],
6497 
            },
6498 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6499 
            'width' => 32,
6500 
          },
6501 
          'from_register18_data_out_net' => {
6502 
            'attributes' => {
6503 
              'hdlNetAttributes' => [
6504 
              ],
6505 
            },
6506 
            'hdlType' => 'std_logic',
6507 
            'width' => 1,
6508 
          },
6509 
          'from_register18_data_out_net_x0' => {
6510 
            'attributes' => {
6511 
              'hdlNetAttributes' => [
6512 
              ],
6513 
            },
6514 
            'hdlType' => 'std_logic',
6515 
            'width' => 1,
6516 
          },
6517 
          'from_register19_data_out_net' => {
6518 
            'attributes' => {
6519 
              'hdlNetAttributes' => [
6520 
              ],
6521 
            },
6522 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6523 
            'width' => 32,
6524 
          },
6525 
          'from_register19_data_out_net_x0' => {
6526 
            'attributes' => {
6527 
              'hdlNetAttributes' => [
6528 
              ],
6529 
            },
6530 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6531 
            'width' => 32,
6532 
          },
6533 
          'from_register1_data_out_net' => {
6534 
            'attributes' => {
6535 
              'hdlNetAttributes' => [
6536 
              ],
6537 
            },
6538 
            'hdlType' => 'std_logic',
6539 
            'width' => 1,
6540 
          },
6541 
          'from_register1_data_out_net_x0' => {
6542 
            'attributes' => {
6543 
              'hdlNetAttributes' => [
6544 
              ],
6545 
            },
6546 
            'hdlType' => 'std_logic',
6547 
            'width' => 1,
6548 
          },
6549 
          'from_register20_data_out_net' => {
6550 
            'attributes' => {
6551 
              'hdlNetAttributes' => [
6552 
              ],
6553 
            },
6554 
            'hdlType' => 'std_logic',
6555 
            'width' => 1,
6556 
          },
6557 
          'from_register20_data_out_net_x0' => {
6558 
            'attributes' => {
6559 
              'hdlNetAttributes' => [
6560 
              ],
6561 
            },
6562 
            'hdlType' => 'std_logic',
6563 
            'width' => 1,
6564 
          },
6565 
          'from_register21_data_out_net' => {
6566 
            'attributes' => {
6567 
              'hdlNetAttributes' => [
6568 
              ],
6569 
            },
6570 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6571 
            'width' => 32,
6572 
          },
6573 
          'from_register21_data_out_net_x0' => {
6574 
            'attributes' => {
6575 
              'hdlNetAttributes' => [
6576 
              ],
6577 
            },
6578 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6579 
            'width' => 32,
6580 
          },
6581 
          'from_register22_data_out_net' => {
6582 
            'attributes' => {
6583 
              'hdlNetAttributes' => [
6584 
              ],
6585 
            },
6586 
            'hdlType' => 'std_logic',
6587 
            'width' => 1,
6588 
          },
6589 
          'from_register22_data_out_net_x0' => {
6590 
            'attributes' => {
6591 
              'hdlNetAttributes' => [
6592 
              ],
6593 
            },
6594 
            'hdlType' => 'std_logic',
6595 
            'width' => 1,
6596 
          },
6597 
          'from_register23_data_out_net' => {
6598 
            'attributes' => {
6599 
              'hdlNetAttributes' => [
6600 
              ],
6601 
            },
6602 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6603 
            'width' => 32,
6604 
          },
6605 
          'from_register23_data_out_net_x0' => {
6606 
            'attributes' => {
6607 
              'hdlNetAttributes' => [
6608 
              ],
6609 
            },
6610 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6611 
            'width' => 32,
6612 
          },
6613 
          'from_register24_data_out_net' => {
6614 
            'attributes' => {
6615 
              'hdlNetAttributes' => [
6616 
              ],
6617 
            },
6618 
            'hdlType' => 'std_logic',
6619 
            'width' => 1,
6620 
          },
6621 
          'from_register24_data_out_net_x0' => {
6622 
            'attributes' => {
6623 
              'hdlNetAttributes' => [
6624 
              ],
6625 
            },
6626 
            'hdlType' => 'std_logic',
6627 
            'width' => 1,
6628 
          },
6629 
          'from_register25_data_out_net' => {
6630 
            'attributes' => {
6631 
              'hdlNetAttributes' => [
6632 
              ],
6633 
            },
6634 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6635 
            'width' => 32,
6636 
          },
6637 
          'from_register25_data_out_net_x0' => {
6638 
            'attributes' => {
6639 
              'hdlNetAttributes' => [
6640 
              ],
6641 
            },
6642 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6643 
            'width' => 32,
6644 
          },
6645 
          'from_register26_data_out_net' => {
6646 
            'attributes' => {
6647 
              'hdlNetAttributes' => [
6648 
              ],
6649 
            },
6650 
            'hdlType' => 'std_logic',
6651 
            'width' => 1,
6652 
          },
6653 
          'from_register26_data_out_net_x0' => {
6654 
            'attributes' => {
6655 
              'hdlNetAttributes' => [
6656 
              ],
6657 
            },
6658 
            'hdlType' => 'std_logic',
6659 
            'width' => 1,
6660 
          },
6661 
          'from_register27_data_out_net' => {
6662 
            'attributes' => {
6663 
              'hdlNetAttributes' => [
6664 
              ],
6665 
            },
6666 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6667 
            'width' => 32,
6668 
          },
6669 
          'from_register27_data_out_net_x0' => {
6670 
            'attributes' => {
6671 
              'hdlNetAttributes' => [
6672 
              ],
6673 
            },
6674 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6675 
            'width' => 32,
6676 
          },
6677 
          'from_register28_data_out_net' => {
6678 
            'attributes' => {
6679 
              'hdlNetAttributes' => [
6680 
              ],
6681 
            },
6682 
            'hdlType' => 'std_logic',
6683 
            'width' => 1,
6684 
          },
6685 
          'from_register28_data_out_net_x0' => {
6686 
            'attributes' => {
6687 
              'hdlNetAttributes' => [
6688 
              ],
6689 
            },
6690 
            'hdlType' => 'std_logic',
6691 
            'width' => 1,
6692 
          },
6693 
          'from_register2_data_out_net' => {
6694 
            'attributes' => {
6695 
              'hdlNetAttributes' => [
6696 
              ],
6697 
            },
6698 
            'hdlType' => 'std_logic',
6699 
            'width' => 1,
6700 
          },
6701 
          'from_register2_data_out_net_x0' => {
6702 
            'attributes' => {
6703 
              'hdlNetAttributes' => [
6704 
              ],
6705 
            },
6706 
            'hdlType' => 'std_logic',
6707 
            'width' => 1,
6708 
          },
6709 
          'from_register3_data_out_net' => {
6710 
            'attributes' => {
6711 
              'hdlNetAttributes' => [
6712 
              ],
6713 
            },
6714 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6715 
            'width' => 32,
6716 
          },
6717 
          'from_register3_data_out_net_x0' => {
6718 
            'attributes' => {
6719 
              'hdlNetAttributes' => [
6720 
              ],
6721 
            },
6722 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6723 
            'width' => 32,
6724 
          },
6725 
          'from_register4_data_out_net' => {
6726 
            'attributes' => {
6727 
              'hdlNetAttributes' => [
6728 
              ],
6729 
            },
6730 
            'hdlType' => 'std_logic',
6731 
            'width' => 1,
6732 
          },
6733 
          'from_register4_data_out_net_x0' => {
6734 
            'attributes' => {
6735 
              'hdlNetAttributes' => [
6736 
              ],
6737 
            },
6738 
            'hdlType' => 'std_logic',
6739 
            'width' => 1,
6740 
          },
6741 
          'from_register5_data_out_net' => {
6742 
            'attributes' => {
6743 
              'hdlNetAttributes' => [
6744 
              ],
6745 
            },
6746 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6747 
            'width' => 32,
6748 
          },
6749 
          'from_register5_data_out_net_x0' => {
6750 
            'attributes' => {
6751 
              'hdlNetAttributes' => [
6752 
              ],
6753 
            },
6754 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6755 
            'width' => 32,
6756 
          },
6757 
          'from_register6_data_out_net' => {
6758 
            'attributes' => {
6759 
              'hdlNetAttributes' => [
6760 
              ],
6761 
            },
6762 
            'hdlType' => 'std_logic',
6763 
            'width' => 1,
6764 
          },
6765 
          'from_register6_data_out_net_x0' => {
6766 
            'attributes' => {
6767 
              'hdlNetAttributes' => [
6768 
              ],
6769 
            },
6770 
            'hdlType' => 'std_logic',
6771 
            'width' => 1,
6772 
          },
6773 
          'from_register7_data_out_net' => {
6774 
            'attributes' => {
6775 
              'hdlNetAttributes' => [
6776 
              ],
6777 
            },
6778 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6779 
            'width' => 32,
6780 
          },
6781 
          'from_register7_data_out_net_x0' => {
6782 
            'attributes' => {
6783 
              'hdlNetAttributes' => [
6784 
              ],
6785 
            },
6786 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6787 
            'width' => 32,
6788 
          },
6789 
          'from_register8_data_out_net' => {
6790 
            'attributes' => {
6791 
              'hdlNetAttributes' => [
6792 
              ],
6793 
            },
6794 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6795 
            'width' => 32,
6796 
          },
6797 
          'from_register8_data_out_net_x0' => {
6798 
            'attributes' => {
6799 
              'hdlNetAttributes' => [
6800 
              ],
6801 
            },
6802 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6803 
            'width' => 32,
6804 
          },
6805 
          'from_register9_data_out_net' => {
6806 
            'attributes' => {
6807 
              'hdlNetAttributes' => [
6808 
              ],
6809 
            },
6810 
            'hdlType' => 'std_logic',
6811 
            'width' => 1,
6812 
          },
6813 
          'from_register9_data_out_net_x0' => {
6814 
            'attributes' => {
6815 
              'hdlNetAttributes' => [
6816 
              ],
6817 
            },
6818 
            'hdlType' => 'std_logic',
6819 
            'width' => 1,
6820 
          },
6821 
          'persistentdff_inst_q' => {
6822 
            'attributes' => {
6823 
              'hdlNetAttributes' => [
6824 
                [
6825 
                  'syn_keep',
6826 
                  'boolean',
6827 
                  'true',
6828 
                ],
6829 
                [
6830 
                  'keep',
6831 
                  'boolean',
6832 
                  'true',
6833 
                ],
6834 
                [
6835 
                  'preserve_signal',
6836 
                  'boolean',
6837 
                  'true',
6838 
                ],
6839 
              ],
6840 
            },
6841 
            'hdlType' => 'std_logic',
6842 
            'width' => 1,
6843 
          },
6844 
          'reg01_td_net' => {
6845 
            'attributes' => {
6846 
              'hdlNetAttributes' => [
6847 
              ],
6848 
            },
6849 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6850 
            'width' => 32,
6851 
          },
6852 
          'reg01_td_net_x0' => {
6853 
            'attributes' => {
6854 
              'hdlNetAttributes' => [
6855 
              ],
6856 
            },
6857 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6858 
            'width' => 32,
6859 
          },
6860 
          'reg01_tv_net' => {
6861 
            'attributes' => {
6862 
              'hdlNetAttributes' => [
6863 
              ],
6864 
            },
6865 
            'hdlType' => 'std_logic',
6866 
            'width' => 1,
6867 
          },
6868 
          'reg01_tv_net_x0' => {
6869 
            'attributes' => {
6870 
              'hdlNetAttributes' => [
6871 
              ],
6872 
            },
6873 
            'hdlType' => 'std_logic',
6874 
            'width' => 1,
6875 
          },
6876 
          'reg02_td_net' => {
6877 
            'attributes' => {
6878 
              'hdlNetAttributes' => [
6879 
              ],
6880 
            },
6881 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6882 
            'width' => 32,
6883 
          },
6884 
          'reg02_td_net_x0' => {
6885 
            'attributes' => {
6886 
              'hdlNetAttributes' => [
6887 
              ],
6888 
            },
6889 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6890 
            'width' => 32,
6891 
          },
6892 
          'reg02_tv_net' => {
6893 
            'attributes' => {
6894 
              'hdlNetAttributes' => [
6895 
              ],
6896 
            },
6897 
            'hdlType' => 'std_logic',
6898 
            'width' => 1,
6899 
          },
6900 
          'reg02_tv_net_x0' => {
6901 
            'attributes' => {
6902 
              'hdlNetAttributes' => [
6903 
              ],
6904 
            },
6905 
            'hdlType' => 'std_logic',
6906 
            'width' => 1,
6907 
          },
6908 
          'reg03_td_net' => {
6909 
            'attributes' => {
6910 
              'hdlNetAttributes' => [
6911 
              ],
6912 
            },
6913 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6914 
            'width' => 32,
6915 
          },
6916 
          'reg03_td_net_x0' => {
6917 
            'attributes' => {
6918 
              'hdlNetAttributes' => [
6919 
              ],
6920 
            },
6921 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6922 
            'width' => 32,
6923 
          },
6924 
          'reg03_tv_net' => {
6925 
            'attributes' => {
6926 
              'hdlNetAttributes' => [
6927 
              ],
6928 
            },
6929 
            'hdlType' => 'std_logic',
6930 
            'width' => 1,
6931 
          },
6932 
          'reg03_tv_net_x0' => {
6933 
            'attributes' => {
6934 
              'hdlNetAttributes' => [
6935 
              ],
6936 
            },
6937 
            'hdlType' => 'std_logic',
6938 
            'width' => 1,
6939 
          },
6940 
          'reg04_td_net' => {
6941 
            'attributes' => {
6942 
              'hdlNetAttributes' => [
6943 
              ],
6944 
            },
6945 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6946 
            'width' => 32,
6947 
          },
6948 
          'reg04_td_net_x0' => {
6949 
            'attributes' => {
6950 
              'hdlNetAttributes' => [
6951 
              ],
6952 
            },
6953 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6954 
            'width' => 32,
6955 
          },
6956 
          'reg04_tv_net' => {
6957 
            'attributes' => {
6958 
              'hdlNetAttributes' => [
6959 
              ],
6960 
            },
6961 
            'hdlType' => 'std_logic',
6962 
            'width' => 1,
6963 
          },
6964 
          'reg04_tv_net_x0' => {
6965 
            'attributes' => {
6966 
              'hdlNetAttributes' => [
6967 
              ],
6968 
            },
6969 
            'hdlType' => 'std_logic',
6970 
            'width' => 1,
6971 
          },
6972 
          'reg05_td_net' => {
6973 
            'attributes' => {
6974 
              'hdlNetAttributes' => [
6975 
              ],
6976 
            },
6977 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6978 
            'width' => 32,
6979 
          },
6980 
          'reg05_td_net_x0' => {
6981 
            'attributes' => {
6982 
              'hdlNetAttributes' => [
6983 
              ],
6984 
            },
6985 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6986 
            'width' => 32,
6987 
          },
6988 
          'reg05_tv_net' => {
6989 
            'attributes' => {
6990 
              'hdlNetAttributes' => [
6991 
              ],
6992 
            },
6993 
            'hdlType' => 'std_logic',
6994 
            'width' => 1,
6995 
          },
6996 
          'reg05_tv_net_x0' => {
6997 
            'attributes' => {
6998 
              'hdlNetAttributes' => [
6999 
              ],
7000 
            },
7001 
            'hdlType' => 'std_logic',
7002 
            'width' => 1,
7003 
          },
7004 
          'reg06_td_net' => {
7005 
            'attributes' => {
7006 
              'hdlNetAttributes' => [
7007 
              ],
7008 
            },
7009 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7010 
            'width' => 32,
7011 
          },
7012 
          'reg06_td_net_x0' => {
7013 
            'attributes' => {
7014 
              'hdlNetAttributes' => [
7015 
              ],
7016 
            },
7017 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7018 
            'width' => 32,
7019 
          },
7020 
          'reg06_tv_net' => {
7021 
            'attributes' => {
7022 
              'hdlNetAttributes' => [
7023 
              ],
7024 
            },
7025 
            'hdlType' => 'std_logic',
7026 
            'width' => 1,
7027 
          },
7028 
          'reg06_tv_net_x0' => {
7029 
            'attributes' => {
7030 
              'hdlNetAttributes' => [
7031 
              ],
7032 
            },
7033 
            'hdlType' => 'std_logic',
7034 
            'width' => 1,
7035 
          },
7036 
          'reg07_td_net' => {
7037 
            'attributes' => {
7038 
              'hdlNetAttributes' => [
7039 
              ],
7040 
            },
7041 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7042 
            'width' => 32,
7043 
          },
7044 
          'reg07_td_net_x0' => {
7045 
            'attributes' => {
7046 
              'hdlNetAttributes' => [
7047 
              ],
7048 
            },
7049 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7050 
            'width' => 32,
7051 
          },
7052 
          'reg07_tv_net' => {
7053 
            'attributes' => {
7054 
              'hdlNetAttributes' => [
7055 
              ],
7056 
            },
7057 
            'hdlType' => 'std_logic',
7058 
            'width' => 1,
7059 
          },
7060 
          'reg07_tv_net_x0' => {
7061 
            'attributes' => {
7062 
              'hdlNetAttributes' => [
7063 
              ],
7064 
            },
7065 
            'hdlType' => 'std_logic',
7066 
            'width' => 1,
7067 
          },
7068 
          'reg08_td_net' => {
7069 
            'attributes' => {
7070 
              'hdlNetAttributes' => [
7071 
              ],
7072 
            },
7073 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7074 
            'width' => 32,
7075 
          },
7076 
          'reg08_td_net_x0' => {
7077 
            'attributes' => {
7078 
              'hdlNetAttributes' => [
7079 
              ],
7080 
            },
7081 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7082 
            'width' => 32,
7083 
          },
7084 
          'reg08_tv_net' => {
7085 
            'attributes' => {
7086 
              'hdlNetAttributes' => [
7087 
              ],
7088 
            },
7089 
            'hdlType' => 'std_logic',
7090 
            'width' => 1,
7091 
          },
7092 
          'reg08_tv_net_x0' => {
7093 
            'attributes' => {
7094 
              'hdlNetAttributes' => [
7095 
              ],
7096 
            },
7097 
            'hdlType' => 'std_logic',
7098 
            'width' => 1,
7099 
          },
7100 
          'reg09_td_net' => {
7101 
            'attributes' => {
7102 
              'hdlNetAttributes' => [
7103 
              ],
7104 
            },
7105 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7106 
            'width' => 32,
7107 
          },
7108 
          'reg09_td_net_x0' => {
7109 
            'attributes' => {
7110 
              'hdlNetAttributes' => [
7111 
              ],
7112 
            },
7113 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7114 
            'width' => 32,
7115 
          },
7116 
          'reg09_tv_net' => {
7117 
            'attributes' => {
7118 
              'hdlNetAttributes' => [
7119 
              ],
7120 
            },
7121 
            'hdlType' => 'std_logic',
7122 
            'width' => 1,
7123 
          },
7124 
          'reg09_tv_net_x0' => {
7125 
            'attributes' => {
7126 
              'hdlNetAttributes' => [
7127 
              ],
7128 
            },
7129 
            'hdlType' => 'std_logic',
7130 
            'width' => 1,
7131 
          },
7132 
          'reg10_td_net' => {
7133 
            'attributes' => {
7134 
              'hdlNetAttributes' => [
7135 
              ],
7136 
            },
7137 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7138 
            'width' => 32,
7139 
          },
7140 
          'reg10_td_net_x0' => {
7141 
            'attributes' => {
7142 
              'hdlNetAttributes' => [
7143 
              ],
7144 
            },
7145 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7146 
            'width' => 32,
7147 
          },
7148 
          'reg10_tv_net' => {
7149 
            'attributes' => {
7150 
              'hdlNetAttributes' => [
7151 
              ],
7152 
            },
7153 
            'hdlType' => 'std_logic',
7154 
            'width' => 1,
7155 
          },
7156 
          'reg10_tv_net_x0' => {
7157 
            'attributes' => {
7158 
              'hdlNetAttributes' => [
7159 
              ],
7160 
            },
7161 
            'hdlType' => 'std_logic',
7162 
            'width' => 1,
7163 
          },
7164 
          'reg11_td_net' => {
7165 
            'attributes' => {
7166 
              'hdlNetAttributes' => [
7167 
              ],
7168 
            },
7169 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7170 
            'width' => 32,
7171 
          },
7172 
          'reg11_td_net_x0' => {
7173 
            'attributes' => {
7174 
              'hdlNetAttributes' => [
7175 
              ],
7176 
            },
7177 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7178 
            'width' => 32,
7179 
          },
7180 
          'reg11_tv_net' => {
7181 
            'attributes' => {
7182 
              'hdlNetAttributes' => [
7183 
              ],
7184 
            },
7185 
            'hdlType' => 'std_logic',
7186 
            'width' => 1,
7187 
          },
7188 
          'reg11_tv_net_x0' => {
7189 
            'attributes' => {
7190 
              'hdlNetAttributes' => [
7191 
              ],
7192 
            },
7193 
            'hdlType' => 'std_logic',
7194 
            'width' => 1,
7195 
          },
7196 
          'reg12_td_net' => {
7197 
            'attributes' => {
7198 
              'hdlNetAttributes' => [
7199 
              ],
7200 
            },
7201 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7202 
            'width' => 32,
7203 
          },
7204 
          'reg12_td_net_x0' => {
7205 
            'attributes' => {
7206 
              'hdlNetAttributes' => [
7207 
              ],
7208 
            },
7209 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7210 
            'width' => 32,
7211 
          },
7212 
          'reg12_tv_net' => {
7213 
            'attributes' => {
7214 
              'hdlNetAttributes' => [
7215 
              ],
7216 
            },
7217 
            'hdlType' => 'std_logic',
7218 
            'width' => 1,
7219 
          },
7220 
          'reg12_tv_net_x0' => {
7221 
            'attributes' => {
7222 
              'hdlNetAttributes' => [
7223 
              ],
7224 
            },
7225 
            'hdlType' => 'std_logic',
7226 
            'width' => 1,
7227 
          },
7228 
          'reg13_td_net' => {
7229 
            'attributes' => {
7230 
              'hdlNetAttributes' => [
7231 
              ],
7232 
            },
7233 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7234 
            'width' => 32,
7235 
          },
7236 
          'reg13_td_net_x0' => {
7237 
            'attributes' => {
7238 
              'hdlNetAttributes' => [
7239 
              ],
7240 
            },
7241 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7242 
            'width' => 32,
7243 
          },
7244 
          'reg13_tv_net' => {
7245 
            'attributes' => {
7246 
              'hdlNetAttributes' => [
7247 
              ],
7248 
            },
7249 
            'hdlType' => 'std_logic',
7250 
            'width' => 1,
7251 
          },
7252 
          'reg13_tv_net_x0' => {
7253 
            'attributes' => {
7254 
              'hdlNetAttributes' => [
7255 
              ],
7256 
            },
7257 
            'hdlType' => 'std_logic',
7258 
            'width' => 1,
7259 
          },
7260 
          'reg14_td_net' => {
7261 
            'attributes' => {
7262 
              'hdlNetAttributes' => [
7263 
              ],
7264 
            },
7265 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7266 
            'width' => 32,
7267 
          },
7268 
          'reg14_td_net_x0' => {
7269 
            'attributes' => {
7270 
              'hdlNetAttributes' => [
7271 
              ],
7272 
            },
7273 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7274 
            'width' => 32,
7275 
          },
7276 
          'reg14_tv_net' => {
7277 
            'attributes' => {
7278 
              'hdlNetAttributes' => [
7279 
              ],
7280 
            },
7281 
            'hdlType' => 'std_logic',
7282 
            'width' => 1,
7283 
          },
7284 
          'reg14_tv_net_x0' => {
7285 
            'attributes' => {
7286 
              'hdlNetAttributes' => [
7287 
              ],
7288 
            },
7289 
            'hdlType' => 'std_logic',
7290 
            'width' => 1,
7291 
          },
7292 
          'to_register10_dout_net' => {
7293 
            'attributes' => {
7294 
              'hdlNetAttributes' => [
7295 
              ],
7296 
            },
7297 
            'hdlType' => 'std_logic',
7298 
            'width' => 1,
7299 
          },
7300 
          'to_register11_dout_net' => {
7301 
            'attributes' => {
7302 
              'hdlNetAttributes' => [
7303 
              ],
7304 
            },
7305 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7306 
            'width' => 32,
7307 
          },
7308 
          'to_register12_dout_net' => {
7309 
            'attributes' => {
7310 
              'hdlNetAttributes' => [
7311 
              ],
7312 
            },
7313 
            'hdlType' => 'std_logic',
7314 
            'width' => 1,
7315 
          },
7316 
          'to_register13_dout_net' => {
7317 
            'attributes' => {
7318 
              'hdlNetAttributes' => [
7319 
              ],
7320 
            },
7321 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7322 
            'width' => 32,
7323 
          },
7324 
          'to_register14_dout_net' => {
7325 
            'attributes' => {
7326 
              'hdlNetAttributes' => [
7327 
              ],
7328 
            },
7329 
            'hdlType' => 'std_logic',
7330 
            'width' => 1,
7331 
          },
7332 
          'to_register15_dout_net' => {
7333 
            'attributes' => {
7334 
              'hdlNetAttributes' => [
7335 
              ],
7336 
            },
7337 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7338 
            'width' => 32,
7339 
          },
7340 
          'to_register16_dout_net' => {
7341 
            'attributes' => {
7342 
              'hdlNetAttributes' => [
7343 
              ],
7344 
            },
7345 
            'hdlType' => 'std_logic',
7346 
            'width' => 1,
7347 
          },
7348 
          'to_register17_dout_net' => {
7349 
            'attributes' => {
7350 
              'hdlNetAttributes' => [
7351 
              ],
7352 
            },
7353 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7354 
            'width' => 32,
7355 
          },
7356 
          'to_register18_dout_net' => {
7357 
            'attributes' => {
7358 
              'hdlNetAttributes' => [
7359 
              ],
7360 
            },
7361 
            'hdlType' => 'std_logic',
7362 
            'width' => 1,
7363 
          },
7364 
          'to_register19_dout_net' => {
7365 
            'attributes' => {
7366 
              'hdlNetAttributes' => [
7367 
              ],
7368 
            },
7369 
            'hdlType' => 'std_logic',
7370 
            'width' => 1,
7371 
          },
7372 
          'to_register1_dout_net' => {
7373 
            'attributes' => {
7374 
              'hdlNetAttributes' => [
7375 
              ],
7376 
            },
7377 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7378 
            'width' => 32,
7379 
          },
7380 
          'to_register20_dout_net' => {
7381 
            'attributes' => {
7382 
              'hdlNetAttributes' => [
7383 
              ],
7384 
            },
7385 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7386 
            'width' => 32,
7387 
          },
7388 
          'to_register21_dout_net' => {
7389 
            'attributes' => {
7390 
              'hdlNetAttributes' => [
7391 
              ],
7392 
            },
7393 
            'hdlType' => 'std_logic',
7394 
            'width' => 1,
7395 
          },
7396 
          'to_register22_dout_net' => {
7397 
            'attributes' => {
7398 
              'hdlNetAttributes' => [
7399 
              ],
7400 
            },
7401 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7402 
            'width' => 32,
7403 
          },
7404 
          'to_register23_dout_net' => {
7405 
            'attributes' => {
7406 
              'hdlNetAttributes' => [
7407 
              ],
7408 
            },
7409 
            'hdlType' => 'std_logic',
7410 
            'width' => 1,
7411 
          },
7412 
          'to_register24_dout_net' => {
7413 
            'attributes' => {
7414 
              'hdlNetAttributes' => [
7415 
              ],
7416 
            },
7417 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7418 
            'width' => 32,
7419 
          },
7420 
          'to_register25_dout_net' => {
7421 
            'attributes' => {
7422 
              'hdlNetAttributes' => [
7423 
              ],
7424 
            },
7425 
            'hdlType' => 'std_logic',
7426 
            'width' => 1,
7427 
          },
7428 
          'to_register26_dout_net' => {
7429 
            'attributes' => {
7430 
              'hdlNetAttributes' => [
7431 
              ],
7432 
            },
7433 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7434 
            'width' => 32,
7435 
          },
7436 
          'to_register27_dout_net' => {
7437 
            'attributes' => {
7438 
              'hdlNetAttributes' => [
7439 
              ],
7440 
            },
7441 
            'hdlType' => 'std_logic',
7442 
            'width' => 1,
7443 
          },
7444 
          'to_register28_dout_net' => {
7445 
            'attributes' => {
7446 
              'hdlNetAttributes' => [
7447 
              ],
7448 
            },
7449 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7450 
            'width' => 32,
7451 
          },
7452 
          'to_register29_dout_net' => {
7453 
            'attributes' => {
7454 
              'hdlNetAttributes' => [
7455 
              ],
7456 
            },
7457 
            'hdlType' => 'std_logic',
7458 
            'width' => 1,
7459 
          },
7460 
          'to_register2_dout_net' => {
7461 
            'attributes' => {
7462 
              'hdlNetAttributes' => [
7463 
              ],
7464 
            },
7465 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7466 
            'width' => 32,
7467 
          },
7468 
          'to_register30_dout_net' => {
7469 
            'attributes' => {
7470 
              'hdlNetAttributes' => [
7471 
              ],
7472 
            },
7473 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7474 
            'width' => 32,
7475 
          },
7476 
          'to_register31_dout_net' => {
7477 
            'attributes' => {
7478 
              'hdlNetAttributes' => [
7479 
              ],
7480 
            },
7481 
            'hdlType' => 'std_logic',
7482 
            'width' => 1,
7483 
          },
7484 
          'to_register32_dout_net' => {
7485 
            'attributes' => {
7486 
              'hdlNetAttributes' => [
7487 
              ],
7488 
            },
7489 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7490 
            'width' => 32,
7491 
          },
7492 
          'to_register33_dout_net' => {
7493 
            'attributes' => {
7494 
              'hdlNetAttributes' => [
7495 
              ],
7496 
            },
7497 
            'hdlType' => 'std_logic',
7498 
            'width' => 1,
7499 
          },
7500 
          'to_register34_dout_net' => {
7501 
            'attributes' => {
7502 
              'hdlNetAttributes' => [
7503 
              ],
7504 
            },
7505 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7506 
            'width' => 32,
7507 
          },
7508 
          'to_register3_dout_net' => {
7509 
            'attributes' => {
7510 
              'hdlNetAttributes' => [
7511 
              ],
7512 
            },
7513 
            'hdlType' => 'std_logic',
7514 
            'width' => 1,
7515 
          },
7516 
          'to_register4_dout_net' => {
7517 
            'attributes' => {
7518 
              'hdlNetAttributes' => [
7519 
              ],
7520 
            },
7521 
            'hdlType' => 'std_logic',
7522 
            'width' => 1,
7523 
          },
7524 
          'to_register5_dout_net' => {
7525 
            'attributes' => {
7526 
              'hdlNetAttributes' => [
7527 
              ],
7528 
            },
7529 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7530 
            'width' => 32,
7531 
          },
7532 
          'to_register6_dout_net' => {
7533 
            'attributes' => {
7534 
              'hdlNetAttributes' => [
7535 
              ],
7536 
            },
7537 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7538 
            'width' => 32,
7539 
          },
7540 
          'to_register7_dout_net' => {
7541 
            'attributes' => {
7542 
              'hdlNetAttributes' => [
7543 
              ],
7544 
            },
7545 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7546 
            'width' => 32,
7547 
          },
7548 
          'to_register8_dout_net' => {
7549 
            'attributes' => {
7550 
              'hdlNetAttributes' => [
7551 
              ],
7552 
            },
7553 
            'hdlType' => 'std_logic',
7554 
            'width' => 1,
7555 
          },
7556 
          'to_register9_dout_net' => {
7557 
            'attributes' => {
7558 
              'hdlNetAttributes' => [
7559 
              ],
7560 
            },
7561 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7562 
            'width' => 32,
7563 
          },
7564 
        },
7565 
        'ports' => {
7566 
          'ce' => {
7567 
            'attributes' => {
7568 
              'defaultHdlValue' => '\'1\'',
7569 
              'domain' => 'default',
7570 
              'group' => 4,
7571 
              'isCe' => 1,
7572 
              'period' => 1,
7573 
            },
7574 
            'direction' => 'in',
7575 
            'hdlType' => 'std_logic',
7576 
            'width' => 1,
7577 
          },
7578 
          'clk' => {
7579 
            'attributes' => {
7580 
              'domain' => 'default',
7581 
              'group' => 4,
7582 
              'isClk' => 1,
7583 
              'period' => 1,
7584 
              'type' => 'logic',
7585 
            },
7586 
            'direction' => 'in',
7587 
            'hdlType' => 'std_logic',
7588 
            'width' => 1,
7589 
          },
7590 
          'debug_in_1i' => {
7591 
            'attributes' => {
7592 
              'bin_pt' => 0,
7593 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
7594 
              'is_floating_block' => 1,
7595 
              'is_gateway_port' => 1,
7596 
              'must_be_hdl_vector' => 1,
7597 
              'period' => 1,
7598 
              'port_id' => 0,
7599 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i/debug_in_1i',
7600 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_1i',
7601 
              'timingConstraint' => 'none',
7602 
              'type' => 'UFix_32_0',
7603 
            },
7604 
            'direction' => 'in',
7605 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7606 
            'width' => 32,
7607 
          },
7608 
          'debug_in_2i' => {
7609 
            'attributes' => {
7610 
              'bin_pt' => 0,
7611 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
7612 
              'is_floating_block' => 1,
7613 
              'is_gateway_port' => 1,
7614 
              'must_be_hdl_vector' => 1,
7615 
              'period' => 1,
7616 
              'port_id' => 0,
7617 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i/debug_in_2i',
7618 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_2i',
7619 
              'timingConstraint' => 'none',
7620 
              'type' => 'UFix_32_0',
7621 
            },
7622 
            'direction' => 'in',
7623 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7624 
            'width' => 32,
7625 
          },
7626 
          'debug_in_3i' => {
7627 
            'attributes' => {
7628 
              'bin_pt' => 0,
7629 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
7630 
              'is_floating_block' => 1,
7631 
              'is_gateway_port' => 1,
7632 
              'must_be_hdl_vector' => 1,
7633 
              'period' => 1,
7634 
              'port_id' => 0,
7635 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i/debug_in_3i',
7636 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_3i',
7637 
              'timingConstraint' => 'none',
7638 
              'type' => 'UFix_32_0',
7639 
            },
7640 
            'direction' => 'in',
7641 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7642 
            'width' => 32,
7643 
          },
7644 
          'debug_in_4i' => {
7645 
            'attributes' => {
7646 
              'bin_pt' => 0,
7647 
              'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
7648 
              'is_floating_block' => 1,
7649 
              'is_gateway_port' => 1,
7650 
              'must_be_hdl_vector' => 1,
7651 
              'period' => 1,
7652 
              'port_id' => 0,
7653 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
7654 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i',
7655 
              'timingConstraint' => 'none',
7656 
              'type' => 'UFix_32_0',
7657 
            },
7658 
            'direction' => 'in',
7659 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7660 
            'width' => 32,
7661 
          },
7662 
          'dma_host2board_busy' => {
7663 
            'attributes' => {
7664 
              'bin_pt' => 0,
7665 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
7666 
              'is_floating_block' => 1,
7667 
              'is_gateway_port' => 1,
7668 
              'must_be_hdl_vector' => 1,
7669 
              'period' => 1,
7670 
              'port_id' => 0,
7671 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
7672 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
7673 
              'timingConstraint' => 'none',
7674 
              'type' => 'UFix_1_0',
7675 
            },
7676 
            'direction' => 'in',
7677 
            'hdlType' => 'std_logic',
7678 
            'width' => 1,
7679 
          },
7680 
          'dma_host2board_done' => {
7681 
            'attributes' => {
7682 
              'bin_pt' => 0,
7683 
              'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
7684 
              'is_floating_block' => 1,
7685 
              'is_gateway_port' => 1,
7686 
              'must_be_hdl_vector' => 1,
7687 
              'period' => 1,
7688 
              'port_id' => 0,
7689 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done/DMA_Host2Board_Done',
7690 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Done',
7691 
              'timingConstraint' => 'none',
7692 
              'type' => 'UFix_1_0',
7693 
            },
7694 
            'direction' => 'in',
7695 
            'hdlType' => 'std_logic',
7696 
            'width' => 1,
7697 
          },
7698 
          'from_register10_data_out' => {
7699 
            'attributes' => {
7700 
              'bin_pt' => 0,
7701 
              'is_floating_block' => 1,
7702 
              'must_be_hdl_vector' => 1,
7703 
              'period' => 1,
7704 
              'port_id' => 0,
7705 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register10/data_out',
7706 
              'type' => 'UFix_32_0',
7707 
            },
7708 
            'direction' => 'in',
7709 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7710 
            'width' => 32,
7711 
          },
7712 
          'from_register11_data_out' => {
7713 
            'attributes' => {
7714 
              'bin_pt' => 0,
7715 
              'is_floating_block' => 1,
7716 
              'must_be_hdl_vector' => 1,
7717 
              'period' => 1,
7718 
              'port_id' => 0,
7719 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register11/data_out',
7720 
              'type' => 'UFix_32_0',
7721 
            },
7722 
            'direction' => 'in',
7723 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7724 
            'width' => 32,
7725 
          },
7726 
          'from_register12_data_out' => {
7727 
            'attributes' => {
7728 
              'bin_pt' => 0,
7729 
              'is_floating_block' => 1,
7730 
              'must_be_hdl_vector' => 1,
7731 
              'period' => 1,
7732 
              'port_id' => 0,
7733 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register12/data_out',
7734 
              'type' => 'UFix_1_0',
7735 
            },
7736 
            'direction' => 'in',
7737 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7738 
            'width' => 1,
7739 
          },
7740 
          'from_register13_data_out' => {
7741 
            'attributes' => {
7742 
              'bin_pt' => 0,
7743 
              'is_floating_block' => 1,
7744 
              'must_be_hdl_vector' => 1,
7745 
              'period' => 1,
7746 
              'port_id' => 0,
7747 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register13/data_out',
7748 
              'type' => 'UFix_32_0',
7749 
            },
7750 
            'direction' => 'in',
7751 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7752 
            'width' => 32,
7753 
          },
7754 
          'from_register14_data_out' => {
7755 
            'attributes' => {
7756 
              'bin_pt' => 0,
7757 
              'is_floating_block' => 1,
7758 
              'must_be_hdl_vector' => 1,
7759 
              'period' => 1,
7760 
              'port_id' => 0,
7761 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register14/data_out',
7762 
              'type' => 'UFix_1_0',
7763 
            },
7764 
            'direction' => 'in',
7765 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7766 
            'width' => 1,
7767 
          },
7768 
          'from_register15_data_out' => {
7769 
            'attributes' => {
7770 
              'bin_pt' => 0,
7771 
              'is_floating_block' => 1,
7772 
              'must_be_hdl_vector' => 1,
7773 
              'period' => 1,
7774 
              'port_id' => 0,
7775 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register15/data_out',
7776 
              'type' => 'UFix_32_0',
7777 
            },
7778 
            'direction' => 'in',
7779 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7780 
            'width' => 32,
7781 
          },
7782 
          'from_register16_data_out' => {
7783 
            'attributes' => {
7784 
              'bin_pt' => 0,
7785 
              'is_floating_block' => 1,
7786 
              'must_be_hdl_vector' => 1,
7787 
              'period' => 1,
7788 
              'port_id' => 0,
7789 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register16/data_out',
7790 
              'type' => 'UFix_1_0',
7791 
            },
7792 
            'direction' => 'in',
7793 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7794 
            'width' => 1,
7795 
          },
7796 
          'from_register17_data_out' => {
7797 
            'attributes' => {
7798 
              'bin_pt' => 0,
7799 
              'is_floating_block' => 1,
7800 
              'must_be_hdl_vector' => 1,
7801 
              'period' => 1,
7802 
              'port_id' => 0,
7803 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register17/data_out',
7804 
              'type' => 'UFix_32_0',
7805 
            },
7806 
            'direction' => 'in',
7807 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7808 
            'width' => 32,
7809 
          },
7810 
          'from_register18_data_out' => {
7811 
            'attributes' => {
7812 
              'bin_pt' => 0,
7813 
              'is_floating_block' => 1,
7814 
              'must_be_hdl_vector' => 1,
7815 
              'period' => 1,
7816 
              'port_id' => 0,
7817 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register18/data_out',
7818 
              'type' => 'UFix_1_0',
7819 
            },
7820 
            'direction' => 'in',
7821 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7822 
            'width' => 1,
7823 
          },
7824 
          'from_register19_data_out' => {
7825 
            'attributes' => {
7826 
              'bin_pt' => 0,
7827 
              'is_floating_block' => 1,
7828 
              'must_be_hdl_vector' => 1,
7829 
              'period' => 1,
7830 
              'port_id' => 0,
7831 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register19/data_out',
7832 
              'type' => 'UFix_32_0',
7833 
            },
7834 
            'direction' => 'in',
7835 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7836 
            'width' => 32,
7837 
          },
7838 
          'from_register1_data_out' => {
7839 
            'attributes' => {
7840 
              'bin_pt' => 0,
7841 
              'is_floating_block' => 1,
7842 
              'must_be_hdl_vector' => 1,
7843 
              'period' => 1,
7844 
              'port_id' => 0,
7845 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register1/data_out',
7846 
              'type' => 'UFix_1_0',
7847 
            },
7848 
            'direction' => 'in',
7849 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7850 
            'width' => 1,
7851 
          },
7852 
          'from_register20_data_out' => {
7853 
            'attributes' => {
7854 
              'bin_pt' => 0,
7855 
              'is_floating_block' => 1,
7856 
              'must_be_hdl_vector' => 1,
7857 
              'period' => 1,
7858 
              'port_id' => 0,
7859 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register20/data_out',
7860 
              'type' => 'UFix_1_0',
7861 
            },
7862 
            'direction' => 'in',
7863 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7864 
            'width' => 1,
7865 
          },
7866 
          'from_register21_data_out' => {
7867 
            'attributes' => {
7868 
              'bin_pt' => 0,
7869 
              'is_floating_block' => 1,
7870 
              'must_be_hdl_vector' => 1,
7871 
              'period' => 1,
7872 
              'port_id' => 0,
7873 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register21/data_out',
7874 
              'type' => 'UFix_32_0',
7875 
            },
7876 
            'direction' => 'in',
7877 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7878 
            'width' => 32,
7879 
          },
7880 
          'from_register22_data_out' => {
7881 
            'attributes' => {
7882 
              'bin_pt' => 0,
7883 
              'is_floating_block' => 1,
7884 
              'must_be_hdl_vector' => 1,
7885 
              'period' => 1,
7886 
              'port_id' => 0,
7887 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register22/data_out',
7888 
              'type' => 'UFix_1_0',
7889 
            },
7890 
            'direction' => 'in',
7891 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7892 
            'width' => 1,
7893 
          },
7894 
          'from_register23_data_out' => {
7895 
            'attributes' => {
7896 
              'bin_pt' => 0,
7897 
              'is_floating_block' => 1,
7898 
              'must_be_hdl_vector' => 1,
7899 
              'period' => 1,
7900 
              'port_id' => 0,
7901 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register23/data_out',
7902 
              'type' => 'UFix_32_0',
7903 
            },
7904 
            'direction' => 'in',
7905 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7906 
            'width' => 32,
7907 
          },
7908 
          'from_register24_data_out' => {
7909 
            'attributes' => {
7910 
              'bin_pt' => 0,
7911 
              'is_floating_block' => 1,
7912 
              'must_be_hdl_vector' => 1,
7913 
              'period' => 1,
7914 
              'port_id' => 0,
7915 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register24/data_out',
7916 
              'type' => 'UFix_1_0',
7917 
            },
7918 
            'direction' => 'in',
7919 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7920 
            'width' => 1,
7921 
          },
7922 
          'from_register25_data_out' => {
7923 
            'attributes' => {
7924 
              'bin_pt' => 0,
7925 
              'is_floating_block' => 1,
7926 
              'must_be_hdl_vector' => 1,
7927 
              'period' => 1,
7928 
              'port_id' => 0,
7929 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register25/data_out',
7930 
              'type' => 'UFix_32_0',
7931 
            },
7932 
            'direction' => 'in',
7933 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7934 
            'width' => 32,
7935 
          },
7936 
          'from_register26_data_out' => {
7937 
            'attributes' => {
7938 
              'bin_pt' => 0,
7939 
              'is_floating_block' => 1,
7940 
              'must_be_hdl_vector' => 1,
7941 
              'period' => 1,
7942 
              'port_id' => 0,
7943 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register26/data_out',
7944 
              'type' => 'UFix_1_0',
7945 
            },
7946 
            'direction' => 'in',
7947 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7948 
            'width' => 1,
7949 
          },
7950 
          'from_register27_data_out' => {
7951 
            'attributes' => {
7952 
              'bin_pt' => 0,
7953 
              'is_floating_block' => 1,
7954 
              'must_be_hdl_vector' => 1,
7955 
              'period' => 1,
7956 
              'port_id' => 0,
7957 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register27/data_out',
7958 
              'type' => 'UFix_32_0',
7959 
            },
7960 
            'direction' => 'in',
7961 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7962 
            'width' => 32,
7963 
          },
7964 
          'from_register28_data_out' => {
7965 
            'attributes' => {
7966 
              'bin_pt' => 0,
7967 
              'is_floating_block' => 1,
7968 
              'must_be_hdl_vector' => 1,
7969 
              'period' => 1,
7970 
              'port_id' => 0,
7971 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register28/data_out',
7972 
              'type' => 'UFix_1_0',
7973 
            },
7974 
            'direction' => 'in',
7975 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7976 
            'width' => 1,
7977 
          },
7978 
          'from_register2_data_out' => {
7979 
            'attributes' => {
7980 
              'bin_pt' => 0,
7981 
              'is_floating_block' => 1,
7982 
              'must_be_hdl_vector' => 1,
7983 
              'period' => 1,
7984 
              'port_id' => 0,
7985 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register2/data_out',
7986 
              'type' => 'UFix_1_0',
7987 
            },
7988 
            'direction' => 'in',
7989 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7990 
            'width' => 1,
7991 
          },
7992 
          'from_register3_data_out' => {
7993 
            'attributes' => {
7994 
              'bin_pt' => 0,
7995 
              'is_floating_block' => 1,
7996 
              'must_be_hdl_vector' => 1,
7997 
              'period' => 1,
7998 
              'port_id' => 0,
7999 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register3/data_out',
8000 
              'type' => 'UFix_32_0',
8001 
            },
8002 
            'direction' => 'in',
8003 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8004 
            'width' => 32,
8005 
          },
8006 
          'from_register4_data_out' => {
8007 
            'attributes' => {
8008 
              'bin_pt' => 0,
8009 
              'is_floating_block' => 1,
8010 
              'must_be_hdl_vector' => 1,
8011 
              'period' => 1,
8012 
              'port_id' => 0,
8013 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register4/data_out',
8014 
              'type' => 'UFix_1_0',
8015 
            },
8016 
            'direction' => 'in',
8017 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8018 
            'width' => 1,
8019 
          },
8020 
          'from_register5_data_out' => {
8021 
            'attributes' => {
8022 
              'bin_pt' => 0,
8023 
              'is_floating_block' => 1,
8024 
              'must_be_hdl_vector' => 1,
8025 
              'period' => 1,
8026 
              'port_id' => 0,
8027 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register5/data_out',
8028 
              'type' => 'UFix_32_0',
8029 
            },
8030 
            'direction' => 'in',
8031 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8032 
            'width' => 32,
8033 
          },
8034 
          'from_register6_data_out' => {
8035 
            'attributes' => {
8036 
              'bin_pt' => 0,
8037 
              'is_floating_block' => 1,
8038 
              'must_be_hdl_vector' => 1,
8039 
              'period' => 1,
8040 
              'port_id' => 0,
8041 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register6/data_out',
8042 
              'type' => 'UFix_1_0',
8043 
            },
8044 
            'direction' => 'in',
8045 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8046 
            'width' => 1,
8047 
          },
8048 
          'from_register7_data_out' => {
8049 
            'attributes' => {
8050 
              'bin_pt' => 0,
8051 
              'is_floating_block' => 1,
8052 
              'must_be_hdl_vector' => 1,
8053 
              'period' => 1,
8054 
              'port_id' => 0,
8055 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register7/data_out',
8056 
              'type' => 'UFix_32_0',
8057 
            },
8058 
            'direction' => 'in',
8059 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8060 
            'width' => 32,
8061 
          },
8062 
          'from_register8_data_out' => {
8063 
            'attributes' => {
8064 
              'bin_pt' => 0,
8065 
              'is_floating_block' => 1,
8066 
              'must_be_hdl_vector' => 1,
8067 
              'period' => 1,
8068 
              'port_id' => 0,
8069 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register8/data_out',
8070 
              'type' => 'UFix_32_0',
8071 
            },
8072 
            'direction' => 'in',
8073 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8074 
            'width' => 32,
8075 
          },
8076 
          'from_register9_data_out' => {
8077 
            'attributes' => {
8078 
              'bin_pt' => 0,
8079 
              'is_floating_block' => 1,
8080 
              'must_be_hdl_vector' => 1,
8081 
              'period' => 1,
8082 
              'port_id' => 0,
8083 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/From Register9/data_out',
8084 
              'type' => 'UFix_1_0',
8085 
            },
8086 
            'direction' => 'in',
8087 
            'hdlType' => 'std_logic_vector(0 downto 0)',
8088 
            'width' => 1,
8089 
          },
8090 
          'reg01_rd' => {
8091 
            'attributes' => {
8092 
              'bin_pt' => 0,
8093 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
8094 
              'is_floating_block' => 1,
8095 
              'is_gateway_port' => 1,
8096 
              'must_be_hdl_vector' => 1,
8097 
              'period' => 1,
8098 
              'port_id' => 0,
8099 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd/reg01_rd',
8100 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rd',
8101 
              'timingConstraint' => 'none',
8102 
              'type' => 'UFix_32_0',
8103 
            },
8104 
            'direction' => 'out',
8105 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8106 
            'width' => 32,
8107 
          },
8108 
          'reg01_rv' => {
8109 
            'attributes' => {
8110 
              'bin_pt' => 0,
8111 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
8112 
              'is_floating_block' => 1,
8113 
              'is_gateway_port' => 1,
8114 
              'must_be_hdl_vector' => 1,
8115 
              'period' => 1,
8116 
              'port_id' => 0,
8117 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv/reg01_rv',
8118 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_rv',
8119 
              'timingConstraint' => 'none',
8120 
              'type' => 'UFix_1_0',
8121 
            },
8122 
            'direction' => 'out',
8123 
            'hdlType' => 'std_logic',
8124 
            'width' => 1,
8125 
          },
8126 
          'reg01_td' => {
8127 
            'attributes' => {
8128 
              'bin_pt' => 0,
8129 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
8130 
              'is_floating_block' => 1,
8131 
              'is_gateway_port' => 1,
8132 
              'must_be_hdl_vector' => 1,
8133 
              'period' => 1,
8134 
              'port_id' => 0,
8135 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td/reg01_td',
8136 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_td',
8137 
              'timingConstraint' => 'none',
8138 
              'type' => 'UFix_32_0',
8139 
            },
8140 
            'direction' => 'in',
8141 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8142 
            'width' => 32,
8143 
          },
8144 
          'reg01_tv' => {
8145 
            'attributes' => {
8146 
              'bin_pt' => 0,
8147 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
8148 
              'is_floating_block' => 1,
8149 
              'is_gateway_port' => 1,
8150 
              'must_be_hdl_vector' => 1,
8151 
              'period' => 1,
8152 
              'port_id' => 0,
8153 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv/reg01_tv',
8154 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg01_tv',
8155 
              'timingConstraint' => 'none',
8156 
              'type' => 'Bool',
8157 
            },
8158 
            'direction' => 'in',
8159 
            'hdlType' => 'std_logic',
8160 
            'width' => 1,
8161 
          },
8162 
          'reg02_rd' => {
8163 
            'attributes' => {
8164 
              'bin_pt' => 0,
8165 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
8166 
              'is_floating_block' => 1,
8167 
              'is_gateway_port' => 1,
8168 
              'must_be_hdl_vector' => 1,
8169 
              'period' => 1,
8170 
              'port_id' => 0,
8171 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
8172 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
8173 
              'timingConstraint' => 'none',
8174 
              'type' => 'UFix_32_0',
8175 
            },
8176 
            'direction' => 'out',
8177 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8178 
            'width' => 32,
8179 
          },
8180 
          'reg02_rv' => {
8181 
            'attributes' => {
8182 
              'bin_pt' => 0,
8183 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
8184 
              'is_floating_block' => 1,
8185 
              'is_gateway_port' => 1,
8186 
              'must_be_hdl_vector' => 1,
8187 
              'period' => 1,
8188 
              'port_id' => 0,
8189 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
8190 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
8191 
              'timingConstraint' => 'none',
8192 
              'type' => 'UFix_1_0',
8193 
            },
8194 
            'direction' => 'out',
8195 
            'hdlType' => 'std_logic',
8196 
            'width' => 1,
8197 
          },
8198 
          'reg02_td' => {
8199 
            'attributes' => {
8200 
              'bin_pt' => 0,
8201 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
8202 
              'is_floating_block' => 1,
8203 
              'is_gateway_port' => 1,
8204 
              'must_be_hdl_vector' => 1,
8205 
              'period' => 1,
8206 
              'port_id' => 0,
8207 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td/reg02_td',
8208 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_td',
8209 
              'timingConstraint' => 'none',
8210 
              'type' => 'UFix_32_0',
8211 
            },
8212 
            'direction' => 'in',
8213 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8214 
            'width' => 32,
8215 
          },
8216 
          'reg02_tv' => {
8217 
            'attributes' => {
8218 
              'bin_pt' => 0,
8219 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
8220 
              'is_floating_block' => 1,
8221 
              'is_gateway_port' => 1,
8222 
              'must_be_hdl_vector' => 1,
8223 
              'period' => 1,
8224 
              'port_id' => 0,
8225 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
8226 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
8227 
              'timingConstraint' => 'none',
8228 
              'type' => 'Bool',
8229 
            },
8230 
            'direction' => 'in',
8231 
            'hdlType' => 'std_logic',
8232 
            'width' => 1,
8233 
          },
8234 
          'reg03_rd' => {
8235 
            'attributes' => {
8236 
              'bin_pt' => 0,
8237 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
8238 
              'is_floating_block' => 1,
8239 
              'is_gateway_port' => 1,
8240 
              'must_be_hdl_vector' => 1,
8241 
              'period' => 1,
8242 
              'port_id' => 0,
8243 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd/reg03_rd',
8244 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rd',
8245 
              'timingConstraint' => 'none',
8246 
              'type' => 'UFix_32_0',
8247 
            },
8248 
            'direction' => 'out',
8249 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8250 
            'width' => 32,
8251 
          },
8252 
          'reg03_rv' => {
8253 
            'attributes' => {
8254 
              'bin_pt' => 0,
8255 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
8256 
              'is_floating_block' => 1,
8257 
              'is_gateway_port' => 1,
8258 
              'must_be_hdl_vector' => 1,
8259 
              'period' => 1,
8260 
              'port_id' => 0,
8261 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv/reg03_rv',
8262 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_rv',
8263 
              'timingConstraint' => 'none',
8264 
              'type' => 'UFix_1_0',
8265 
            },
8266 
            'direction' => 'out',
8267 
            'hdlType' => 'std_logic',
8268 
            'width' => 1,
8269 
          },
8270 
          'reg03_td' => {
8271 
            'attributes' => {
8272 
              'bin_pt' => 0,
8273 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
8274 
              'is_floating_block' => 1,
8275 
              'is_gateway_port' => 1,
8276 
              'must_be_hdl_vector' => 1,
8277 
              'period' => 1,
8278 
              'port_id' => 0,
8279 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td/reg03_td',
8280 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_td',
8281 
              'timingConstraint' => 'none',
8282 
              'type' => 'UFix_32_0',
8283 
            },
8284 
            'direction' => 'in',
8285 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8286 
            'width' => 32,
8287 
          },
8288 
          'reg03_tv' => {
8289 
            'attributes' => {
8290 
              'bin_pt' => 0,
8291 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
8292 
              'is_floating_block' => 1,
8293 
              'is_gateway_port' => 1,
8294 
              'must_be_hdl_vector' => 1,
8295 
              'period' => 1,
8296 
              'port_id' => 0,
8297 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
8298 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv',
8299 
              'timingConstraint' => 'none',
8300 
              'type' => 'Bool',
8301 
            },
8302 
            'direction' => 'in',
8303 
            'hdlType' => 'std_logic',
8304 
            'width' => 1,
8305 
          },
8306 
          'reg04_rd' => {
8307 
            'attributes' => {
8308 
              'bin_pt' => 0,
8309 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
8310 
              'is_floating_block' => 1,
8311 
              'is_gateway_port' => 1,
8312 
              'must_be_hdl_vector' => 1,
8313 
              'period' => 1,
8314 
              'port_id' => 0,
8315 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
8316 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd',
8317 
              'timingConstraint' => 'none',
8318 
              'type' => 'UFix_32_0',
8319 
            },
8320 
            'direction' => 'out',
8321 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8322 
            'width' => 32,
8323 
          },
8324 
          'reg04_rv' => {
8325 
            'attributes' => {
8326 
              'bin_pt' => 0,
8327 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
8328 
              'is_floating_block' => 1,
8329 
              'is_gateway_port' => 1,
8330 
              'must_be_hdl_vector' => 1,
8331 
              'period' => 1,
8332 
              'port_id' => 0,
8333 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv/reg04_rv',
8334 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rv',
8335 
              'timingConstraint' => 'none',
8336 
              'type' => 'UFix_1_0',
8337 
            },
8338 
            'direction' => 'out',
8339 
            'hdlType' => 'std_logic',
8340 
            'width' => 1,
8341 
          },
8342 
          'reg04_td' => {
8343 
            'attributes' => {
8344 
              'bin_pt' => 0,
8345 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
8346 
              'is_floating_block' => 1,
8347 
              'is_gateway_port' => 1,
8348 
              'must_be_hdl_vector' => 1,
8349 
              'period' => 1,
8350 
              'port_id' => 0,
8351 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td/reg04_td',
8352 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_td',
8353 
              'timingConstraint' => 'none',
8354 
              'type' => 'UFix_32_0',
8355 
            },
8356 
            'direction' => 'in',
8357 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8358 
            'width' => 32,
8359 
          },
8360 
          'reg04_tv' => {
8361 
            'attributes' => {
8362 
              'bin_pt' => 0,
8363 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
8364 
              'is_floating_block' => 1,
8365 
              'is_gateway_port' => 1,
8366 
              'must_be_hdl_vector' => 1,
8367 
              'period' => 1,
8368 
              'port_id' => 0,
8369 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv/reg04_tv',
8370 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_tv',
8371 
              'timingConstraint' => 'none',
8372 
              'type' => 'Bool',
8373 
            },
8374 
            'direction' => 'in',
8375 
            'hdlType' => 'std_logic',
8376 
            'width' => 1,
8377 
          },
8378 
          'reg05_rd' => {
8379 
            'attributes' => {
8380 
              'bin_pt' => 0,
8381 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
8382 
              'is_floating_block' => 1,
8383 
              'is_gateway_port' => 1,
8384 
              'must_be_hdl_vector' => 1,
8385 
              'period' => 1,
8386 
              'port_id' => 0,
8387 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd/reg05_rd',
8388 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rd',
8389 
              'timingConstraint' => 'none',
8390 
              'type' => 'UFix_32_0',
8391 
            },
8392 
            'direction' => 'out',
8393 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8394 
            'width' => 32,
8395 
          },
8396 
          'reg05_rv' => {
8397 
            'attributes' => {
8398 
              'bin_pt' => 0,
8399 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
8400 
              'is_floating_block' => 1,
8401 
              'is_gateway_port' => 1,
8402 
              'must_be_hdl_vector' => 1,
8403 
              'period' => 1,
8404 
              'port_id' => 0,
8405 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv/reg05_rv',
8406 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_rv',
8407 
              'timingConstraint' => 'none',
8408 
              'type' => 'UFix_1_0',
8409 
            },
8410 
            'direction' => 'out',
8411 
            'hdlType' => 'std_logic',
8412 
            'width' => 1,
8413 
          },
8414 
          'reg05_td' => {
8415 
            'attributes' => {
8416 
              'bin_pt' => 0,
8417 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
8418 
              'is_floating_block' => 1,
8419 
              'is_gateway_port' => 1,
8420 
              'must_be_hdl_vector' => 1,
8421 
              'period' => 1,
8422 
              'port_id' => 0,
8423 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td/reg05_td',
8424 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_td',
8425 
              'timingConstraint' => 'none',
8426 
              'type' => 'UFix_32_0',
8427 
            },
8428 
            'direction' => 'in',
8429 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8430 
            'width' => 32,
8431 
          },
8432 
          'reg05_tv' => {
8433 
            'attributes' => {
8434 
              'bin_pt' => 0,
8435 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
8436 
              'is_floating_block' => 1,
8437 
              'is_gateway_port' => 1,
8438 
              'must_be_hdl_vector' => 1,
8439 
              'period' => 1,
8440 
              'port_id' => 0,
8441 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
8442 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv',
8443 
              'timingConstraint' => 'none',
8444 
              'type' => 'Bool',
8445 
            },
8446 
            'direction' => 'in',
8447 
            'hdlType' => 'std_logic',
8448 
            'width' => 1,
8449 
          },
8450 
          'reg06_rd' => {
8451 
            'attributes' => {
8452 
              'bin_pt' => 0,
8453 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
8454 
              'is_floating_block' => 1,
8455 
              'is_gateway_port' => 1,
8456 
              'must_be_hdl_vector' => 1,
8457 
              'period' => 1,
8458 
              'port_id' => 0,
8459 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd/reg06_rd',
8460 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rd',
8461 
              'timingConstraint' => 'none',
8462 
              'type' => 'UFix_32_0',
8463 
            },
8464 
            'direction' => 'out',
8465 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8466 
            'width' => 32,
8467 
          },
8468 
          'reg06_rv' => {
8469 
            'attributes' => {
8470 
              'bin_pt' => 0,
8471 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
8472 
              'is_floating_block' => 1,
8473 
              'is_gateway_port' => 1,
8474 
              'must_be_hdl_vector' => 1,
8475 
              'period' => 1,
8476 
              'port_id' => 0,
8477 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv/reg06_rv',
8478 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_rv',
8479 
              'timingConstraint' => 'none',
8480 
              'type' => 'UFix_1_0',
8481 
            },
8482 
            'direction' => 'out',
8483 
            'hdlType' => 'std_logic',
8484 
            'width' => 1,
8485 
          },
8486 
          'reg06_td' => {
8487 
            'attributes' => {
8488 
              'bin_pt' => 0,
8489 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
8490 
              'is_floating_block' => 1,
8491 
              'is_gateway_port' => 1,
8492 
              'must_be_hdl_vector' => 1,
8493 
              'period' => 1,
8494 
              'port_id' => 0,
8495 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td/reg06_td',
8496 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_td',
8497 
              'timingConstraint' => 'none',
8498 
              'type' => 'UFix_32_0',
8499 
            },
8500 
            'direction' => 'in',
8501 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8502 
            'width' => 32,
8503 
          },
8504 
          'reg06_tv' => {
8505 
            'attributes' => {
8506 
              'bin_pt' => 0,
8507 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
8508 
              'is_floating_block' => 1,
8509 
              'is_gateway_port' => 1,
8510 
              'must_be_hdl_vector' => 1,
8511 
              'period' => 1,
8512 
              'port_id' => 0,
8513 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv/reg06_tv',
8514 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg06_tv',
8515 
              'timingConstraint' => 'none',
8516 
              'type' => 'Bool',
8517 
            },
8518 
            'direction' => 'in',
8519 
            'hdlType' => 'std_logic',
8520 
            'width' => 1,
8521 
          },
8522 
          'reg07_rd' => {
8523 
            'attributes' => {
8524 
              'bin_pt' => 0,
8525 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
8526 
              'is_floating_block' => 1,
8527 
              'is_gateway_port' => 1,
8528 
              'must_be_hdl_vector' => 1,
8529 
              'period' => 1,
8530 
              'port_id' => 0,
8531 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
8532 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
8533 
              'timingConstraint' => 'none',
8534 
              'type' => 'UFix_32_0',
8535 
            },
8536 
            'direction' => 'out',
8537 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8538 
            'width' => 32,
8539 
          },
8540 
          'reg07_rv' => {
8541 
            'attributes' => {
8542 
              'bin_pt' => 0,
8543 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
8544 
              'is_floating_block' => 1,
8545 
              'is_gateway_port' => 1,
8546 
              'must_be_hdl_vector' => 1,
8547 
              'period' => 1,
8548 
              'port_id' => 0,
8549 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
8550 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
8551 
              'timingConstraint' => 'none',
8552 
              'type' => 'UFix_1_0',
8553 
            },
8554 
            'direction' => 'out',
8555 
            'hdlType' => 'std_logic',
8556 
            'width' => 1,
8557 
          },
8558 
          'reg07_td' => {
8559 
            'attributes' => {
8560 
              'bin_pt' => 0,
8561 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
8562 
              'is_floating_block' => 1,
8563 
              'is_gateway_port' => 1,
8564 
              'must_be_hdl_vector' => 1,
8565 
              'period' => 1,
8566 
              'port_id' => 0,
8567 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
8568 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
8569 
              'timingConstraint' => 'none',
8570 
              'type' => 'UFix_32_0',
8571 
            },
8572 
            'direction' => 'in',
8573 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8574 
            'width' => 32,
8575 
          },
8576 
          'reg07_tv' => {
8577 
            'attributes' => {
8578 
              'bin_pt' => 0,
8579 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
8580 
              'is_floating_block' => 1,
8581 
              'is_gateway_port' => 1,
8582 
              'must_be_hdl_vector' => 1,
8583 
              'period' => 1,
8584 
              'port_id' => 0,
8585 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
8586 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
8587 
              'timingConstraint' => 'none',
8588 
              'type' => 'Bool',
8589 
            },
8590 
            'direction' => 'in',
8591 
            'hdlType' => 'std_logic',
8592 
            'width' => 1,
8593 
          },
8594 
          'reg08_rd' => {
8595 
            'attributes' => {
8596 
              'bin_pt' => 0,
8597 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
8598 
              'is_floating_block' => 1,
8599 
              'is_gateway_port' => 1,
8600 
              'must_be_hdl_vector' => 1,
8601 
              'period' => 1,
8602 
              'port_id' => 0,
8603 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
8604 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
8605 
              'timingConstraint' => 'none',
8606 
              'type' => 'UFix_32_0',
8607 
            },
8608 
            'direction' => 'out',
8609 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8610 
            'width' => 32,
8611 
          },
8612 
          'reg08_rv' => {
8613 
            'attributes' => {
8614 
              'bin_pt' => 0,
8615 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
8616 
              'is_floating_block' => 1,
8617 
              'is_gateway_port' => 1,
8618 
              'must_be_hdl_vector' => 1,
8619 
              'period' => 1,
8620 
              'port_id' => 0,
8621 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
8622 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
8623 
              'timingConstraint' => 'none',
8624 
              'type' => 'UFix_1_0',
8625 
            },
8626 
            'direction' => 'out',
8627 
            'hdlType' => 'std_logic',
8628 
            'width' => 1,
8629 
          },
8630 
          'reg08_td' => {
8631 
            'attributes' => {
8632 
              'bin_pt' => 0,
8633 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
8634 
              'is_floating_block' => 1,
8635 
              'is_gateway_port' => 1,
8636 
              'must_be_hdl_vector' => 1,
8637 
              'period' => 1,
8638 
              'port_id' => 0,
8639 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
8640 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
8641 
              'timingConstraint' => 'none',
8642 
              'type' => 'UFix_32_0',
8643 
            },
8644 
            'direction' => 'in',
8645 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8646 
            'width' => 32,
8647 
          },
8648 
          'reg08_tv' => {
8649 
            'attributes' => {
8650 
              'bin_pt' => 0,
8651 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
8652 
              'is_floating_block' => 1,
8653 
              'is_gateway_port' => 1,
8654 
              'must_be_hdl_vector' => 1,
8655 
              'period' => 1,
8656 
              'port_id' => 0,
8657 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
8658 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
8659 
              'timingConstraint' => 'none',
8660 
              'type' => 'Bool',
8661 
            },
8662 
            'direction' => 'in',
8663 
            'hdlType' => 'std_logic',
8664 
            'width' => 1,
8665 
          },
8666 
          'reg09_rd' => {
8667 
            'attributes' => {
8668 
              'bin_pt' => 0,
8669 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
8670 
              'is_floating_block' => 1,
8671 
              'is_gateway_port' => 1,
8672 
              'must_be_hdl_vector' => 1,
8673 
              'period' => 1,
8674 
              'port_id' => 0,
8675 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
8676 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
8677 
              'timingConstraint' => 'none',
8678 
              'type' => 'UFix_32_0',
8679 
            },
8680 
            'direction' => 'out',
8681 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8682 
            'width' => 32,
8683 
          },
8684 
          'reg09_rv' => {
8685 
            'attributes' => {
8686 
              'bin_pt' => 0,
8687 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
8688 
              'is_floating_block' => 1,
8689 
              'is_gateway_port' => 1,
8690 
              'must_be_hdl_vector' => 1,
8691 
              'period' => 1,
8692 
              'port_id' => 0,
8693 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
8694 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
8695 
              'timingConstraint' => 'none',
8696 
              'type' => 'UFix_1_0',
8697 
            },
8698 
            'direction' => 'out',
8699 
            'hdlType' => 'std_logic',
8700 
            'width' => 1,
8701 
          },
8702 
          'reg09_td' => {
8703 
            'attributes' => {
8704 
              'bin_pt' => 0,
8705 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
8706 
              'is_floating_block' => 1,
8707 
              'is_gateway_port' => 1,
8708 
              'must_be_hdl_vector' => 1,
8709 
              'period' => 1,
8710 
              'port_id' => 0,
8711 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
8712 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
8713 
              'timingConstraint' => 'none',
8714 
              'type' => 'UFix_32_0',
8715 
            },
8716 
            'direction' => 'in',
8717 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8718 
            'width' => 32,
8719 
          },
8720 
          'reg09_tv' => {
8721 
            'attributes' => {
8722 
              'bin_pt' => 0,
8723 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
8724 
              'is_floating_block' => 1,
8725 
              'is_gateway_port' => 1,
8726 
              'must_be_hdl_vector' => 1,
8727 
              'period' => 1,
8728 
              'port_id' => 0,
8729 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
8730 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
8731 
              'timingConstraint' => 'none',
8732 
              'type' => 'Bool',
8733 
            },
8734 
            'direction' => 'in',
8735 
            'hdlType' => 'std_logic',
8736 
            'width' => 1,
8737 
          },
8738 
          'reg10_rd' => {
8739 
            'attributes' => {
8740 
              'bin_pt' => 0,
8741 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
8742 
              'is_floating_block' => 1,
8743 
              'is_gateway_port' => 1,
8744 
              'must_be_hdl_vector' => 1,
8745 
              'period' => 1,
8746 
              'port_id' => 0,
8747 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
8748 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
8749 
              'timingConstraint' => 'none',
8750 
              'type' => 'UFix_32_0',
8751 
            },
8752 
            'direction' => 'out',
8753 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8754 
            'width' => 32,
8755 
          },
8756 
          'reg10_rv' => {
8757 
            'attributes' => {
8758 
              'bin_pt' => 0,
8759 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
8760 
              'is_floating_block' => 1,
8761 
              'is_gateway_port' => 1,
8762 
              'must_be_hdl_vector' => 1,
8763 
              'period' => 1,
8764 
              'port_id' => 0,
8765 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
8766 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
8767 
              'timingConstraint' => 'none',
8768 
              'type' => 'UFix_1_0',
8769 
            },
8770 
            'direction' => 'out',
8771 
            'hdlType' => 'std_logic',
8772 
            'width' => 1,
8773 
          },
8774 
          'reg10_td' => {
8775 
            'attributes' => {
8776 
              'bin_pt' => 0,
8777 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
8778 
              'is_floating_block' => 1,
8779 
              'is_gateway_port' => 1,
8780 
              'must_be_hdl_vector' => 1,
8781 
              'period' => 1,
8782 
              'port_id' => 0,
8783 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td/reg10_td',
8784 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
8785 
              'timingConstraint' => 'none',
8786 
              'type' => 'UFix_32_0',
8787 
            },
8788 
            'direction' => 'in',
8789 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8790 
            'width' => 32,
8791 
          },
8792 
          'reg10_tv' => {
8793 
            'attributes' => {
8794 
              'bin_pt' => 0,
8795 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
8796 
              'is_floating_block' => 1,
8797 
              'is_gateway_port' => 1,
8798 
              'must_be_hdl_vector' => 1,
8799 
              'period' => 1,
8800 
              'port_id' => 0,
8801 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
8802 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
8803 
              'timingConstraint' => 'none',
8804 
              'type' => 'Bool',
8805 
            },
8806 
            'direction' => 'in',
8807 
            'hdlType' => 'std_logic',
8808 
            'width' => 1,
8809 
          },
8810 
          'reg11_rd' => {
8811 
            'attributes' => {
8812 
              'bin_pt' => 0,
8813 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
8814 
              'is_floating_block' => 1,
8815 
              'is_gateway_port' => 1,
8816 
              'must_be_hdl_vector' => 1,
8817 
              'period' => 1,
8818 
              'port_id' => 0,
8819 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
8820 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
8821 
              'timingConstraint' => 'none',
8822 
              'type' => 'UFix_32_0',
8823 
            },
8824 
            'direction' => 'out',
8825 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8826 
            'width' => 32,
8827 
          },
8828 
          'reg11_rv' => {
8829 
            'attributes' => {
8830 
              'bin_pt' => 0,
8831 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
8832 
              'is_floating_block' => 1,
8833 
              'is_gateway_port' => 1,
8834 
              'must_be_hdl_vector' => 1,
8835 
              'period' => 1,
8836 
              'port_id' => 0,
8837 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv/reg11_rv',
8838 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
8839 
              'timingConstraint' => 'none',
8840 
              'type' => 'UFix_1_0',
8841 
            },
8842 
            'direction' => 'out',
8843 
            'hdlType' => 'std_logic',
8844 
            'width' => 1,
8845 
          },
8846 
          'reg11_td' => {
8847 
            'attributes' => {
8848 
              'bin_pt' => 0,
8849 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
8850 
              'is_floating_block' => 1,
8851 
              'is_gateway_port' => 1,
8852 
              'must_be_hdl_vector' => 1,
8853 
              'period' => 1,
8854 
              'port_id' => 0,
8855 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td/reg11_td',
8856 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
8857 
              'timingConstraint' => 'none',
8858 
              'type' => 'UFix_32_0',
8859 
            },
8860 
            'direction' => 'in',
8861 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8862 
            'width' => 32,
8863 
          },
8864 
          'reg11_tv' => {
8865 
            'attributes' => {
8866 
              'bin_pt' => 0,
8867 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
8868 
              'is_floating_block' => 1,
8869 
              'is_gateway_port' => 1,
8870 
              'must_be_hdl_vector' => 1,
8871 
              'period' => 1,
8872 
              'port_id' => 0,
8873 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv/reg11_tv',
8874 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
8875 
              'timingConstraint' => 'none',
8876 
              'type' => 'Bool',
8877 
            },
8878 
            'direction' => 'in',
8879 
            'hdlType' => 'std_logic',
8880 
            'width' => 1,
8881 
          },
8882 
          'reg12_rd' => {
8883 
            'attributes' => {
8884 
              'bin_pt' => 0,
8885 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
8886 
              'is_floating_block' => 1,
8887 
              'is_gateway_port' => 1,
8888 
              'must_be_hdl_vector' => 1,
8889 
              'period' => 1,
8890 
              'port_id' => 0,
8891 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd/reg12_rd',
8892 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
8893 
              'timingConstraint' => 'none',
8894 
              'type' => 'UFix_32_0',
8895 
            },
8896 
            'direction' => 'out',
8897 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8898 
            'width' => 32,
8899 
          },
8900 
          'reg12_rv' => {
8901 
            'attributes' => {
8902 
              'bin_pt' => 0,
8903 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
8904 
              'is_floating_block' => 1,
8905 
              'is_gateway_port' => 1,
8906 
              'must_be_hdl_vector' => 1,
8907 
              'period' => 1,
8908 
              'port_id' => 0,
8909 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv/reg12_rv',
8910 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
8911 
              'timingConstraint' => 'none',
8912 
              'type' => 'UFix_1_0',
8913 
            },
8914 
            'direction' => 'out',
8915 
            'hdlType' => 'std_logic',
8916 
            'width' => 1,
8917 
          },
8918 
          'reg12_td' => {
8919 
            'attributes' => {
8920 
              'bin_pt' => 0,
8921 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
8922 
              'is_floating_block' => 1,
8923 
              'is_gateway_port' => 1,
8924 
              'must_be_hdl_vector' => 1,
8925 
              'period' => 1,
8926 
              'port_id' => 0,
8927 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td/reg12_td',
8928 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td',
8929 
              'timingConstraint' => 'none',
8930 
              'type' => 'UFix_32_0',
8931 
            },
8932 
            'direction' => 'in',
8933 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8934 
            'width' => 32,
8935 
          },
8936 
          'reg12_tv' => {
8937 
            'attributes' => {
8938 
              'bin_pt' => 0,
8939 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
8940 
              'is_floating_block' => 1,
8941 
              'is_gateway_port' => 1,
8942 
              'must_be_hdl_vector' => 1,
8943 
              'period' => 1,
8944 
              'port_id' => 0,
8945 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv/reg12_tv',
8946 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
8947 
              'timingConstraint' => 'none',
8948 
              'type' => 'Bool',
8949 
            },
8950 
            'direction' => 'in',
8951 
            'hdlType' => 'std_logic',
8952 
            'width' => 1,
8953 
          },
8954 
          'reg13_rd' => {
8955 
            'attributes' => {
8956 
              'bin_pt' => 0,
8957 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
8958 
              'is_floating_block' => 1,
8959 
              'is_gateway_port' => 1,
8960 
              'must_be_hdl_vector' => 1,
8961 
              'period' => 1,
8962 
              'port_id' => 0,
8963 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd/reg13_rd',
8964 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
8965 
              'timingConstraint' => 'none',
8966 
              'type' => 'UFix_32_0',
8967 
            },
8968 
            'direction' => 'out',
8969 
            'hdlType' => 'std_logic_vector(31 downto 0)',
8970 
            'width' => 32,
8971 
          },
8972 
          'reg13_rv' => {
8973 
            'attributes' => {
8974 
              'bin_pt' => 0,
8975 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
8976 
              'is_floating_block' => 1,
8977 
              'is_gateway_port' => 1,
8978 
              'must_be_hdl_vector' => 1,
8979 
              'period' => 1,
8980 
              'port_id' => 0,
8981 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
8982 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
8983 
              'timingConstraint' => 'none',
8984 
              'type' => 'UFix_1_0',
8985 
            },
8986 
            'direction' => 'out',
8987 
            'hdlType' => 'std_logic',
8988 
            'width' => 1,
8989 
          },
8990 
          'reg13_td' => {
8991 
            'attributes' => {
8992 
              'bin_pt' => 0,
8993 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
8994 
              'is_floating_block' => 1,
8995 
              'is_gateway_port' => 1,
8996 
              'must_be_hdl_vector' => 1,
8997 
              'period' => 1,
8998 
              'port_id' => 0,
8999 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
9000 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
9001 
              'timingConstraint' => 'none',
9002 
              'type' => 'UFix_32_0',
9003 
            },
9004 
            'direction' => 'in',
9005 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9006 
            'width' => 32,
9007 
          },
9008 
          'reg13_tv' => {
9009 
            'attributes' => {
9010 
              'bin_pt' => 0,
9011 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
9012 
              'is_floating_block' => 1,
9013 
              'is_gateway_port' => 1,
9014 
              'must_be_hdl_vector' => 1,
9015 
              'period' => 1,
9016 
              'port_id' => 0,
9017 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
9018 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
9019 
              'timingConstraint' => 'none',
9020 
              'type' => 'Bool',
9021 
            },
9022 
            'direction' => 'in',
9023 
            'hdlType' => 'std_logic',
9024 
            'width' => 1,
9025 
          },
9026 
          'reg14_rd' => {
9027 
            'attributes' => {
9028 
              'bin_pt' => 0,
9029 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
9030 
              'is_floating_block' => 1,
9031 
              'is_gateway_port' => 1,
9032 
              'must_be_hdl_vector' => 1,
9033 
              'period' => 1,
9034 
              'port_id' => 0,
9035 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
9036 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
9037 
              'timingConstraint' => 'none',
9038 
              'type' => 'UFix_32_0',
9039 
            },
9040 
            'direction' => 'out',
9041 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9042 
            'width' => 32,
9043 
          },
9044 
          'reg14_rv' => {
9045 
            'attributes' => {
9046 
              'bin_pt' => 0,
9047 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
9048 
              'is_floating_block' => 1,
9049 
              'is_gateway_port' => 1,
9050 
              'must_be_hdl_vector' => 1,
9051 
              'period' => 1,
9052 
              'port_id' => 0,
9053 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
9054 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
9055 
              'timingConstraint' => 'none',
9056 
              'type' => 'UFix_1_0',
9057 
            },
9058 
            'direction' => 'out',
9059 
            'hdlType' => 'std_logic',
9060 
            'width' => 1,
9061 
          },
9062 
          'reg14_td' => {
9063 
            'attributes' => {
9064 
              'bin_pt' => 0,
9065 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
9066 
              'is_floating_block' => 1,
9067 
              'is_gateway_port' => 1,
9068 
              'must_be_hdl_vector' => 1,
9069 
              'period' => 1,
9070 
              'port_id' => 0,
9071 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
9072 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
9073 
              'timingConstraint' => 'none',
9074 
              'type' => 'UFix_32_0',
9075 
            },
9076 
            'direction' => 'in',
9077 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9078 
            'width' => 32,
9079 
          },
9080 
          'reg14_tv' => {
9081 
            'attributes' => {
9082 
              'bin_pt' => 0,
9083 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
9084 
              'is_floating_block' => 1,
9085 
              'is_gateway_port' => 1,
9086 
              'must_be_hdl_vector' => 1,
9087 
              'period' => 1,
9088 
              'port_id' => 0,
9089 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
9090 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
9091 
              'timingConstraint' => 'none',
9092 
              'type' => 'Bool',
9093 
            },
9094 
            'direction' => 'in',
9095 
            'hdlType' => 'std_logic',
9096 
            'width' => 1,
9097 
          },
9098 
          'to_register10_ce' => {
9099 
            'attributes' => {
9100 
              'domain' => '',
9101 
              'group' => 1,
9102 
              'isCe' => 1,
9103 
              'is_floating_block' => 1,
9104 
              'period' => 1,
9105 
              'type' => 'logic',
9106 
            },
9107 
            'direction' => 'out',
9108 
            'hdlType' => 'std_logic',
9109 
            'width' => 1,
9110 
          },
9111 
          'to_register10_clk' => {
9112 
            'attributes' => {
9113 
              'domain' => '',
9114 
              'group' => 1,
9115 
              'isClk' => 1,
9116 
              'is_floating_block' => 1,
9117 
              'period' => 1,
9118 
              'type' => 'logic',
9119 
            },
9120 
            'direction' => 'out',
9121 
            'hdlType' => 'std_logic',
9122 
            'width' => 1,
9123 
          },
9124 
          'to_register10_clr' => {
9125 
            'attributes' => {
9126 
              'domain' => '',
9127 
              'group' => 1,
9128 
              'isClr' => 1,
9129 
              'is_floating_block' => 1,
9130 
              'period' => 1,
9131 
              'type' => 'logic',
9132 
              'valid_bit_used' => 0,
9133 
            },
9134 
            'direction' => 'out',
9135 
            'hdlType' => 'std_logic',
9136 
            'width' => 1,
9137 
          },
9138 
          'to_register10_data_in' => {
9139 
            'attributes' => {
9140 
              'bin_pt' => 0,
9141 
              'is_floating_block' => 1,
9142 
              'must_be_hdl_vector' => 1,
9143 
              'period' => 1,
9144 
              'port_id' => 0,
9145 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/data_in',
9146 
              'type' => 'Bool',
9147 
            },
9148 
            'direction' => 'out',
9149 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9150 
            'width' => 1,
9151 
          },
9152 
          'to_register10_dout' => {
9153 
            'attributes' => {
9154 
              'bin_pt' => 0,
9155 
              'is_floating_block' => 1,
9156 
              'must_be_hdl_vector' => 1,
9157 
              'period' => 1,
9158 
              'port_id' => 0,
9159 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/dout',
9160 
              'type' => 'Bool',
9161 
            },
9162 
            'direction' => 'in',
9163 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9164 
            'width' => 1,
9165 
          },
9166 
          'to_register10_en' => {
9167 
            'attributes' => {
9168 
              'bin_pt' => 0,
9169 
              'is_floating_block' => 1,
9170 
              'must_be_hdl_vector' => 1,
9171 
              'period' => 1,
9172 
              'port_id' => 1,
9173 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/en',
9174 
              'type' => 'Bool',
9175 
            },
9176 
            'direction' => 'out',
9177 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9178 
            'width' => 1,
9179 
          },
9180 
          'to_register11_ce' => {
9181 
            'attributes' => {
9182 
              'domain' => '',
9183 
              'group' => 1,
9184 
              'isCe' => 1,
9185 
              'is_floating_block' => 1,
9186 
              'period' => 1,
9187 
              'type' => 'logic',
9188 
            },
9189 
            'direction' => 'out',
9190 
            'hdlType' => 'std_logic',
9191 
            'width' => 1,
9192 
          },
9193 
          'to_register11_clk' => {
9194 
            'attributes' => {
9195 
              'domain' => '',
9196 
              'group' => 1,
9197 
              'isClk' => 1,
9198 
              'is_floating_block' => 1,
9199 
              'period' => 1,
9200 
              'type' => 'logic',
9201 
            },
9202 
            'direction' => 'out',
9203 
            'hdlType' => 'std_logic',
9204 
            'width' => 1,
9205 
          },
9206 
          'to_register11_clr' => {
9207 
            'attributes' => {
9208 
              'domain' => '',
9209 
              'group' => 1,
9210 
              'isClr' => 1,
9211 
              'is_floating_block' => 1,
9212 
              'period' => 1,
9213 
              'type' => 'logic',
9214 
              'valid_bit_used' => 0,
9215 
            },
9216 
            'direction' => 'out',
9217 
            'hdlType' => 'std_logic',
9218 
            'width' => 1,
9219 
          },
9220 
          'to_register11_data_in' => {
9221 
            'attributes' => {
9222 
              'bin_pt' => 0,
9223 
              'is_floating_block' => 1,
9224 
              'must_be_hdl_vector' => 1,
9225 
              'period' => 1,
9226 
              'port_id' => 0,
9227 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/data_in',
9228 
              'type' => 'UFix_32_0',
9229 
            },
9230 
            'direction' => 'out',
9231 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9232 
            'width' => 32,
9233 
          },
9234 
          'to_register11_dout' => {
9235 
            'attributes' => {
9236 
              'bin_pt' => 0,
9237 
              'is_floating_block' => 1,
9238 
              'must_be_hdl_vector' => 1,
9239 
              'period' => 1,
9240 
              'port_id' => 0,
9241 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/dout',
9242 
              'type' => 'UFix_32_0',
9243 
            },
9244 
            'direction' => 'in',
9245 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9246 
            'width' => 32,
9247 
          },
9248 
          'to_register11_en' => {
9249 
            'attributes' => {
9250 
              'bin_pt' => 0,
9251 
              'is_floating_block' => 1,
9252 
              'must_be_hdl_vector' => 1,
9253 
              'period' => 1,
9254 
              'port_id' => 1,
9255 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/en',
9256 
              'type' => 'Bool',
9257 
            },
9258 
            'direction' => 'out',
9259 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9260 
            'width' => 1,
9261 
          },
9262 
          'to_register12_ce' => {
9263 
            'attributes' => {
9264 
              'domain' => '',
9265 
              'group' => 1,
9266 
              'isCe' => 1,
9267 
              'is_floating_block' => 1,
9268 
              'period' => 1,
9269 
              'type' => 'logic',
9270 
            },
9271 
            'direction' => 'out',
9272 
            'hdlType' => 'std_logic',
9273 
            'width' => 1,
9274 
          },
9275 
          'to_register12_clk' => {
9276 
            'attributes' => {
9277 
              'domain' => '',
9278 
              'group' => 1,
9279 
              'isClk' => 1,
9280 
              'is_floating_block' => 1,
9281 
              'period' => 1,
9282 
              'type' => 'logic',
9283 
            },
9284 
            'direction' => 'out',
9285 
            'hdlType' => 'std_logic',
9286 
            'width' => 1,
9287 
          },
9288 
          'to_register12_clr' => {
9289 
            'attributes' => {
9290 
              'domain' => '',
9291 
              'group' => 1,
9292 
              'isClr' => 1,
9293 
              'is_floating_block' => 1,
9294 
              'period' => 1,
9295 
              'type' => 'logic',
9296 
              'valid_bit_used' => 0,
9297 
            },
9298 
            'direction' => 'out',
9299 
            'hdlType' => 'std_logic',
9300 
            'width' => 1,
9301 
          },
9302 
          'to_register12_data_in' => {
9303 
            'attributes' => {
9304 
              'bin_pt' => 0,
9305 
              'is_floating_block' => 1,
9306 
              'must_be_hdl_vector' => 1,
9307 
              'period' => 1,
9308 
              'port_id' => 0,
9309 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/data_in',
9310 
              'type' => 'Bool',
9311 
            },
9312 
            'direction' => 'out',
9313 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9314 
            'width' => 1,
9315 
          },
9316 
          'to_register12_dout' => {
9317 
            'attributes' => {
9318 
              'bin_pt' => 0,
9319 
              'is_floating_block' => 1,
9320 
              'must_be_hdl_vector' => 1,
9321 
              'period' => 1,
9322 
              'port_id' => 0,
9323 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/dout',
9324 
              'type' => 'Bool',
9325 
            },
9326 
            'direction' => 'in',
9327 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9328 
            'width' => 1,
9329 
          },
9330 
          'to_register12_en' => {
9331 
            'attributes' => {
9332 
              'bin_pt' => 0,
9333 
              'is_floating_block' => 1,
9334 
              'must_be_hdl_vector' => 1,
9335 
              'period' => 1,
9336 
              'port_id' => 1,
9337 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/en',
9338 
              'type' => 'Bool',
9339 
            },
9340 
            'direction' => 'out',
9341 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9342 
            'width' => 1,
9343 
          },
9344 
          'to_register13_ce' => {
9345 
            'attributes' => {
9346 
              'domain' => '',
9347 
              'group' => 1,
9348 
              'isCe' => 1,
9349 
              'is_floating_block' => 1,
9350 
              'period' => 1,
9351 
              'type' => 'logic',
9352 
            },
9353 
            'direction' => 'out',
9354 
            'hdlType' => 'std_logic',
9355 
            'width' => 1,
9356 
          },
9357 
          'to_register13_clk' => {
9358 
            'attributes' => {
9359 
              'domain' => '',
9360 
              'group' => 1,
9361 
              'isClk' => 1,
9362 
              'is_floating_block' => 1,
9363 
              'period' => 1,
9364 
              'type' => 'logic',
9365 
            },
9366 
            'direction' => 'out',
9367 
            'hdlType' => 'std_logic',
9368 
            'width' => 1,
9369 
          },
9370 
          'to_register13_clr' => {
9371 
            'attributes' => {
9372 
              'domain' => '',
9373 
              'group' => 1,
9374 
              'isClr' => 1,
9375 
              'is_floating_block' => 1,
9376 
              'period' => 1,
9377 
              'type' => 'logic',
9378 
              'valid_bit_used' => 0,
9379 
            },
9380 
            'direction' => 'out',
9381 
            'hdlType' => 'std_logic',
9382 
            'width' => 1,
9383 
          },
9384 
          'to_register13_data_in' => {
9385 
            'attributes' => {
9386 
              'bin_pt' => 0,
9387 
              'is_floating_block' => 1,
9388 
              'must_be_hdl_vector' => 1,
9389 
              'period' => 1,
9390 
              'port_id' => 0,
9391 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/data_in',
9392 
              'type' => 'UFix_32_0',
9393 
            },
9394 
            'direction' => 'out',
9395 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9396 
            'width' => 32,
9397 
          },
9398 
          'to_register13_dout' => {
9399 
            'attributes' => {
9400 
              'bin_pt' => 0,
9401 
              'is_floating_block' => 1,
9402 
              'must_be_hdl_vector' => 1,
9403 
              'period' => 1,
9404 
              'port_id' => 0,
9405 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/dout',
9406 
              'type' => 'UFix_32_0',
9407 
            },
9408 
            'direction' => 'in',
9409 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9410 
            'width' => 32,
9411 
          },
9412 
          'to_register13_en' => {
9413 
            'attributes' => {
9414 
              'bin_pt' => 0,
9415 
              'is_floating_block' => 1,
9416 
              'must_be_hdl_vector' => 1,
9417 
              'period' => 1,
9418 
              'port_id' => 1,
9419 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/en',
9420 
              'type' => 'Bool',
9421 
            },
9422 
            'direction' => 'out',
9423 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9424 
            'width' => 1,
9425 
          },
9426 
          'to_register14_ce' => {
9427 
            'attributes' => {
9428 
              'domain' => '',
9429 
              'group' => 1,
9430 
              'isCe' => 1,
9431 
              'is_floating_block' => 1,
9432 
              'period' => 1,
9433 
              'type' => 'logic',
9434 
            },
9435 
            'direction' => 'out',
9436 
            'hdlType' => 'std_logic',
9437 
            'width' => 1,
9438 
          },
9439 
          'to_register14_clk' => {
9440 
            'attributes' => {
9441 
              'domain' => '',
9442 
              'group' => 1,
9443 
              'isClk' => 1,
9444 
              'is_floating_block' => 1,
9445 
              'period' => 1,
9446 
              'type' => 'logic',
9447 
            },
9448 
            'direction' => 'out',
9449 
            'hdlType' => 'std_logic',
9450 
            'width' => 1,
9451 
          },
9452 
          'to_register14_clr' => {
9453 
            'attributes' => {
9454 
              'domain' => '',
9455 
              'group' => 1,
9456 
              'isClr' => 1,
9457 
              'is_floating_block' => 1,
9458 
              'period' => 1,
9459 
              'type' => 'logic',
9460 
              'valid_bit_used' => 0,
9461 
            },
9462 
            'direction' => 'out',
9463 
            'hdlType' => 'std_logic',
9464 
            'width' => 1,
9465 
          },
9466 
          'to_register14_data_in' => {
9467 
            'attributes' => {
9468 
              'bin_pt' => 0,
9469 
              'is_floating_block' => 1,
9470 
              'must_be_hdl_vector' => 1,
9471 
              'period' => 1,
9472 
              'port_id' => 0,
9473 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/data_in',
9474 
              'type' => 'Bool',
9475 
            },
9476 
            'direction' => 'out',
9477 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9478 
            'width' => 1,
9479 
          },
9480 
          'to_register14_dout' => {
9481 
            'attributes' => {
9482 
              'bin_pt' => 0,
9483 
              'is_floating_block' => 1,
9484 
              'must_be_hdl_vector' => 1,
9485 
              'period' => 1,
9486 
              'port_id' => 0,
9487 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/dout',
9488 
              'type' => 'Bool',
9489 
            },
9490 
            'direction' => 'in',
9491 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9492 
            'width' => 1,
9493 
          },
9494 
          'to_register14_en' => {
9495 
            'attributes' => {
9496 
              'bin_pt' => 0,
9497 
              'is_floating_block' => 1,
9498 
              'must_be_hdl_vector' => 1,
9499 
              'period' => 1,
9500 
              'port_id' => 1,
9501 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/en',
9502 
              'type' => 'Bool',
9503 
            },
9504 
            'direction' => 'out',
9505 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9506 
            'width' => 1,
9507 
          },
9508 
          'to_register15_ce' => {
9509 
            'attributes' => {
9510 
              'domain' => '',
9511 
              'group' => 1,
9512 
              'isCe' => 1,
9513 
              'is_floating_block' => 1,
9514 
              'period' => 1,
9515 
              'type' => 'logic',
9516 
            },
9517 
            'direction' => 'out',
9518 
            'hdlType' => 'std_logic',
9519 
            'width' => 1,
9520 
          },
9521 
          'to_register15_clk' => {
9522 
            'attributes' => {
9523 
              'domain' => '',
9524 
              'group' => 1,
9525 
              'isClk' => 1,
9526 
              'is_floating_block' => 1,
9527 
              'period' => 1,
9528 
              'type' => 'logic',
9529 
            },
9530 
            'direction' => 'out',
9531 
            'hdlType' => 'std_logic',
9532 
            'width' => 1,
9533 
          },
9534 
          'to_register15_clr' => {
9535 
            'attributes' => {
9536 
              'domain' => '',
9537 
              'group' => 1,
9538 
              'isClr' => 1,
9539 
              'is_floating_block' => 1,
9540 
              'period' => 1,
9541 
              'type' => 'logic',
9542 
              'valid_bit_used' => 0,
9543 
            },
9544 
            'direction' => 'out',
9545 
            'hdlType' => 'std_logic',
9546 
            'width' => 1,
9547 
          },
9548 
          'to_register15_data_in' => {
9549 
            'attributes' => {
9550 
              'bin_pt' => 0,
9551 
              'is_floating_block' => 1,
9552 
              'must_be_hdl_vector' => 1,
9553 
              'period' => 1,
9554 
              'port_id' => 0,
9555 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/data_in',
9556 
              'type' => 'UFix_32_0',
9557 
            },
9558 
            'direction' => 'out',
9559 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9560 
            'width' => 32,
9561 
          },
9562 
          'to_register15_dout' => {
9563 
            'attributes' => {
9564 
              'bin_pt' => 0,
9565 
              'is_floating_block' => 1,
9566 
              'must_be_hdl_vector' => 1,
9567 
              'period' => 1,
9568 
              'port_id' => 0,
9569 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/dout',
9570 
              'type' => 'UFix_32_0',
9571 
            },
9572 
            'direction' => 'in',
9573 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9574 
            'width' => 32,
9575 
          },
9576 
          'to_register15_en' => {
9577 
            'attributes' => {
9578 
              'bin_pt' => 0,
9579 
              'is_floating_block' => 1,
9580 
              'must_be_hdl_vector' => 1,
9581 
              'period' => 1,
9582 
              'port_id' => 1,
9583 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/en',
9584 
              'type' => 'Bool',
9585 
            },
9586 
            'direction' => 'out',
9587 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9588 
            'width' => 1,
9589 
          },
9590 
          'to_register16_ce' => {
9591 
            'attributes' => {
9592 
              'domain' => '',
9593 
              'group' => 1,
9594 
              'isCe' => 1,
9595 
              'is_floating_block' => 1,
9596 
              'period' => 1,
9597 
              'type' => 'logic',
9598 
            },
9599 
            'direction' => 'out',
9600 
            'hdlType' => 'std_logic',
9601 
            'width' => 1,
9602 
          },
9603 
          'to_register16_clk' => {
9604 
            'attributes' => {
9605 
              'domain' => '',
9606 
              'group' => 1,
9607 
              'isClk' => 1,
9608 
              'is_floating_block' => 1,
9609 
              'period' => 1,
9610 
              'type' => 'logic',
9611 
            },
9612 
            'direction' => 'out',
9613 
            'hdlType' => 'std_logic',
9614 
            'width' => 1,
9615 
          },
9616 
          'to_register16_clr' => {
9617 
            'attributes' => {
9618 
              'domain' => '',
9619 
              'group' => 1,
9620 
              'isClr' => 1,
9621 
              'is_floating_block' => 1,
9622 
              'period' => 1,
9623 
              'type' => 'logic',
9624 
              'valid_bit_used' => 0,
9625 
            },
9626 
            'direction' => 'out',
9627 
            'hdlType' => 'std_logic',
9628 
            'width' => 1,
9629 
          },
9630 
          'to_register16_data_in' => {
9631 
            'attributes' => {
9632 
              'bin_pt' => 0,
9633 
              'is_floating_block' => 1,
9634 
              'must_be_hdl_vector' => 1,
9635 
              'period' => 1,
9636 
              'port_id' => 0,
9637 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/data_in',
9638 
              'type' => 'Bool',
9639 
            },
9640 
            'direction' => 'out',
9641 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9642 
            'width' => 1,
9643 
          },
9644 
          'to_register16_dout' => {
9645 
            'attributes' => {
9646 
              'bin_pt' => 0,
9647 
              'is_floating_block' => 1,
9648 
              'must_be_hdl_vector' => 1,
9649 
              'period' => 1,
9650 
              'port_id' => 0,
9651 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/dout',
9652 
              'type' => 'Bool',
9653 
            },
9654 
            'direction' => 'in',
9655 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9656 
            'width' => 1,
9657 
          },
9658 
          'to_register16_en' => {
9659 
            'attributes' => {
9660 
              'bin_pt' => 0,
9661 
              'is_floating_block' => 1,
9662 
              'must_be_hdl_vector' => 1,
9663 
              'period' => 1,
9664 
              'port_id' => 1,
9665 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/en',
9666 
              'type' => 'Bool',
9667 
            },
9668 
            'direction' => 'out',
9669 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9670 
            'width' => 1,
9671 
          },
9672 
          'to_register17_ce' => {
9673 
            'attributes' => {
9674 
              'domain' => '',
9675 
              'group' => 1,
9676 
              'isCe' => 1,
9677 
              'is_floating_block' => 1,
9678 
              'period' => 1,
9679 
              'type' => 'logic',
9680 
            },
9681 
            'direction' => 'out',
9682 
            'hdlType' => 'std_logic',
9683 
            'width' => 1,
9684 
          },
9685 
          'to_register17_clk' => {
9686 
            'attributes' => {
9687 
              'domain' => '',
9688 
              'group' => 1,
9689 
              'isClk' => 1,
9690 
              'is_floating_block' => 1,
9691 
              'period' => 1,
9692 
              'type' => 'logic',
9693 
            },
9694 
            'direction' => 'out',
9695 
            'hdlType' => 'std_logic',
9696 
            'width' => 1,
9697 
          },
9698 
          'to_register17_clr' => {
9699 
            'attributes' => {
9700 
              'domain' => '',
9701 
              'group' => 1,
9702 
              'isClr' => 1,
9703 
              'is_floating_block' => 1,
9704 
              'period' => 1,
9705 
              'type' => 'logic',
9706 
              'valid_bit_used' => 0,
9707 
            },
9708 
            'direction' => 'out',
9709 
            'hdlType' => 'std_logic',
9710 
            'width' => 1,
9711 
          },
9712 
          'to_register17_data_in' => {
9713 
            'attributes' => {
9714 
              'bin_pt' => 0,
9715 
              'is_floating_block' => 1,
9716 
              'must_be_hdl_vector' => 1,
9717 
              'period' => 1,
9718 
              'port_id' => 0,
9719 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/data_in',
9720 
              'type' => 'UFix_32_0',
9721 
            },
9722 
            'direction' => 'out',
9723 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9724 
            'width' => 32,
9725 
          },
9726 
          'to_register17_dout' => {
9727 
            'attributes' => {
9728 
              'bin_pt' => 0,
9729 
              'is_floating_block' => 1,
9730 
              'must_be_hdl_vector' => 1,
9731 
              'period' => 1,
9732 
              'port_id' => 0,
9733 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/dout',
9734 
              'type' => 'UFix_32_0',
9735 
            },
9736 
            'direction' => 'in',
9737 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9738 
            'width' => 32,
9739 
          },
9740 
          'to_register17_en' => {
9741 
            'attributes' => {
9742 
              'bin_pt' => 0,
9743 
              'is_floating_block' => 1,
9744 
              'must_be_hdl_vector' => 1,
9745 
              'period' => 1,
9746 
              'port_id' => 1,
9747 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/en',
9748 
              'type' => 'Bool',
9749 
            },
9750 
            'direction' => 'out',
9751 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9752 
            'width' => 1,
9753 
          },
9754 
          'to_register18_ce' => {
9755 
            'attributes' => {
9756 
              'domain' => '',
9757 
              'group' => 1,
9758 
              'isCe' => 1,
9759 
              'is_floating_block' => 1,
9760 
              'period' => 1,
9761 
              'type' => 'logic',
9762 
            },
9763 
            'direction' => 'out',
9764 
            'hdlType' => 'std_logic',
9765 
            'width' => 1,
9766 
          },
9767 
          'to_register18_clk' => {
9768 
            'attributes' => {
9769 
              'domain' => '',
9770 
              'group' => 1,
9771 
              'isClk' => 1,
9772 
              'is_floating_block' => 1,
9773 
              'period' => 1,
9774 
              'type' => 'logic',
9775 
            },
9776 
            'direction' => 'out',
9777 
            'hdlType' => 'std_logic',
9778 
            'width' => 1,
9779 
          },
9780 
          'to_register18_clr' => {
9781 
            'attributes' => {
9782 
              'domain' => '',
9783 
              'group' => 1,
9784 
              'isClr' => 1,
9785 
              'is_floating_block' => 1,
9786 
              'period' => 1,
9787 
              'type' => 'logic',
9788 
              'valid_bit_used' => 0,
9789 
            },
9790 
            'direction' => 'out',
9791 
            'hdlType' => 'std_logic',
9792 
            'width' => 1,
9793 
          },
9794 
          'to_register18_data_in' => {
9795 
            'attributes' => {
9796 
              'bin_pt' => 0,
9797 
              'is_floating_block' => 1,
9798 
              'must_be_hdl_vector' => 1,
9799 
              'period' => 1,
9800 
              'port_id' => 0,
9801 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/data_in',
9802 
              'type' => 'UFix_1_0',
9803 
            },
9804 
            'direction' => 'out',
9805 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9806 
            'width' => 1,
9807 
          },
9808 
          'to_register18_dout' => {
9809 
            'attributes' => {
9810 
              'bin_pt' => 0,
9811 
              'is_floating_block' => 1,
9812 
              'must_be_hdl_vector' => 1,
9813 
              'period' => 1,
9814 
              'port_id' => 0,
9815 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/dout',
9816 
              'type' => 'UFix_1_0',
9817 
            },
9818 
            'direction' => 'in',
9819 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9820 
            'width' => 1,
9821 
          },
9822 
          'to_register18_en' => {
9823 
            'attributes' => {
9824 
              'bin_pt' => 0,
9825 
              'is_floating_block' => 1,
9826 
              'must_be_hdl_vector' => 1,
9827 
              'period' => 1,
9828 
              'port_id' => 1,
9829 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/en',
9830 
              'type' => 'Bool',
9831 
            },
9832 
            'direction' => 'out',
9833 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9834 
            'width' => 1,
9835 
          },
9836 
          'to_register19_ce' => {
9837 
            'attributes' => {
9838 
              'domain' => '',
9839 
              'group' => 1,
9840 
              'isCe' => 1,
9841 
              'is_floating_block' => 1,
9842 
              'period' => 1,
9843 
              'type' => 'logic',
9844 
            },
9845 
            'direction' => 'out',
9846 
            'hdlType' => 'std_logic',
9847 
            'width' => 1,
9848 
          },
9849 
          'to_register19_clk' => {
9850 
            'attributes' => {
9851 
              'domain' => '',
9852 
              'group' => 1,
9853 
              'isClk' => 1,
9854 
              'is_floating_block' => 1,
9855 
              'period' => 1,
9856 
              'type' => 'logic',
9857 
            },
9858 
            'direction' => 'out',
9859 
            'hdlType' => 'std_logic',
9860 
            'width' => 1,
9861 
          },
9862 
          'to_register19_clr' => {
9863 
            'attributes' => {
9864 
              'domain' => '',
9865 
              'group' => 1,
9866 
              'isClr' => 1,
9867 
              'is_floating_block' => 1,
9868 
              'period' => 1,
9869 
              'type' => 'logic',
9870 
              'valid_bit_used' => 0,
9871 
            },
9872 
            'direction' => 'out',
9873 
            'hdlType' => 'std_logic',
9874 
            'width' => 1,
9875 
          },
9876 
          'to_register19_data_in' => {
9877 
            'attributes' => {
9878 
              'bin_pt' => 0,
9879 
              'is_floating_block' => 1,
9880 
              'must_be_hdl_vector' => 1,
9881 
              'period' => 1,
9882 
              'port_id' => 0,
9883 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/data_in',
9884 
              'type' => 'UFix_1_0',
9885 
            },
9886 
            'direction' => 'out',
9887 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9888 
            'width' => 1,
9889 
          },
9890 
          'to_register19_dout' => {
9891 
            'attributes' => {
9892 
              'bin_pt' => 0,
9893 
              'is_floating_block' => 1,
9894 
              'must_be_hdl_vector' => 1,
9895 
              'period' => 1,
9896 
              'port_id' => 0,
9897 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/dout',
9898 
              'type' => 'UFix_1_0',
9899 
            },
9900 
            'direction' => 'in',
9901 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9902 
            'width' => 1,
9903 
          },
9904 
          'to_register19_en' => {
9905 
            'attributes' => {
9906 
              'bin_pt' => 0,
9907 
              'is_floating_block' => 1,
9908 
              'must_be_hdl_vector' => 1,
9909 
              'period' => 1,
9910 
              'port_id' => 1,
9911 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/en',
9912 
              'type' => 'Bool',
9913 
            },
9914 
            'direction' => 'out',
9915 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9916 
            'width' => 1,
9917 
          },
9918 
          'to_register1_ce' => {
9919 
            'attributes' => {
9920 
              'domain' => '',
9921 
              'group' => 1,
9922 
              'isCe' => 1,
9923 
              'is_floating_block' => 1,
9924 
              'period' => 1,
9925 
              'type' => 'logic',
9926 
            },
9927 
            'direction' => 'out',
9928 
            'hdlType' => 'std_logic',
9929 
            'width' => 1,
9930 
          },
9931 
          'to_register1_clk' => {
9932 
            'attributes' => {
9933 
              'domain' => '',
9934 
              'group' => 1,
9935 
              'isClk' => 1,
9936 
              'is_floating_block' => 1,
9937 
              'period' => 1,
9938 
              'type' => 'logic',
9939 
            },
9940 
            'direction' => 'out',
9941 
            'hdlType' => 'std_logic',
9942 
            'width' => 1,
9943 
          },
9944 
          'to_register1_clr' => {
9945 
            'attributes' => {
9946 
              'domain' => '',
9947 
              'group' => 1,
9948 
              'isClr' => 1,
9949 
              'is_floating_block' => 1,
9950 
              'period' => 1,
9951 
              'type' => 'logic',
9952 
              'valid_bit_used' => 0,
9953 
            },
9954 
            'direction' => 'out',
9955 
            'hdlType' => 'std_logic',
9956 
            'width' => 1,
9957 
          },
9958 
          'to_register1_data_in' => {
9959 
            'attributes' => {
9960 
              'bin_pt' => 0,
9961 
              'is_floating_block' => 1,
9962 
              'must_be_hdl_vector' => 1,
9963 
              'period' => 1,
9964 
              'port_id' => 0,
9965 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/data_in',
9966 
              'type' => 'UFix_32_0',
9967 
            },
9968 
            'direction' => 'out',
9969 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9970 
            'width' => 32,
9971 
          },
9972 
          'to_register1_dout' => {
9973 
            'attributes' => {
9974 
              'bin_pt' => 0,
9975 
              'is_floating_block' => 1,
9976 
              'must_be_hdl_vector' => 1,
9977 
              'period' => 1,
9978 
              'port_id' => 0,
9979 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/dout',
9980 
              'type' => 'UFix_32_0',
9981 
            },
9982 
            'direction' => 'in',
9983 
            'hdlType' => 'std_logic_vector(31 downto 0)',
9984 
            'width' => 32,
9985 
          },
9986 
          'to_register1_en' => {
9987 
            'attributes' => {
9988 
              'bin_pt' => 0,
9989 
              'is_floating_block' => 1,
9990 
              'must_be_hdl_vector' => 1,
9991 
              'period' => 1,
9992 
              'port_id' => 1,
9993 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/en',
9994 
              'type' => 'Bool',
9995 
            },
9996 
            'direction' => 'out',
9997 
            'hdlType' => 'std_logic_vector(0 downto 0)',
9998 
            'width' => 1,
9999 
          },
10000 
          'to_register20_ce' => {
10001 
            'attributes' => {
10002 
              'domain' => '',
10003 
              'group' => 1,
10004 
              'isCe' => 1,
10005 
              'is_floating_block' => 1,
10006 
              'period' => 1,
10007 
              'type' => 'logic',
10008 
            },
10009 
            'direction' => 'out',
10010 
            'hdlType' => 'std_logic',
10011 
            'width' => 1,
10012 
          },
10013 
          'to_register20_clk' => {
10014 
            'attributes' => {
10015 
              'domain' => '',
10016 
              'group' => 1,
10017 
              'isClk' => 1,
10018 
              'is_floating_block' => 1,
10019 
              'period' => 1,
10020 
              'type' => 'logic',
10021 
            },
10022 
            'direction' => 'out',
10023 
            'hdlType' => 'std_logic',
10024 
            'width' => 1,
10025 
          },
10026 
          'to_register20_clr' => {
10027 
            'attributes' => {
10028 
              'domain' => '',
10029 
              'group' => 1,
10030 
              'isClr' => 1,
10031 
              'is_floating_block' => 1,
10032 
              'period' => 1,
10033 
              'type' => 'logic',
10034 
              'valid_bit_used' => 0,
10035 
            },
10036 
            'direction' => 'out',
10037 
            'hdlType' => 'std_logic',
10038 
            'width' => 1,
10039 
          },
10040 
          'to_register20_data_in' => {
10041 
            'attributes' => {
10042 
              'bin_pt' => 0,
10043 
              'is_floating_block' => 1,
10044 
              'must_be_hdl_vector' => 1,
10045 
              'period' => 1,
10046 
              'port_id' => 0,
10047 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/data_in',
10048 
              'type' => 'UFix_32_0',
10049 
            },
10050 
            'direction' => 'out',
10051 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10052 
            'width' => 32,
10053 
          },
10054 
          'to_register20_dout' => {
10055 
            'attributes' => {
10056 
              'bin_pt' => 0,
10057 
              'is_floating_block' => 1,
10058 
              'must_be_hdl_vector' => 1,
10059 
              'period' => 1,
10060 
              'port_id' => 0,
10061 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/dout',
10062 
              'type' => 'UFix_32_0',
10063 
            },
10064 
            'direction' => 'in',
10065 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10066 
            'width' => 32,
10067 
          },
10068 
          'to_register20_en' => {
10069 
            'attributes' => {
10070 
              'bin_pt' => 0,
10071 
              'is_floating_block' => 1,
10072 
              'must_be_hdl_vector' => 1,
10073 
              'period' => 1,
10074 
              'port_id' => 1,
10075 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/en',
10076 
              'type' => 'Bool',
10077 
            },
10078 
            'direction' => 'out',
10079 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10080 
            'width' => 1,
10081 
          },
10082 
          'to_register21_ce' => {
10083 
            'attributes' => {
10084 
              'domain' => '',
10085 
              'group' => 1,
10086 
              'isCe' => 1,
10087 
              'is_floating_block' => 1,
10088 
              'period' => 1,
10089 
              'type' => 'logic',
10090 
            },
10091 
            'direction' => 'out',
10092 
            'hdlType' => 'std_logic',
10093 
            'width' => 1,
10094 
          },
10095 
          'to_register21_clk' => {
10096 
            'attributes' => {
10097 
              'domain' => '',
10098 
              'group' => 1,
10099 
              'isClk' => 1,
10100 
              'is_floating_block' => 1,
10101 
              'period' => 1,
10102 
              'type' => 'logic',
10103 
            },
10104 
            'direction' => 'out',
10105 
            'hdlType' => 'std_logic',
10106 
            'width' => 1,
10107 
          },
10108 
          'to_register21_clr' => {
10109 
            'attributes' => {
10110 
              'domain' => '',
10111 
              'group' => 1,
10112 
              'isClr' => 1,
10113 
              'is_floating_block' => 1,
10114 
              'period' => 1,
10115 
              'type' => 'logic',
10116 
              'valid_bit_used' => 0,
10117 
            },
10118 
            'direction' => 'out',
10119 
            'hdlType' => 'std_logic',
10120 
            'width' => 1,
10121 
          },
10122 
          'to_register21_data_in' => {
10123 
            'attributes' => {
10124 
              'bin_pt' => 0,
10125 
              'is_floating_block' => 1,
10126 
              'must_be_hdl_vector' => 1,
10127 
              'period' => 1,
10128 
              'port_id' => 0,
10129 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/data_in',
10130 
              'type' => 'Bool',
10131 
            },
10132 
            'direction' => 'out',
10133 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10134 
            'width' => 1,
10135 
          },
10136 
          'to_register21_dout' => {
10137 
            'attributes' => {
10138 
              'bin_pt' => 0,
10139 
              'is_floating_block' => 1,
10140 
              'must_be_hdl_vector' => 1,
10141 
              'period' => 1,
10142 
              'port_id' => 0,
10143 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/dout',
10144 
              'type' => 'Bool',
10145 
            },
10146 
            'direction' => 'in',
10147 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10148 
            'width' => 1,
10149 
          },
10150 
          'to_register21_en' => {
10151 
            'attributes' => {
10152 
              'bin_pt' => 0,
10153 
              'is_floating_block' => 1,
10154 
              'must_be_hdl_vector' => 1,
10155 
              'period' => 1,
10156 
              'port_id' => 1,
10157 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/en',
10158 
              'type' => 'Bool',
10159 
            },
10160 
            'direction' => 'out',
10161 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10162 
            'width' => 1,
10163 
          },
10164 
          'to_register22_ce' => {
10165 
            'attributes' => {
10166 
              'domain' => '',
10167 
              'group' => 1,
10168 
              'isCe' => 1,
10169 
              'is_floating_block' => 1,
10170 
              'period' => 1,
10171 
              'type' => 'logic',
10172 
            },
10173 
            'direction' => 'out',
10174 
            'hdlType' => 'std_logic',
10175 
            'width' => 1,
10176 
          },
10177 
          'to_register22_clk' => {
10178 
            'attributes' => {
10179 
              'domain' => '',
10180 
              'group' => 1,
10181 
              'isClk' => 1,
10182 
              'is_floating_block' => 1,
10183 
              'period' => 1,
10184 
              'type' => 'logic',
10185 
            },
10186 
            'direction' => 'out',
10187 
            'hdlType' => 'std_logic',
10188 
            'width' => 1,
10189 
          },
10190 
          'to_register22_clr' => {
10191 
            'attributes' => {
10192 
              'domain' => '',
10193 
              'group' => 1,
10194 
              'isClr' => 1,
10195 
              'is_floating_block' => 1,
10196 
              'period' => 1,
10197 
              'type' => 'logic',
10198 
              'valid_bit_used' => 0,
10199 
            },
10200 
            'direction' => 'out',
10201 
            'hdlType' => 'std_logic',
10202 
            'width' => 1,
10203 
          },
10204 
          'to_register22_data_in' => {
10205 
            'attributes' => {
10206 
              'bin_pt' => 0,
10207 
              'is_floating_block' => 1,
10208 
              'must_be_hdl_vector' => 1,
10209 
              'period' => 1,
10210 
              'port_id' => 0,
10211 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/data_in',
10212 
              'type' => 'UFix_32_0',
10213 
            },
10214 
            'direction' => 'out',
10215 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10216 
            'width' => 32,
10217 
          },
10218 
          'to_register22_dout' => {
10219 
            'attributes' => {
10220 
              'bin_pt' => 0,
10221 
              'is_floating_block' => 1,
10222 
              'must_be_hdl_vector' => 1,
10223 
              'period' => 1,
10224 
              'port_id' => 0,
10225 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/dout',
10226 
              'type' => 'UFix_32_0',
10227 
            },
10228 
            'direction' => 'in',
10229 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10230 
            'width' => 32,
10231 
          },
10232 
          'to_register22_en' => {
10233 
            'attributes' => {
10234 
              'bin_pt' => 0,
10235 
              'is_floating_block' => 1,
10236 
              'must_be_hdl_vector' => 1,
10237 
              'period' => 1,
10238 
              'port_id' => 1,
10239 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/en',
10240 
              'type' => 'Bool',
10241 
            },
10242 
            'direction' => 'out',
10243 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10244 
            'width' => 1,
10245 
          },
10246 
          'to_register23_ce' => {
10247 
            'attributes' => {
10248 
              'domain' => '',
10249 
              'group' => 1,
10250 
              'isCe' => 1,
10251 
              'is_floating_block' => 1,
10252 
              'period' => 1,
10253 
              'type' => 'logic',
10254 
            },
10255 
            'direction' => 'out',
10256 
            'hdlType' => 'std_logic',
10257 
            'width' => 1,
10258 
          },
10259 
          'to_register23_clk' => {
10260 
            'attributes' => {
10261 
              'domain' => '',
10262 
              'group' => 1,
10263 
              'isClk' => 1,
10264 
              'is_floating_block' => 1,
10265 
              'period' => 1,
10266 
              'type' => 'logic',
10267 
            },
10268 
            'direction' => 'out',
10269 
            'hdlType' => 'std_logic',
10270 
            'width' => 1,
10271 
          },
10272 
          'to_register23_clr' => {
10273 
            'attributes' => {
10274 
              'domain' => '',
10275 
              'group' => 1,
10276 
              'isClr' => 1,
10277 
              'is_floating_block' => 1,
10278 
              'period' => 1,
10279 
              'type' => 'logic',
10280 
              'valid_bit_used' => 0,
10281 
            },
10282 
            'direction' => 'out',
10283 
            'hdlType' => 'std_logic',
10284 
            'width' => 1,
10285 
          },
10286 
          'to_register23_data_in' => {
10287 
            'attributes' => {
10288 
              'bin_pt' => 0,
10289 
              'is_floating_block' => 1,
10290 
              'must_be_hdl_vector' => 1,
10291 
              'period' => 1,
10292 
              'port_id' => 0,
10293 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/data_in',
10294 
              'type' => 'Bool',
10295 
            },
10296 
            'direction' => 'out',
10297 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10298 
            'width' => 1,
10299 
          },
10300 
          'to_register23_dout' => {
10301 
            'attributes' => {
10302 
              'bin_pt' => 0,
10303 
              'is_floating_block' => 1,
10304 
              'must_be_hdl_vector' => 1,
10305 
              'period' => 1,
10306 
              'port_id' => 0,
10307 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/dout',
10308 
              'type' => 'Bool',
10309 
            },
10310 
            'direction' => 'in',
10311 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10312 
            'width' => 1,
10313 
          },
10314 
          'to_register23_en' => {
10315 
            'attributes' => {
10316 
              'bin_pt' => 0,
10317 
              'is_floating_block' => 1,
10318 
              'must_be_hdl_vector' => 1,
10319 
              'period' => 1,
10320 
              'port_id' => 1,
10321 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/en',
10322 
              'type' => 'Bool',
10323 
            },
10324 
            'direction' => 'out',
10325 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10326 
            'width' => 1,
10327 
          },
10328 
          'to_register24_ce' => {
10329 
            'attributes' => {
10330 
              'domain' => '',
10331 
              'group' => 1,
10332 
              'isCe' => 1,
10333 
              'is_floating_block' => 1,
10334 
              'period' => 1,
10335 
              'type' => 'logic',
10336 
            },
10337 
            'direction' => 'out',
10338 
            'hdlType' => 'std_logic',
10339 
            'width' => 1,
10340 
          },
10341 
          'to_register24_clk' => {
10342 
            'attributes' => {
10343 
              'domain' => '',
10344 
              'group' => 1,
10345 
              'isClk' => 1,
10346 
              'is_floating_block' => 1,
10347 
              'period' => 1,
10348 
              'type' => 'logic',
10349 
            },
10350 
            'direction' => 'out',
10351 
            'hdlType' => 'std_logic',
10352 
            'width' => 1,
10353 
          },
10354 
          'to_register24_clr' => {
10355 
            'attributes' => {
10356 
              'domain' => '',
10357 
              'group' => 1,
10358 
              'isClr' => 1,
10359 
              'is_floating_block' => 1,
10360 
              'period' => 1,
10361 
              'type' => 'logic',
10362 
              'valid_bit_used' => 0,
10363 
            },
10364 
            'direction' => 'out',
10365 
            'hdlType' => 'std_logic',
10366 
            'width' => 1,
10367 
          },
10368 
          'to_register24_data_in' => {
10369 
            'attributes' => {
10370 
              'bin_pt' => 0,
10371 
              'is_floating_block' => 1,
10372 
              'must_be_hdl_vector' => 1,
10373 
              'period' => 1,
10374 
              'port_id' => 0,
10375 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/data_in',
10376 
              'type' => 'UFix_32_0',
10377 
            },
10378 
            'direction' => 'out',
10379 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10380 
            'width' => 32,
10381 
          },
10382 
          'to_register24_dout' => {
10383 
            'attributes' => {
10384 
              'bin_pt' => 0,
10385 
              'is_floating_block' => 1,
10386 
              'must_be_hdl_vector' => 1,
10387 
              'period' => 1,
10388 
              'port_id' => 0,
10389 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/dout',
10390 
              'type' => 'UFix_32_0',
10391 
            },
10392 
            'direction' => 'in',
10393 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10394 
            'width' => 32,
10395 
          },
10396 
          'to_register24_en' => {
10397 
            'attributes' => {
10398 
              'bin_pt' => 0,
10399 
              'is_floating_block' => 1,
10400 
              'must_be_hdl_vector' => 1,
10401 
              'period' => 1,
10402 
              'port_id' => 1,
10403 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/en',
10404 
              'type' => 'Bool',
10405 
            },
10406 
            'direction' => 'out',
10407 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10408 
            'width' => 1,
10409 
          },
10410 
          'to_register25_ce' => {
10411 
            'attributes' => {
10412 
              'domain' => '',
10413 
              'group' => 1,
10414 
              'isCe' => 1,
10415 
              'is_floating_block' => 1,
10416 
              'period' => 1,
10417 
              'type' => 'logic',
10418 
            },
10419 
            'direction' => 'out',
10420 
            'hdlType' => 'std_logic',
10421 
            'width' => 1,
10422 
          },
10423 
          'to_register25_clk' => {
10424 
            'attributes' => {
10425 
              'domain' => '',
10426 
              'group' => 1,
10427 
              'isClk' => 1,
10428 
              'is_floating_block' => 1,
10429 
              'period' => 1,
10430 
              'type' => 'logic',
10431 
            },
10432 
            'direction' => 'out',
10433 
            'hdlType' => 'std_logic',
10434 
            'width' => 1,
10435 
          },
10436 
          'to_register25_clr' => {
10437 
            'attributes' => {
10438 
              'domain' => '',
10439 
              'group' => 1,
10440 
              'isClr' => 1,
10441 
              'is_floating_block' => 1,
10442 
              'period' => 1,
10443 
              'type' => 'logic',
10444 
              'valid_bit_used' => 0,
10445 
            },
10446 
            'direction' => 'out',
10447 
            'hdlType' => 'std_logic',
10448 
            'width' => 1,
10449 
          },
10450 
          'to_register25_data_in' => {
10451 
            'attributes' => {
10452 
              'bin_pt' => 0,
10453 
              'is_floating_block' => 1,
10454 
              'must_be_hdl_vector' => 1,
10455 
              'period' => 1,
10456 
              'port_id' => 0,
10457 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/data_in',
10458 
              'type' => 'Bool',
10459 
            },
10460 
            'direction' => 'out',
10461 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10462 
            'width' => 1,
10463 
          },
10464 
          'to_register25_dout' => {
10465 
            'attributes' => {
10466 
              'bin_pt' => 0,
10467 
              'is_floating_block' => 1,
10468 
              'must_be_hdl_vector' => 1,
10469 
              'period' => 1,
10470 
              'port_id' => 0,
10471 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/dout',
10472 
              'type' => 'Bool',
10473 
            },
10474 
            'direction' => 'in',
10475 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10476 
            'width' => 1,
10477 
          },
10478 
          'to_register25_en' => {
10479 
            'attributes' => {
10480 
              'bin_pt' => 0,
10481 
              'is_floating_block' => 1,
10482 
              'must_be_hdl_vector' => 1,
10483 
              'period' => 1,
10484 
              'port_id' => 1,
10485 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/en',
10486 
              'type' => 'Bool',
10487 
            },
10488 
            'direction' => 'out',
10489 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10490 
            'width' => 1,
10491 
          },
10492 
          'to_register26_ce' => {
10493 
            'attributes' => {
10494 
              'domain' => '',
10495 
              'group' => 1,
10496 
              'isCe' => 1,
10497 
              'is_floating_block' => 1,
10498 
              'period' => 1,
10499 
              'type' => 'logic',
10500 
            },
10501 
            'direction' => 'out',
10502 
            'hdlType' => 'std_logic',
10503 
            'width' => 1,
10504 
          },
10505 
          'to_register26_clk' => {
10506 
            'attributes' => {
10507 
              'domain' => '',
10508 
              'group' => 1,
10509 
              'isClk' => 1,
10510 
              'is_floating_block' => 1,
10511 
              'period' => 1,
10512 
              'type' => 'logic',
10513 
            },
10514 
            'direction' => 'out',
10515 
            'hdlType' => 'std_logic',
10516 
            'width' => 1,
10517 
          },
10518 
          'to_register26_clr' => {
10519 
            'attributes' => {
10520 
              'domain' => '',
10521 
              'group' => 1,
10522 
              'isClr' => 1,
10523 
              'is_floating_block' => 1,
10524 
              'period' => 1,
10525 
              'type' => 'logic',
10526 
              'valid_bit_used' => 0,
10527 
            },
10528 
            'direction' => 'out',
10529 
            'hdlType' => 'std_logic',
10530 
            'width' => 1,
10531 
          },
10532 
          'to_register26_data_in' => {
10533 
            'attributes' => {
10534 
              'bin_pt' => 0,
10535 
              'is_floating_block' => 1,
10536 
              'must_be_hdl_vector' => 1,
10537 
              'period' => 1,
10538 
              'port_id' => 0,
10539 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/data_in',
10540 
              'type' => 'UFix_32_0',
10541 
            },
10542 
            'direction' => 'out',
10543 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10544 
            'width' => 32,
10545 
          },
10546 
          'to_register26_dout' => {
10547 
            'attributes' => {
10548 
              'bin_pt' => 0,
10549 
              'is_floating_block' => 1,
10550 
              'must_be_hdl_vector' => 1,
10551 
              'period' => 1,
10552 
              'port_id' => 0,
10553 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/dout',
10554 
              'type' => 'UFix_32_0',
10555 
            },
10556 
            'direction' => 'in',
10557 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10558 
            'width' => 32,
10559 
          },
10560 
          'to_register26_en' => {
10561 
            'attributes' => {
10562 
              'bin_pt' => 0,
10563 
              'is_floating_block' => 1,
10564 
              'must_be_hdl_vector' => 1,
10565 
              'period' => 1,
10566 
              'port_id' => 1,
10567 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/en',
10568 
              'type' => 'Bool',
10569 
            },
10570 
            'direction' => 'out',
10571 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10572 
            'width' => 1,
10573 
          },
10574 
          'to_register27_ce' => {
10575 
            'attributes' => {
10576 
              'domain' => '',
10577 
              'group' => 1,
10578 
              'isCe' => 1,
10579 
              'is_floating_block' => 1,
10580 
              'period' => 1,
10581 
              'type' => 'logic',
10582 
            },
10583 
            'direction' => 'out',
10584 
            'hdlType' => 'std_logic',
10585 
            'width' => 1,
10586 
          },
10587 
          'to_register27_clk' => {
10588 
            'attributes' => {
10589 
              'domain' => '',
10590 
              'group' => 1,
10591 
              'isClk' => 1,
10592 
              'is_floating_block' => 1,
10593 
              'period' => 1,
10594 
              'type' => 'logic',
10595 
            },
10596 
            'direction' => 'out',
10597 
            'hdlType' => 'std_logic',
10598 
            'width' => 1,
10599 
          },
10600 
          'to_register27_clr' => {
10601 
            'attributes' => {
10602 
              'domain' => '',
10603 
              'group' => 1,
10604 
              'isClr' => 1,
10605 
              'is_floating_block' => 1,
10606 
              'period' => 1,
10607 
              'type' => 'logic',
10608 
              'valid_bit_used' => 0,
10609 
            },
10610 
            'direction' => 'out',
10611 
            'hdlType' => 'std_logic',
10612 
            'width' => 1,
10613 
          },
10614 
          'to_register27_data_in' => {
10615 
            'attributes' => {
10616 
              'bin_pt' => 0,
10617 
              'is_floating_block' => 1,
10618 
              'must_be_hdl_vector' => 1,
10619 
              'period' => 1,
10620 
              'port_id' => 0,
10621 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/data_in',
10622 
              'type' => 'Bool',
10623 
            },
10624 
            'direction' => 'out',
10625 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10626 
            'width' => 1,
10627 
          },
10628 
          'to_register27_dout' => {
10629 
            'attributes' => {
10630 
              'bin_pt' => 0,
10631 
              'is_floating_block' => 1,
10632 
              'must_be_hdl_vector' => 1,
10633 
              'period' => 1,
10634 
              'port_id' => 0,
10635 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
10636 
              'type' => 'Bool',
10637 
            },
10638 
            'direction' => 'in',
10639 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10640 
            'width' => 1,
10641 
          },
10642 
          'to_register27_en' => {
10643 
            'attributes' => {
10644 
              'bin_pt' => 0,
10645 
              'is_floating_block' => 1,
10646 
              'must_be_hdl_vector' => 1,
10647 
              'period' => 1,
10648 
              'port_id' => 1,
10649 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/en',
10650 
              'type' => 'Bool',
10651 
            },
10652 
            'direction' => 'out',
10653 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10654 
            'width' => 1,
10655 
          },
10656 
          'to_register28_ce' => {
10657 
            'attributes' => {
10658 
              'domain' => '',
10659 
              'group' => 1,
10660 
              'isCe' => 1,
10661 
              'is_floating_block' => 1,
10662 
              'period' => 1,
10663 
              'type' => 'logic',
10664 
            },
10665 
            'direction' => 'out',
10666 
            'hdlType' => 'std_logic',
10667 
            'width' => 1,
10668 
          },
10669 
          'to_register28_clk' => {
10670 
            'attributes' => {
10671 
              'domain' => '',
10672 
              'group' => 1,
10673 
              'isClk' => 1,
10674 
              'is_floating_block' => 1,
10675 
              'period' => 1,
10676 
              'type' => 'logic',
10677 
            },
10678 
            'direction' => 'out',
10679 
            'hdlType' => 'std_logic',
10680 
            'width' => 1,
10681 
          },
10682 
          'to_register28_clr' => {
10683 
            'attributes' => {
10684 
              'domain' => '',
10685 
              'group' => 1,
10686 
              'isClr' => 1,
10687 
              'is_floating_block' => 1,
10688 
              'period' => 1,
10689 
              'type' => 'logic',
10690 
              'valid_bit_used' => 0,
10691 
            },
10692 
            'direction' => 'out',
10693 
            'hdlType' => 'std_logic',
10694 
            'width' => 1,
10695 
          },
10696 
          'to_register28_data_in' => {
10697 
            'attributes' => {
10698 
              'bin_pt' => 0,
10699 
              'is_floating_block' => 1,
10700 
              'must_be_hdl_vector' => 1,
10701 
              'period' => 1,
10702 
              'port_id' => 0,
10703 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/data_in',
10704 
              'type' => 'UFix_32_0',
10705 
            },
10706 
            'direction' => 'out',
10707 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10708 
            'width' => 32,
10709 
          },
10710 
          'to_register28_dout' => {
10711 
            'attributes' => {
10712 
              'bin_pt' => 0,
10713 
              'is_floating_block' => 1,
10714 
              'must_be_hdl_vector' => 1,
10715 
              'period' => 1,
10716 
              'port_id' => 0,
10717 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/dout',
10718 
              'type' => 'UFix_32_0',
10719 
            },
10720 
            'direction' => 'in',
10721 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10722 
            'width' => 32,
10723 
          },
10724 
          'to_register28_en' => {
10725 
            'attributes' => {
10726 
              'bin_pt' => 0,
10727 
              'is_floating_block' => 1,
10728 
              'must_be_hdl_vector' => 1,
10729 
              'period' => 1,
10730 
              'port_id' => 1,
10731 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/en',
10732 
              'type' => 'Bool',
10733 
            },
10734 
            'direction' => 'out',
10735 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10736 
            'width' => 1,
10737 
          },
10738 
          'to_register29_ce' => {
10739 
            'attributes' => {
10740 
              'domain' => '',
10741 
              'group' => 1,
10742 
              'isCe' => 1,
10743 
              'is_floating_block' => 1,
10744 
              'period' => 1,
10745 
              'type' => 'logic',
10746 
            },
10747 
            'direction' => 'out',
10748 
            'hdlType' => 'std_logic',
10749 
            'width' => 1,
10750 
          },
10751 
          'to_register29_clk' => {
10752 
            'attributes' => {
10753 
              'domain' => '',
10754 
              'group' => 1,
10755 
              'isClk' => 1,
10756 
              'is_floating_block' => 1,
10757 
              'period' => 1,
10758 
              'type' => 'logic',
10759 
            },
10760 
            'direction' => 'out',
10761 
            'hdlType' => 'std_logic',
10762 
            'width' => 1,
10763 
          },
10764 
          'to_register29_clr' => {
10765 
            'attributes' => {
10766 
              'domain' => '',
10767 
              'group' => 1,
10768 
              'isClr' => 1,
10769 
              'is_floating_block' => 1,
10770 
              'period' => 1,
10771 
              'type' => 'logic',
10772 
              'valid_bit_used' => 0,
10773 
            },
10774 
            'direction' => 'out',
10775 
            'hdlType' => 'std_logic',
10776 
            'width' => 1,
10777 
          },
10778 
          'to_register29_data_in' => {
10779 
            'attributes' => {
10780 
              'bin_pt' => 0,
10781 
              'is_floating_block' => 1,
10782 
              'must_be_hdl_vector' => 1,
10783 
              'period' => 1,
10784 
              'port_id' => 0,
10785 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/data_in',
10786 
              'type' => 'Bool',
10787 
            },
10788 
            'direction' => 'out',
10789 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10790 
            'width' => 1,
10791 
          },
10792 
          'to_register29_dout' => {
10793 
            'attributes' => {
10794 
              'bin_pt' => 0,
10795 
              'is_floating_block' => 1,
10796 
              'must_be_hdl_vector' => 1,
10797 
              'period' => 1,
10798 
              'port_id' => 0,
10799 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/dout',
10800 
              'type' => 'Bool',
10801 
            },
10802 
            'direction' => 'in',
10803 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10804 
            'width' => 1,
10805 
          },
10806 
          'to_register29_en' => {
10807 
            'attributes' => {
10808 
              'bin_pt' => 0,
10809 
              'is_floating_block' => 1,
10810 
              'must_be_hdl_vector' => 1,
10811 
              'period' => 1,
10812 
              'port_id' => 1,
10813 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/en',
10814 
              'type' => 'Bool',
10815 
            },
10816 
            'direction' => 'out',
10817 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10818 
            'width' => 1,
10819 
          },
10820 
          'to_register2_ce' => {
10821 
            'attributes' => {
10822 
              'domain' => '',
10823 
              'group' => 1,
10824 
              'isCe' => 1,
10825 
              'is_floating_block' => 1,
10826 
              'period' => 1,
10827 
              'type' => 'logic',
10828 
            },
10829 
            'direction' => 'out',
10830 
            'hdlType' => 'std_logic',
10831 
            'width' => 1,
10832 
          },
10833 
          'to_register2_clk' => {
10834 
            'attributes' => {
10835 
              'domain' => '',
10836 
              'group' => 1,
10837 
              'isClk' => 1,
10838 
              'is_floating_block' => 1,
10839 
              'period' => 1,
10840 
              'type' => 'logic',
10841 
            },
10842 
            'direction' => 'out',
10843 
            'hdlType' => 'std_logic',
10844 
            'width' => 1,
10845 
          },
10846 
          'to_register2_clr' => {
10847 
            'attributes' => {
10848 
              'domain' => '',
10849 
              'group' => 1,
10850 
              'isClr' => 1,
10851 
              'is_floating_block' => 1,
10852 
              'period' => 1,
10853 
              'type' => 'logic',
10854 
              'valid_bit_used' => 0,
10855 
            },
10856 
            'direction' => 'out',
10857 
            'hdlType' => 'std_logic',
10858 
            'width' => 1,
10859 
          },
10860 
          'to_register2_data_in' => {
10861 
            'attributes' => {
10862 
              'bin_pt' => 0,
10863 
              'is_floating_block' => 1,
10864 
              'must_be_hdl_vector' => 1,
10865 
              'period' => 1,
10866 
              'port_id' => 0,
10867 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/data_in',
10868 
              'type' => 'UFix_32_0',
10869 
            },
10870 
            'direction' => 'out',
10871 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10872 
            'width' => 32,
10873 
          },
10874 
          'to_register2_dout' => {
10875 
            'attributes' => {
10876 
              'bin_pt' => 0,
10877 
              'is_floating_block' => 1,
10878 
              'must_be_hdl_vector' => 1,
10879 
              'period' => 1,
10880 
              'port_id' => 0,
10881 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/dout',
10882 
              'type' => 'UFix_32_0',
10883 
            },
10884 
            'direction' => 'in',
10885 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10886 
            'width' => 32,
10887 
          },
10888 
          'to_register2_en' => {
10889 
            'attributes' => {
10890 
              'bin_pt' => 0,
10891 
              'is_floating_block' => 1,
10892 
              'must_be_hdl_vector' => 1,
10893 
              'period' => 1,
10894 
              'port_id' => 1,
10895 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/en',
10896 
              'type' => 'Bool',
10897 
            },
10898 
            'direction' => 'out',
10899 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10900 
            'width' => 1,
10901 
          },
10902 
          'to_register30_ce' => {
10903 
            'attributes' => {
10904 
              'domain' => '',
10905 
              'group' => 1,
10906 
              'isCe' => 1,
10907 
              'is_floating_block' => 1,
10908 
              'period' => 1,
10909 
              'type' => 'logic',
10910 
            },
10911 
            'direction' => 'out',
10912 
            'hdlType' => 'std_logic',
10913 
            'width' => 1,
10914 
          },
10915 
          'to_register30_clk' => {
10916 
            'attributes' => {
10917 
              'domain' => '',
10918 
              'group' => 1,
10919 
              'isClk' => 1,
10920 
              'is_floating_block' => 1,
10921 
              'period' => 1,
10922 
              'type' => 'logic',
10923 
            },
10924 
            'direction' => 'out',
10925 
            'hdlType' => 'std_logic',
10926 
            'width' => 1,
10927 
          },
10928 
          'to_register30_clr' => {
10929 
            'attributes' => {
10930 
              'domain' => '',
10931 
              'group' => 1,
10932 
              'isClr' => 1,
10933 
              'is_floating_block' => 1,
10934 
              'period' => 1,
10935 
              'type' => 'logic',
10936 
              'valid_bit_used' => 0,
10937 
            },
10938 
            'direction' => 'out',
10939 
            'hdlType' => 'std_logic',
10940 
            'width' => 1,
10941 
          },
10942 
          'to_register30_data_in' => {
10943 
            'attributes' => {
10944 
              'bin_pt' => 0,
10945 
              'is_floating_block' => 1,
10946 
              'must_be_hdl_vector' => 1,
10947 
              'period' => 1,
10948 
              'port_id' => 0,
10949 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/data_in',
10950 
              'type' => 'UFix_32_0',
10951 
            },
10952 
            'direction' => 'out',
10953 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10954 
            'width' => 32,
10955 
          },
10956 
          'to_register30_dout' => {
10957 
            'attributes' => {
10958 
              'bin_pt' => 0,
10959 
              'is_floating_block' => 1,
10960 
              'must_be_hdl_vector' => 1,
10961 
              'period' => 1,
10962 
              'port_id' => 0,
10963 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/dout',
10964 
              'type' => 'UFix_32_0',
10965 
            },
10966 
            'direction' => 'in',
10967 
            'hdlType' => 'std_logic_vector(31 downto 0)',
10968 
            'width' => 32,
10969 
          },
10970 
          'to_register30_en' => {
10971 
            'attributes' => {
10972 
              'bin_pt' => 0,
10973 
              'is_floating_block' => 1,
10974 
              'must_be_hdl_vector' => 1,
10975 
              'period' => 1,
10976 
              'port_id' => 1,
10977 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/en',
10978 
              'type' => 'Bool',
10979 
            },
10980 
            'direction' => 'out',
10981 
            'hdlType' => 'std_logic_vector(0 downto 0)',
10982 
            'width' => 1,
10983 
          },
10984 
          'to_register31_ce' => {
10985 
            'attributes' => {
10986 
              'domain' => '',
10987 
              'group' => 1,
10988 
              'isCe' => 1,
10989 
              'is_floating_block' => 1,
10990 
              'period' => 1,
10991 
              'type' => 'logic',
10992 
            },
10993 
            'direction' => 'out',
10994 
            'hdlType' => 'std_logic',
10995 
            'width' => 1,
10996 
          },
10997 
          'to_register31_clk' => {
10998 
            'attributes' => {
10999 
              'domain' => '',
11000 
              'group' => 1,
11001 
              'isClk' => 1,
11002 
              'is_floating_block' => 1,
11003 
              'period' => 1,
11004 
              'type' => 'logic',
11005 
            },
11006 
            'direction' => 'out',
11007 
            'hdlType' => 'std_logic',
11008 
            'width' => 1,
11009 
          },
11010 
          'to_register31_clr' => {
11011 
            'attributes' => {
11012 
              'domain' => '',
11013 
              'group' => 1,
11014 
              'isClr' => 1,
11015 
              'is_floating_block' => 1,
11016 
              'period' => 1,
11017 
              'type' => 'logic',
11018 
              'valid_bit_used' => 0,
11019 
            },
11020 
            'direction' => 'out',
11021 
            'hdlType' => 'std_logic',
11022 
            'width' => 1,
11023 
          },
11024 
          'to_register31_data_in' => {
11025 
            'attributes' => {
11026 
              'bin_pt' => 0,
11027 
              'is_floating_block' => 1,
11028 
              'must_be_hdl_vector' => 1,
11029 
              'period' => 1,
11030 
              'port_id' => 0,
11031 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/data_in',
11032 
              'type' => 'Bool',
11033 
            },
11034 
            'direction' => 'out',
11035 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11036 
            'width' => 1,
11037 
          },
11038 
          'to_register31_dout' => {
11039 
            'attributes' => {
11040 
              'bin_pt' => 0,
11041 
              'is_floating_block' => 1,
11042 
              'must_be_hdl_vector' => 1,
11043 
              'period' => 1,
11044 
              'port_id' => 0,
11045 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/dout',
11046 
              'type' => 'Bool',
11047 
            },
11048 
            'direction' => 'in',
11049 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11050 
            'width' => 1,
11051 
          },
11052 
          'to_register31_en' => {
11053 
            'attributes' => {
11054 
              'bin_pt' => 0,
11055 
              'is_floating_block' => 1,
11056 
              'must_be_hdl_vector' => 1,
11057 
              'period' => 1,
11058 
              'port_id' => 1,
11059 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/en',
11060 
              'type' => 'Bool',
11061 
            },
11062 
            'direction' => 'out',
11063 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11064 
            'width' => 1,
11065 
          },
11066 
          'to_register32_ce' => {
11067 
            'attributes' => {
11068 
              'domain' => '',
11069 
              'group' => 1,
11070 
              'isCe' => 1,
11071 
              'is_floating_block' => 1,
11072 
              'period' => 1,
11073 
              'type' => 'logic',
11074 
            },
11075 
            'direction' => 'out',
11076 
            'hdlType' => 'std_logic',
11077 
            'width' => 1,
11078 
          },
11079 
          'to_register32_clk' => {
11080 
            'attributes' => {
11081 
              'domain' => '',
11082 
              'group' => 1,
11083 
              'isClk' => 1,
11084 
              'is_floating_block' => 1,
11085 
              'period' => 1,
11086 
              'type' => 'logic',
11087 
            },
11088 
            'direction' => 'out',
11089 
            'hdlType' => 'std_logic',
11090 
            'width' => 1,
11091 
          },
11092 
          'to_register32_clr' => {
11093 
            'attributes' => {
11094 
              'domain' => '',
11095 
              'group' => 1,
11096 
              'isClr' => 1,
11097 
              'is_floating_block' => 1,
11098 
              'period' => 1,
11099 
              'type' => 'logic',
11100 
              'valid_bit_used' => 0,
11101 
            },
11102 
            'direction' => 'out',
11103 
            'hdlType' => 'std_logic',
11104 
            'width' => 1,
11105 
          },
11106 
          'to_register32_data_in' => {
11107 
            'attributes' => {
11108 
              'bin_pt' => 0,
11109 
              'is_floating_block' => 1,
11110 
              'must_be_hdl_vector' => 1,
11111 
              'period' => 1,
11112 
              'port_id' => 0,
11113 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/data_in',
11114 
              'type' => 'UFix_32_0',
11115 
            },
11116 
            'direction' => 'out',
11117 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11118 
            'width' => 32,
11119 
          },
11120 
          'to_register32_dout' => {
11121 
            'attributes' => {
11122 
              'bin_pt' => 0,
11123 
              'is_floating_block' => 1,
11124 
              'must_be_hdl_vector' => 1,
11125 
              'period' => 1,
11126 
              'port_id' => 0,
11127 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/dout',
11128 
              'type' => 'UFix_32_0',
11129 
            },
11130 
            'direction' => 'in',
11131 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11132 
            'width' => 32,
11133 
          },
11134 
          'to_register32_en' => {
11135 
            'attributes' => {
11136 
              'bin_pt' => 0,
11137 
              'is_floating_block' => 1,
11138 
              'must_be_hdl_vector' => 1,
11139 
              'period' => 1,
11140 
              'port_id' => 1,
11141 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/en',
11142 
              'type' => 'Bool',
11143 
            },
11144 
            'direction' => 'out',
11145 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11146 
            'width' => 1,
11147 
          },
11148 
          'to_register33_ce' => {
11149 
            'attributes' => {
11150 
              'domain' => '',
11151 
              'group' => 1,
11152 
              'isCe' => 1,
11153 
              'is_floating_block' => 1,
11154 
              'period' => 1,
11155 
              'type' => 'logic',
11156 
            },
11157 
            'direction' => 'out',
11158 
            'hdlType' => 'std_logic',
11159 
            'width' => 1,
11160 
          },
11161 
          'to_register33_clk' => {
11162 
            'attributes' => {
11163 
              'domain' => '',
11164 
              'group' => 1,
11165 
              'isClk' => 1,
11166 
              'is_floating_block' => 1,
11167 
              'period' => 1,
11168 
              'type' => 'logic',
11169 
            },
11170 
            'direction' => 'out',
11171 
            'hdlType' => 'std_logic',
11172 
            'width' => 1,
11173 
          },
11174 
          'to_register33_clr' => {
11175 
            'attributes' => {
11176 
              'domain' => '',
11177 
              'group' => 1,
11178 
              'isClr' => 1,
11179 
              'is_floating_block' => 1,
11180 
              'period' => 1,
11181 
              'type' => 'logic',
11182 
              'valid_bit_used' => 0,
11183 
            },
11184 
            'direction' => 'out',
11185 
            'hdlType' => 'std_logic',
11186 
            'width' => 1,
11187 
          },
11188 
          'to_register33_data_in' => {
11189 
            'attributes' => {
11190 
              'bin_pt' => 0,
11191 
              'is_floating_block' => 1,
11192 
              'must_be_hdl_vector' => 1,
11193 
              'period' => 1,
11194 
              'port_id' => 0,
11195 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/data_in',
11196 
              'type' => 'Bool',
11197 
            },
11198 
            'direction' => 'out',
11199 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11200 
            'width' => 1,
11201 
          },
11202 
          'to_register33_dout' => {
11203 
            'attributes' => {
11204 
              'bin_pt' => 0,
11205 
              'is_floating_block' => 1,
11206 
              'must_be_hdl_vector' => 1,
11207 
              'period' => 1,
11208 
              'port_id' => 0,
11209 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/dout',
11210 
              'type' => 'Bool',
11211 
            },
11212 
            'direction' => 'in',
11213 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11214 
            'width' => 1,
11215 
          },
11216 
          'to_register33_en' => {
11217 
            'attributes' => {
11218 
              'bin_pt' => 0,
11219 
              'is_floating_block' => 1,
11220 
              'must_be_hdl_vector' => 1,
11221 
              'period' => 1,
11222 
              'port_id' => 1,
11223 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/en',
11224 
              'type' => 'Bool',
11225 
            },
11226 
            'direction' => 'out',
11227 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11228 
            'width' => 1,
11229 
          },
11230 
          'to_register34_ce' => {
11231 
            'attributes' => {
11232 
              'domain' => '',
11233 
              'group' => 1,
11234 
              'isCe' => 1,
11235 
              'is_floating_block' => 1,
11236 
              'period' => 1,
11237 
              'type' => 'logic',
11238 
            },
11239 
            'direction' => 'out',
11240 
            'hdlType' => 'std_logic',
11241 
            'width' => 1,
11242 
          },
11243 
          'to_register34_clk' => {
11244 
            'attributes' => {
11245 
              'domain' => '',
11246 
              'group' => 1,
11247 
              'isClk' => 1,
11248 
              'is_floating_block' => 1,
11249 
              'period' => 1,
11250 
              'type' => 'logic',
11251 
            },
11252 
            'direction' => 'out',
11253 
            'hdlType' => 'std_logic',
11254 
            'width' => 1,
11255 
          },
11256 
          'to_register34_clr' => {
11257 
            'attributes' => {
11258 
              'domain' => '',
11259 
              'group' => 1,
11260 
              'isClr' => 1,
11261 
              'is_floating_block' => 1,
11262 
              'period' => 1,
11263 
              'type' => 'logic',
11264 
              'valid_bit_used' => 0,
11265 
            },
11266 
            'direction' => 'out',
11267 
            'hdlType' => 'std_logic',
11268 
            'width' => 1,
11269 
          },
11270 
          'to_register34_data_in' => {
11271 
            'attributes' => {
11272 
              'bin_pt' => 0,
11273 
              'is_floating_block' => 1,
11274 
              'must_be_hdl_vector' => 1,
11275 
              'period' => 1,
11276 
              'port_id' => 0,
11277 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/data_in',
11278 
              'type' => 'UFix_32_0',
11279 
            },
11280 
            'direction' => 'out',
11281 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11282 
            'width' => 32,
11283 
          },
11284 
          'to_register34_dout' => {
11285 
            'attributes' => {
11286 
              'bin_pt' => 0,
11287 
              'is_floating_block' => 1,
11288 
              'must_be_hdl_vector' => 1,
11289 
              'period' => 1,
11290 
              'port_id' => 0,
11291 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/dout',
11292 
              'type' => 'UFix_32_0',
11293 
            },
11294 
            'direction' => 'in',
11295 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11296 
            'width' => 32,
11297 
          },
11298 
          'to_register34_en' => {
11299 
            'attributes' => {
11300 
              'bin_pt' => 0,
11301 
              'is_floating_block' => 1,
11302 
              'must_be_hdl_vector' => 1,
11303 
              'period' => 1,
11304 
              'port_id' => 1,
11305 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
11306 
              'type' => 'Bool',
11307 
            },
11308 
            'direction' => 'out',
11309 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11310 
            'width' => 1,
11311 
          },
11312 
          'to_register3_ce' => {
11313 
            'attributes' => {
11314 
              'domain' => '',
11315 
              'group' => 1,
11316 
              'isCe' => 1,
11317 
              'is_floating_block' => 1,
11318 
              'period' => 1,
11319 
              'type' => 'logic',
11320 
            },
11321 
            'direction' => 'out',
11322 
            'hdlType' => 'std_logic',
11323 
            'width' => 1,
11324 
          },
11325 
          'to_register3_clk' => {
11326 
            'attributes' => {
11327 
              'domain' => '',
11328 
              'group' => 1,
11329 
              'isClk' => 1,
11330 
              'is_floating_block' => 1,
11331 
              'period' => 1,
11332 
              'type' => 'logic',
11333 
            },
11334 
            'direction' => 'out',
11335 
            'hdlType' => 'std_logic',
11336 
            'width' => 1,
11337 
          },
11338 
          'to_register3_clr' => {
11339 
            'attributes' => {
11340 
              'domain' => '',
11341 
              'group' => 1,
11342 
              'isClr' => 1,
11343 
              'is_floating_block' => 1,
11344 
              'period' => 1,
11345 
              'type' => 'logic',
11346 
              'valid_bit_used' => 0,
11347 
            },
11348 
            'direction' => 'out',
11349 
            'hdlType' => 'std_logic',
11350 
            'width' => 1,
11351 
          },
11352 
          'to_register3_data_in' => {
11353 
            'attributes' => {
11354 
              'bin_pt' => 0,
11355 
              'is_floating_block' => 1,
11356 
              'must_be_hdl_vector' => 1,
11357 
              'period' => 1,
11358 
              'port_id' => 0,
11359 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
11360 
              'type' => 'Bool',
11361 
            },
11362 
            'direction' => 'out',
11363 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11364 
            'width' => 1,
11365 
          },
11366 
          'to_register3_dout' => {
11367 
            'attributes' => {
11368 
              'bin_pt' => 0,
11369 
              'is_floating_block' => 1,
11370 
              'must_be_hdl_vector' => 1,
11371 
              'period' => 1,
11372 
              'port_id' => 0,
11373 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
11374 
              'type' => 'Bool',
11375 
            },
11376 
            'direction' => 'in',
11377 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11378 
            'width' => 1,
11379 
          },
11380 
          'to_register3_en' => {
11381 
            'attributes' => {
11382 
              'bin_pt' => 0,
11383 
              'is_floating_block' => 1,
11384 
              'must_be_hdl_vector' => 1,
11385 
              'period' => 1,
11386 
              'port_id' => 1,
11387 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
11388 
              'type' => 'Bool',
11389 
            },
11390 
            'direction' => 'out',
11391 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11392 
            'width' => 1,
11393 
          },
11394 
          'to_register4_ce' => {
11395 
            'attributes' => {
11396 
              'domain' => '',
11397 
              'group' => 1,
11398 
              'isCe' => 1,
11399 
              'is_floating_block' => 1,
11400 
              'period' => 1,
11401 
              'type' => 'logic',
11402 
            },
11403 
            'direction' => 'out',
11404 
            'hdlType' => 'std_logic',
11405 
            'width' => 1,
11406 
          },
11407 
          'to_register4_clk' => {
11408 
            'attributes' => {
11409 
              'domain' => '',
11410 
              'group' => 1,
11411 
              'isClk' => 1,
11412 
              'is_floating_block' => 1,
11413 
              'period' => 1,
11414 
              'type' => 'logic',
11415 
            },
11416 
            'direction' => 'out',
11417 
            'hdlType' => 'std_logic',
11418 
            'width' => 1,
11419 
          },
11420 
          'to_register4_clr' => {
11421 
            'attributes' => {
11422 
              'domain' => '',
11423 
              'group' => 1,
11424 
              'isClr' => 1,
11425 
              'is_floating_block' => 1,
11426 
              'period' => 1,
11427 
              'type' => 'logic',
11428 
              'valid_bit_used' => 0,
11429 
            },
11430 
            'direction' => 'out',
11431 
            'hdlType' => 'std_logic',
11432 
            'width' => 1,
11433 
          },
11434 
          'to_register4_data_in' => {
11435 
            'attributes' => {
11436 
              'bin_pt' => 0,
11437 
              'is_floating_block' => 1,
11438 
              'must_be_hdl_vector' => 1,
11439 
              'period' => 1,
11440 
              'port_id' => 0,
11441 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
11442 
              'type' => 'Bool',
11443 
            },
11444 
            'direction' => 'out',
11445 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11446 
            'width' => 1,
11447 
          },
11448 
          'to_register4_dout' => {
11449 
            'attributes' => {
11450 
              'bin_pt' => 0,
11451 
              'is_floating_block' => 1,
11452 
              'must_be_hdl_vector' => 1,
11453 
              'period' => 1,
11454 
              'port_id' => 0,
11455 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
11456 
              'type' => 'Bool',
11457 
            },
11458 
            'direction' => 'in',
11459 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11460 
            'width' => 1,
11461 
          },
11462 
          'to_register4_en' => {
11463 
            'attributes' => {
11464 
              'bin_pt' => 0,
11465 
              'is_floating_block' => 1,
11466 
              'must_be_hdl_vector' => 1,
11467 
              'period' => 1,
11468 
              'port_id' => 1,
11469 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
11470 
              'type' => 'Bool',
11471 
            },
11472 
            'direction' => 'out',
11473 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11474 
            'width' => 1,
11475 
          },
11476 
          'to_register5_ce' => {
11477 
            'attributes' => {
11478 
              'domain' => '',
11479 
              'group' => 1,
11480 
              'isCe' => 1,
11481 
              'is_floating_block' => 1,
11482 
              'period' => 1,
11483 
              'type' => 'logic',
11484 
            },
11485 
            'direction' => 'out',
11486 
            'hdlType' => 'std_logic',
11487 
            'width' => 1,
11488 
          },
11489 
          'to_register5_clk' => {
11490 
            'attributes' => {
11491 
              'domain' => '',
11492 
              'group' => 1,
11493 
              'isClk' => 1,
11494 
              'is_floating_block' => 1,
11495 
              'period' => 1,
11496 
              'type' => 'logic',
11497 
            },
11498 
            'direction' => 'out',
11499 
            'hdlType' => 'std_logic',
11500 
            'width' => 1,
11501 
          },
11502 
          'to_register5_clr' => {
11503 
            'attributes' => {
11504 
              'domain' => '',
11505 
              'group' => 1,
11506 
              'isClr' => 1,
11507 
              'is_floating_block' => 1,
11508 
              'period' => 1,
11509 
              'type' => 'logic',
11510 
              'valid_bit_used' => 0,
11511 
            },
11512 
            'direction' => 'out',
11513 
            'hdlType' => 'std_logic',
11514 
            'width' => 1,
11515 
          },
11516 
          'to_register5_data_in' => {
11517 
            'attributes' => {
11518 
              'bin_pt' => 0,
11519 
              'is_floating_block' => 1,
11520 
              'must_be_hdl_vector' => 1,
11521 
              'period' => 1,
11522 
              'port_id' => 0,
11523 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
11524 
              'type' => 'UFix_32_0',
11525 
            },
11526 
            'direction' => 'out',
11527 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11528 
            'width' => 32,
11529 
          },
11530 
          'to_register5_dout' => {
11531 
            'attributes' => {
11532 
              'bin_pt' => 0,
11533 
              'is_floating_block' => 1,
11534 
              'must_be_hdl_vector' => 1,
11535 
              'period' => 1,
11536 
              'port_id' => 0,
11537 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
11538 
              'type' => 'UFix_32_0',
11539 
            },
11540 
            'direction' => 'in',
11541 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11542 
            'width' => 32,
11543 
          },
11544 
          'to_register5_en' => {
11545 
            'attributes' => {
11546 
              'bin_pt' => 0,
11547 
              'is_floating_block' => 1,
11548 
              'must_be_hdl_vector' => 1,
11549 
              'period' => 1,
11550 
              'port_id' => 1,
11551 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
11552 
              'type' => 'Bool',
11553 
            },
11554 
            'direction' => 'out',
11555 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11556 
            'width' => 1,
11557 
          },
11558 
          'to_register6_ce' => {
11559 
            'attributes' => {
11560 
              'domain' => '',
11561 
              'group' => 1,
11562 
              'isCe' => 1,
11563 
              'is_floating_block' => 1,
11564 
              'period' => 1,
11565 
              'type' => 'logic',
11566 
            },
11567 
            'direction' => 'out',
11568 
            'hdlType' => 'std_logic',
11569 
            'width' => 1,
11570 
          },
11571 
          'to_register6_clk' => {
11572 
            'attributes' => {
11573 
              'domain' => '',
11574 
              'group' => 1,
11575 
              'isClk' => 1,
11576 
              'is_floating_block' => 1,
11577 
              'period' => 1,
11578 
              'type' => 'logic',
11579 
            },
11580 
            'direction' => 'out',
11581 
            'hdlType' => 'std_logic',
11582 
            'width' => 1,
11583 
          },
11584 
          'to_register6_clr' => {
11585 
            'attributes' => {
11586 
              'domain' => '',
11587 
              'group' => 1,
11588 
              'isClr' => 1,
11589 
              'is_floating_block' => 1,
11590 
              'period' => 1,
11591 
              'type' => 'logic',
11592 
              'valid_bit_used' => 0,
11593 
            },
11594 
            'direction' => 'out',
11595 
            'hdlType' => 'std_logic',
11596 
            'width' => 1,
11597 
          },
11598 
          'to_register6_data_in' => {
11599 
            'attributes' => {
11600 
              'bin_pt' => 0,
11601 
              'is_floating_block' => 1,
11602 
              'must_be_hdl_vector' => 1,
11603 
              'period' => 1,
11604 
              'port_id' => 0,
11605 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
11606 
              'type' => 'UFix_32_0',
11607 
            },
11608 
            'direction' => 'out',
11609 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11610 
            'width' => 32,
11611 
          },
11612 
          'to_register6_dout' => {
11613 
            'attributes' => {
11614 
              'bin_pt' => 0,
11615 
              'is_floating_block' => 1,
11616 
              'must_be_hdl_vector' => 1,
11617 
              'period' => 1,
11618 
              'port_id' => 0,
11619 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
11620 
              'type' => 'UFix_32_0',
11621 
            },
11622 
            'direction' => 'in',
11623 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11624 
            'width' => 32,
11625 
          },
11626 
          'to_register6_en' => {
11627 
            'attributes' => {
11628 
              'bin_pt' => 0,
11629 
              'is_floating_block' => 1,
11630 
              'must_be_hdl_vector' => 1,
11631 
              'period' => 1,
11632 
              'port_id' => 1,
11633 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
11634 
              'type' => 'Bool',
11635 
            },
11636 
            'direction' => 'out',
11637 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11638 
            'width' => 1,
11639 
          },
11640 
          'to_register7_ce' => {
11641 
            'attributes' => {
11642 
              'domain' => '',
11643 
              'group' => 1,
11644 
              'isCe' => 1,
11645 
              'is_floating_block' => 1,
11646 
              'period' => 1,
11647 
              'type' => 'logic',
11648 
            },
11649 
            'direction' => 'out',
11650 
            'hdlType' => 'std_logic',
11651 
            'width' => 1,
11652 
          },
11653 
          'to_register7_clk' => {
11654 
            'attributes' => {
11655 
              'domain' => '',
11656 
              'group' => 1,
11657 
              'isClk' => 1,
11658 
              'is_floating_block' => 1,
11659 
              'period' => 1,
11660 
              'type' => 'logic',
11661 
            },
11662 
            'direction' => 'out',
11663 
            'hdlType' => 'std_logic',
11664 
            'width' => 1,
11665 
          },
11666 
          'to_register7_clr' => {
11667 
            'attributes' => {
11668 
              'domain' => '',
11669 
              'group' => 1,
11670 
              'isClr' => 1,
11671 
              'is_floating_block' => 1,
11672 
              'period' => 1,
11673 
              'type' => 'logic',
11674 
              'valid_bit_used' => 0,
11675 
            },
11676 
            'direction' => 'out',
11677 
            'hdlType' => 'std_logic',
11678 
            'width' => 1,
11679 
          },
11680 
          'to_register7_data_in' => {
11681 
            'attributes' => {
11682 
              'bin_pt' => 0,
11683 
              'is_floating_block' => 1,
11684 
              'must_be_hdl_vector' => 1,
11685 
              'period' => 1,
11686 
              'port_id' => 0,
11687 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
11688 
              'type' => 'UFix_32_0',
11689 
            },
11690 
            'direction' => 'out',
11691 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11692 
            'width' => 32,
11693 
          },
11694 
          'to_register7_dout' => {
11695 
            'attributes' => {
11696 
              'bin_pt' => 0,
11697 
              'is_floating_block' => 1,
11698 
              'must_be_hdl_vector' => 1,
11699 
              'period' => 1,
11700 
              'port_id' => 0,
11701 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
11702 
              'type' => 'UFix_32_0',
11703 
            },
11704 
            'direction' => 'in',
11705 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11706 
            'width' => 32,
11707 
          },
11708 
          'to_register7_en' => {
11709 
            'attributes' => {
11710 
              'bin_pt' => 0,
11711 
              'is_floating_block' => 1,
11712 
              'must_be_hdl_vector' => 1,
11713 
              'period' => 1,
11714 
              'port_id' => 1,
11715 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
11716 
              'type' => 'Bool',
11717 
            },
11718 
            'direction' => 'out',
11719 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11720 
            'width' => 1,
11721 
          },
11722 
          'to_register8_ce' => {
11723 
            'attributes' => {
11724 
              'domain' => '',
11725 
              'group' => 1,
11726 
              'isCe' => 1,
11727 
              'is_floating_block' => 1,
11728 
              'period' => 1,
11729 
              'type' => 'logic',
11730 
            },
11731 
            'direction' => 'out',
11732 
            'hdlType' => 'std_logic',
11733 
            'width' => 1,
11734 
          },
11735 
          'to_register8_clk' => {
11736 
            'attributes' => {
11737 
              'domain' => '',
11738 
              'group' => 1,
11739 
              'isClk' => 1,
11740 
              'is_floating_block' => 1,
11741 
              'period' => 1,
11742 
              'type' => 'logic',
11743 
            },
11744 
            'direction' => 'out',
11745 
            'hdlType' => 'std_logic',
11746 
            'width' => 1,
11747 
          },
11748 
          'to_register8_clr' => {
11749 
            'attributes' => {
11750 
              'domain' => '',
11751 
              'group' => 1,
11752 
              'isClr' => 1,
11753 
              'is_floating_block' => 1,
11754 
              'period' => 1,
11755 
              'type' => 'logic',
11756 
              'valid_bit_used' => 0,
11757 
            },
11758 
            'direction' => 'out',
11759 
            'hdlType' => 'std_logic',
11760 
            'width' => 1,
11761 
          },
11762 
          'to_register8_data_in' => {
11763 
            'attributes' => {
11764 
              'bin_pt' => 0,
11765 
              'is_floating_block' => 1,
11766 
              'must_be_hdl_vector' => 1,
11767 
              'period' => 1,
11768 
              'port_id' => 0,
11769 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
11770 
              'type' => 'Bool',
11771 
            },
11772 
            'direction' => 'out',
11773 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11774 
            'width' => 1,
11775 
          },
11776 
          'to_register8_dout' => {
11777 
            'attributes' => {
11778 
              'bin_pt' => 0,
11779 
              'is_floating_block' => 1,
11780 
              'must_be_hdl_vector' => 1,
11781 
              'period' => 1,
11782 
              'port_id' => 0,
11783 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
11784 
              'type' => 'Bool',
11785 
            },
11786 
            'direction' => 'in',
11787 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11788 
            'width' => 1,
11789 
          },
11790 
          'to_register8_en' => {
11791 
            'attributes' => {
11792 
              'bin_pt' => 0,
11793 
              'is_floating_block' => 1,
11794 
              'must_be_hdl_vector' => 1,
11795 
              'period' => 1,
11796 
              'port_id' => 1,
11797 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
11798 
              'type' => 'Bool',
11799 
            },
11800 
            'direction' => 'out',
11801 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11802 
            'width' => 1,
11803 
          },
11804 
          'to_register9_ce' => {
11805 
            'attributes' => {
11806 
              'domain' => '',
11807 
              'group' => 1,
11808 
              'isCe' => 1,
11809 
              'is_floating_block' => 1,
11810 
              'period' => 1,
11811 
              'type' => 'logic',
11812 
            },
11813 
            'direction' => 'out',
11814 
            'hdlType' => 'std_logic',
11815 
            'width' => 1,
11816 
          },
11817 
          'to_register9_clk' => {
11818 
            'attributes' => {
11819 
              'domain' => '',
11820 
              'group' => 1,
11821 
              'isClk' => 1,
11822 
              'is_floating_block' => 1,
11823 
              'period' => 1,
11824 
              'type' => 'logic',
11825 
            },
11826 
            'direction' => 'out',
11827 
            'hdlType' => 'std_logic',
11828 
            'width' => 1,
11829 
          },
11830 
          'to_register9_clr' => {
11831 
            'attributes' => {
11832 
              'domain' => '',
11833 
              'group' => 1,
11834 
              'isClr' => 1,
11835 
              'is_floating_block' => 1,
11836 
              'period' => 1,
11837 
              'type' => 'logic',
11838 
              'valid_bit_used' => 0,
11839 
            },
11840 
            'direction' => 'out',
11841 
            'hdlType' => 'std_logic',
11842 
            'width' => 1,
11843 
          },
11844 
          'to_register9_data_in' => {
11845 
            'attributes' => {
11846 
              'bin_pt' => 0,
11847 
              'is_floating_block' => 1,
11848 
              'must_be_hdl_vector' => 1,
11849 
              'period' => 1,
11850 
              'port_id' => 0,
11851 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
11852 
              'type' => 'UFix_32_0',
11853 
            },
11854 
            'direction' => 'out',
11855 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11856 
            'width' => 32,
11857 
          },
11858 
          'to_register9_dout' => {
11859 
            'attributes' => {
11860 
              'bin_pt' => 0,
11861 
              'is_floating_block' => 1,
11862 
              'must_be_hdl_vector' => 1,
11863 
              'period' => 1,
11864 
              'port_id' => 0,
11865 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
11866 
              'type' => 'UFix_32_0',
11867 
            },
11868 
            'direction' => 'in',
11869 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11870 
            'width' => 32,
11871 
          },
11872 
          'to_register9_en' => {
11873 
            'attributes' => {
11874 
              'bin_pt' => 0,
11875 
              'is_floating_block' => 1,
11876 
              'must_be_hdl_vector' => 1,
11877 
              'period' => 1,
11878 
              'port_id' => 1,
11879 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11880 
              'type' => 'Bool',
11881 
            },
11882 
            'direction' => 'out',
11883 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11884 
            'width' => 1,
11885 
          },
11886 
        },
11887 
        'subblocks' => {
11888 
          'default_clock_driver_x0' => {
11889 
            'connections' => {
11890 
              'ce_1' => 'ce_1_sg',
11891 
              'clk_1' => 'clk_1_sg',
11892 
              'sysce' => [
11893 
                'constant',
11894 
                '\'1\'',
11895 
              ],
11896 
              'sysce_clr' => [
11897 
                'constant',
11898 
                '\'0\'',
11899 
              ],
11900 
              'sysclk' => 'clkNet',
11901 
            },
11902 
            'entity' => {
11903 
              'attributes' => {
11904 
                'domain' => 'default',
11905 
                'hdlArchAttributes' => [
11906 
                  [
11907 
                    'syn_noprune',
11908 
                    'boolean',
11909 
                    'true',
11910 
                  ],
11911 
                  [
11912 
                    'optimize_primitives',
11913 
                    'boolean',
11914 
                    'false',
11915 
                  ],
11916 
                  [
11917 
                    'dont_touch',
11918 
                    'boolean',
11919 
                    'true',
11920 
                  ],
11921 
                ],
11922 
                'hdlEntityAttributes' => [
11923 
                ],
11924 
                'isClkDriver' => 1,
11925 
              },
11926 
              'entityName' => 'default_clock_driver',
11927 
              'ports' => {
11928 
                'ce_1' => {
11929 
                  'attributes' => {
11930 
                    'domain' => 'default',
11931 
                    'group' => 1,
11932 
                    'isCe' => 1,
11933 
                    'period' => 1,
11934 
                    'type' => 'logic',
11935 
                  },
11936 
                  'direction' => 'out',
11937 
                  'hdlType' => 'std_logic',
11938 
                  'width' => 1,
11939 
                },
11940 
                'clk_1' => {
11941 
                  'attributes' => {
11942 
                    'domain' => 'default',
11943 
                    'group' => 1,
11944 
                    'isClk' => 1,
11945 
                    'period' => 1,
11946 
                    'type' => 'logic',
11947 
                  },
11948 
                  'direction' => 'out',
11949 
                  'hdlType' => 'std_logic',
11950 
                  'width' => 1,
11951 
                },
11952 
                'sysce' => {
11953 
                  'attributes' => {
11954 
                    'group' => 4,
11955 
                    'isCe' => 1,
11956 
                    'period' => 1,
11957 
                  },
11958 
                  'direction' => 'in',
11959 
                  'hdlType' => 'std_logic',
11960 
                  'width' => 1,
11961 
                },
11962 
                'sysce_clr' => {
11963 
                  'attributes' => {
11964 
                    'group' => 4,
11965 
                    'isClr' => 1,
11966 
                    'period' => 1,
11967 
                  },
11968 
                  'direction' => 'in',
11969 
                  'hdlType' => 'std_logic',
11970 
                  'width' => 1,
11971 
                },
11972 
                'sysclk' => {
11973 
                  'attributes' => {
11974 
                    'group' => 4,
11975 
                    'isClk' => 1,
11976 
                    'period' => 1,
11977 
                  },
11978 
                  'direction' => 'in',
11979 
                  'hdlType' => 'std_logic',
11980 
                  'width' => 1,
11981 
                },
11982 
              },
11983 
            },
11984 
            'entityName' => 'default_clock_driver',
11985 
          },
11986 
          'inout_logic_x0' => {
11987 
            'connections' => {
11988 
              'data_in' => 'debug_in_2i_net_x0',
11989 
              'data_in_x0' => 'reg04_tv_net_x0',
11990 
              'data_in_x1' => 'reg04_td_net_x0',
11991 
              'data_in_x10' => 'debug_in_3i_net_x0',
11992 
              'data_in_x11' => 'debug_in_4i_net_x0',
11993 
              'data_in_x12' => 'reg09_tv_net_x0',
11994 
              'data_in_x13' => 'reg09_td_net_x0',
11995 
              'data_in_x14' => 'reg10_tv_net_x0',
11996 
              'data_in_x15' => 'reg10_td_net_x0',
11997 
              'data_in_x16' => 'reg08_tv_net_x0',
11998 
              'data_in_x17' => 'reg08_td_net_x0',
11999 
              'data_in_x18' => 'reg11_tv_net_x0',
12000 
              'data_in_x19' => 'reg11_td_net_x0',
12001 
              'data_in_x2' => 'reg05_tv_net_x0',
12002 
              'data_in_x20' => 'reg12_tv_net_x0',
12003 
              'data_in_x21' => 'reg01_tv_net_x0',
12004 
              'data_in_x22' => 'reg12_td_net_x0',
12005 
              'data_in_x23' => 'reg13_tv_net_x0',
12006 
              'data_in_x24' => 'reg13_td_net_x0',
12007 
              'data_in_x25' => 'reg14_tv_net_x0',
12008 
              'data_in_x26' => 'reg14_td_net_x0',
12009 
              'data_in_x27' => 'reg02_tv_net_x0',
12010 
              'data_in_x28' => 'reg02_td_net_x0',
12011 
              'data_in_x29' => 'debug_in_1i_net_x0',
12012 
              'data_in_x3' => 'reg05_td_net_x0',
12013 
              'data_in_x30' => 'reg01_td_net_x0',
12014 
              'data_in_x31' => 'reg03_tv_net_x0',
12015 
              'data_in_x32' => 'reg03_td_net_x0',
12016 
              'data_in_x4' => 'reg06_tv_net_x0',
12017 
              'data_in_x5' => 'reg06_td_net_x0',
12018 
              'data_in_x6' => 'reg07_tv_net_x0',
12019 
              'data_in_x7' => 'reg07_td_net_x0',
12020 
              'data_in_x8' => 'dma_host2board_busy_net_x0',
12021 
              'data_in_x9' => 'dma_host2board_done_net_x0',
12022 
              'data_out' => 'from_register1_data_out_net',
12023 
              'data_out_x0' => 'from_register10_data_out_net',
12024 
              'data_out_x1' => 'from_register11_data_out_net',
12025 
              'data_out_x10' => 'from_register2_data_out_net',
12026 
              'data_out_x11' => 'from_register20_data_out_net',
12027 
              'data_out_x12' => 'from_register21_data_out_net',
12028 
              'data_out_x13' => 'from_register22_data_out_net',
12029 
              'data_out_x14' => 'from_register23_data_out_net',
12030 
              'data_out_x15' => 'from_register24_data_out_net',
12031 
              'data_out_x16' => 'from_register25_data_out_net',
12032 
              'data_out_x17' => 'from_register26_data_out_net',
12033 
              'data_out_x18' => 'from_register27_data_out_net',
12034 
              'data_out_x19' => 'from_register28_data_out_net',
12035 
              'data_out_x2' => 'from_register12_data_out_net',
12036 
              'data_out_x20' => 'from_register3_data_out_net',
12037 
              'data_out_x21' => 'from_register4_data_out_net',
12038 
              'data_out_x22' => 'from_register5_data_out_net',
12039 
              'data_out_x23' => 'from_register6_data_out_net',
12040 
              'data_out_x24' => 'from_register7_data_out_net',
12041 
              'data_out_x25' => 'from_register8_data_out_net',
12042 
              'data_out_x26' => 'from_register9_data_out_net',
12043 
              'data_out_x3' => 'from_register13_data_out_net',
12044 
              'data_out_x4' => 'from_register14_data_out_net',
12045 
              'data_out_x5' => 'from_register15_data_out_net',
12046 
              'data_out_x6' => 'from_register16_data_out_net',
12047 
              'data_out_x7' => 'from_register17_data_out_net',
12048 
              'data_out_x8' => 'from_register18_data_out_net',
12049 
              'data_out_x9' => 'from_register19_data_out_net',
12050 
              'debug_in_1i' => 'debug_in_1i_net',
12051 
              'debug_in_2i' => 'debug_in_2i_net',
12052 
              'debug_in_3i' => 'debug_in_3i_net',
12053 
              'debug_in_4i' => 'debug_in_4i_net',
12054 
              'dma_host2board_busy' => 'dma_host2board_busy_net',
12055 
              'dma_host2board_done' => 'dma_host2board_done_net',
12056 
              'en' => 'constant5_op_net_x0',
12057 
              'en_x0' => 'constant5_op_net_x1',
12058 
              'en_x1' => 'constant5_op_net_x2',
12059 
              'en_x10' => 'constant5_op_net_x11',
12060 
              'en_x11' => 'constant5_op_net_x12',
12061 
              'en_x12' => 'constant1_op_net_x0',
12062 
              'en_x13' => 'constant1_op_net_x1',
12063 
              'en_x14' => 'constant1_op_net_x2',
12064 
              'en_x15' => 'constant1_op_net_x3',
12065 
              'en_x16' => 'constant1_op_net_x4',
12066 
              'en_x17' => 'constant1_op_net_x5',
12067 
              'en_x18' => 'constant1_op_net_x6',
12068 
              'en_x19' => 'constant1_op_net_x7',
12069 
              'en_x2' => 'constant5_op_net_x3',
12070 
              'en_x20' => 'constant1_op_net_x8',
12071 
              'en_x21' => 'constant5_op_net_x13',
12072 
              'en_x22' => 'constant1_op_net_x9',
12073 
              'en_x23' => 'constant1_op_net_x10',
12074 
              'en_x24' => 'constant1_op_net_x11',
12075 
              'en_x25' => 'constant1_op_net_x12',
12076 
              'en_x26' => 'constant1_op_net_x13',
12077 
              'en_x27' => 'constant5_op_net_x14',
12078 
              'en_x28' => 'constant5_op_net_x15',
12079 
              'en_x29' => 'constant5_op_net_x16',
12080 
              'en_x3' => 'constant5_op_net_x4',
12081 
              'en_x30' => 'constant5_op_net_x17',
12082 
              'en_x31' => 'constant5_op_net_x18',
12083 
              'en_x32' => 'constant5_op_net_x19',
12084 
              'en_x4' => 'constant5_op_net_x5',
12085 
              'en_x5' => 'constant5_op_net_x6',
12086 
              'en_x6' => 'constant5_op_net_x7',
12087 
              'en_x7' => 'constant5_op_net_x8',
12088 
              'en_x8' => 'constant5_op_net_x9',
12089 
              'en_x9' => 'constant5_op_net_x10',
12090 
              'reg01_rd' => 'from_register3_data_out_net_x0',
12091 
              'reg01_rv' => 'from_register1_data_out_net_x0',
12092 
              'reg01_td' => 'reg01_td_net',
12093 
              'reg01_tv' => 'reg01_tv_net',
12094 
              'reg02_rd' => 'from_register5_data_out_net_x0',
12095 
              'reg02_rv' => 'from_register2_data_out_net_x0',
12096 
              'reg02_td' => 'reg02_td_net',
12097 
              'reg02_tv' => 'reg02_tv_net',
12098 
              'reg03_rd' => 'from_register7_data_out_net_x0',
12099 
              'reg03_rv' => 'from_register6_data_out_net_x0',
12100 
              'reg03_td' => 'reg03_td_net',
12101 
              'reg03_tv' => 'reg03_tv_net',
12102 
              'reg04_rd' => 'from_register8_data_out_net_x0',
12103 
              'reg04_rv' => 'from_register4_data_out_net_x0',
12104 
              'reg04_td' => 'reg04_td_net',
12105 
              'reg04_tv' => 'reg04_tv_net',
12106 
              'reg05_rd' => 'from_register10_data_out_net_x0',
12107 
              'reg05_rv' => 'from_register9_data_out_net_x0',
12108 
              'reg05_td' => 'reg05_td_net',
12109 
              'reg05_tv' => 'reg05_tv_net',
12110 
              'reg06_rd' => 'from_register11_data_out_net_x0',
12111 
              'reg06_rv' => 'from_register12_data_out_net_x0',
12112 
              'reg06_td' => 'reg06_td_net',
12113 
              'reg06_tv' => 'reg06_tv_net',
12114 
              'reg07_rd' => 'from_register13_data_out_net_x0',
12115 
              'reg07_rv' => 'from_register14_data_out_net_x0',
12116 
              'reg07_td' => 'reg07_td_net',
12117 
              'reg07_tv' => 'reg07_tv_net',
12118 
              'reg08_rd' => 'from_register15_data_out_net_x0',
12119 
              'reg08_rv' => 'from_register16_data_out_net_x0',
12120 
              'reg08_td' => 'reg08_td_net',
12121 
              'reg08_tv' => 'reg08_tv_net',
12122 
              'reg09_rd' => 'from_register17_data_out_net_x0',
12123 
              'reg09_rv' => 'from_register18_data_out_net_x0',
12124 
              'reg09_td' => 'reg09_td_net',
12125 
              'reg09_tv' => 'reg09_tv_net',
12126 
              'reg10_rd' => 'from_register19_data_out_net_x0',
12127 
              'reg10_rv' => 'from_register20_data_out_net_x0',
12128 
              'reg10_td' => 'reg10_td_net',
12129 
              'reg10_tv' => 'reg10_tv_net',
12130 
              'reg11_rd' => 'from_register21_data_out_net_x0',
12131 
              'reg11_rv' => 'from_register22_data_out_net_x0',
12132 
              'reg11_td' => 'reg11_td_net',
12133 
              'reg11_tv' => 'reg11_tv_net',
12134 
              'reg12_rd' => 'from_register23_data_out_net_x0',
12135 
              'reg12_rv' => 'from_register24_data_out_net_x0',
12136 
              'reg12_td' => 'reg12_td_net',
12137 
              'reg12_tv' => 'reg12_tv_net',
12138 
              'reg13_rd' => 'from_register25_data_out_net_x0',
12139 
              'reg13_rv' => 'from_register26_data_out_net_x0',
12140 
              'reg13_td' => 'reg13_td_net',
12141 
              'reg13_tv' => 'reg13_tv_net',
12142 
              'reg14_rd' => 'from_register27_data_out_net_x0',
12143 
              'reg14_rv' => 'from_register28_data_out_net_x0',
12144 
              'reg14_td' => 'reg14_td_net',
12145 
              'reg14_tv' => 'reg14_tv_net',
12146 
            },
12147 
            'entity' => {
12148 
              'attributes' => {
12149 
                'entityAlreadyNetlisted' => 1,
12150 
                'hdlKind' => 'vhdl',
12151 
                'isDesign' => 1,
12152 
                'simulinkName' => 'INOUT_LOGIC',
12153 
              },
12154 
              'entityName' => 'inout_logic',
12155 
              'ports' => {
12156 
                'data_in' => {
12157 
                  'attributes' => {
12158 
                    'bin_pt' => 0,
12159 
                    'is_floating_block' => 1,
12160 
                    'must_be_hdl_vector' => 1,
12161 
                    'period' => 1,
12162 
                    'port_id' => 0,
12163 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12164 
                    'type' => 'UFix_32_0',
12165 
                  },
12166 
                  'direction' => 'out',
12167 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12168 
                  'width' => 32,
12169 
                },
12170 
                'data_in_x0' => {
12171 
                  'attributes' => {
12172 
                    'bin_pt' => 0,
12173 
                    'is_floating_block' => 1,
12174 
                    'must_be_hdl_vector' => 1,
12175 
                    'period' => 1,
12176 
                    'port_id' => 0,
12177 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12178 
                    'type' => 'Bool',
12179 
                  },
12180 
                  'direction' => 'out',
12181 
                  'hdlType' => 'std_logic',
12182 
                  'width' => 1,
12183 
                },
12184 
                'data_in_x1' => {
12185 
                  'attributes' => {
12186 
                    'bin_pt' => 0,
12187 
                    'is_floating_block' => 1,
12188 
                    'must_be_hdl_vector' => 1,
12189 
                    'period' => 1,
12190 
                    'port_id' => 0,
12191 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12192 
                    'type' => 'UFix_32_0',
12193 
                  },
12194 
                  'direction' => 'out',
12195 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12196 
                  'width' => 32,
12197 
                },
12198 
                'data_in_x10' => {
12199 
                  'attributes' => {
12200 
                    'bin_pt' => 0,
12201 
                    'is_floating_block' => 1,
12202 
                    'must_be_hdl_vector' => 1,
12203 
                    'period' => 1,
12204 
                    'port_id' => 0,
12205 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12206 
                    'type' => 'UFix_32_0',
12207 
                  },
12208 
                  'direction' => 'out',
12209 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12210 
                  'width' => 32,
12211 
                },
12212 
                'data_in_x11' => {
12213 
                  'attributes' => {
12214 
                    'bin_pt' => 0,
12215 
                    'is_floating_block' => 1,
12216 
                    'must_be_hdl_vector' => 1,
12217 
                    'period' => 1,
12218 
                    'port_id' => 0,
12219 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12220 
                    'type' => 'UFix_32_0',
12221 
                  },
12222 
                  'direction' => 'out',
12223 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12224 
                  'width' => 32,
12225 
                },
12226 
                'data_in_x12' => {
12227 
                  'attributes' => {
12228 
                    'bin_pt' => 0,
12229 
                    'is_floating_block' => 1,
12230 
                    'must_be_hdl_vector' => 1,
12231 
                    'period' => 1,
12232 
                    'port_id' => 0,
12233 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12234 
                    'type' => 'Bool',
12235 
                  },
12236 
                  'direction' => 'out',
12237 
                  'hdlType' => 'std_logic',
12238 
                  'width' => 1,
12239 
                },
12240 
                'data_in_x13' => {
12241 
                  'attributes' => {
12242 
                    'bin_pt' => 0,
12243 
                    'is_floating_block' => 1,
12244 
                    'must_be_hdl_vector' => 1,
12245 
                    'period' => 1,
12246 
                    'port_id' => 0,
12247 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12248 
                    'type' => 'UFix_32_0',
12249 
                  },
12250 
                  'direction' => 'out',
12251 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12252 
                  'width' => 32,
12253 
                },
12254 
                'data_in_x14' => {
12255 
                  'attributes' => {
12256 
                    'bin_pt' => 0,
12257 
                    'is_floating_block' => 1,
12258 
                    'must_be_hdl_vector' => 1,
12259 
                    'period' => 1,
12260 
                    'port_id' => 0,
12261 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12262 
                    'type' => 'Bool',
12263 
                  },
12264 
                  'direction' => 'out',
12265 
                  'hdlType' => 'std_logic',
12266 
                  'width' => 1,
12267 
                },
12268 
                'data_in_x15' => {
12269 
                  'attributes' => {
12270 
                    'bin_pt' => 0,
12271 
                    'is_floating_block' => 1,
12272 
                    'must_be_hdl_vector' => 1,
12273 
                    'period' => 1,
12274 
                    'port_id' => 0,
12275 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12276 
                    'type' => 'UFix_32_0',
12277 
                  },
12278 
                  'direction' => 'out',
12279 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12280 
                  'width' => 32,
12281 
                },
12282 
                'data_in_x16' => {
12283 
                  'attributes' => {
12284 
                    'bin_pt' => 0,
12285 
                    'is_floating_block' => 1,
12286 
                    'must_be_hdl_vector' => 1,
12287 
                    'period' => 1,
12288 
                    'port_id' => 0,
12289 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12290 
                    'type' => 'Bool',
12291 
                  },
12292 
                  'direction' => 'out',
12293 
                  'hdlType' => 'std_logic',
12294 
                  'width' => 1,
12295 
                },
12296 
                'data_in_x17' => {
12297 
                  'attributes' => {
12298 
                    'bin_pt' => 0,
12299 
                    'is_floating_block' => 1,
12300 
                    'must_be_hdl_vector' => 1,
12301 
                    'period' => 1,
12302 
                    'port_id' => 0,
12303 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12304 
                    'type' => 'UFix_32_0',
12305 
                  },
12306 
                  'direction' => 'out',
12307 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12308 
                  'width' => 32,
12309 
                },
12310 
                'data_in_x18' => {
12311 
                  'attributes' => {
12312 
                    'bin_pt' => 0,
12313 
                    'is_floating_block' => 1,
12314 
                    'must_be_hdl_vector' => 1,
12315 
                    'period' => 1,
12316 
                    'port_id' => 0,
12317 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12318 
                    'type' => 'Bool',
12319 
                  },
12320 
                  'direction' => 'out',
12321 
                  'hdlType' => 'std_logic',
12322 
                  'width' => 1,
12323 
                },
12324 
                'data_in_x19' => {
12325 
                  'attributes' => {
12326 
                    'bin_pt' => 0,
12327 
                    'is_floating_block' => 1,
12328 
                    'must_be_hdl_vector' => 1,
12329 
                    'period' => 1,
12330 
                    'port_id' => 0,
12331 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12332 
                    'type' => 'UFix_32_0',
12333 
                  },
12334 
                  'direction' => 'out',
12335 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12336 
                  'width' => 32,
12337 
                },
12338 
                'data_in_x2' => {
12339 
                  'attributes' => {
12340 
                    'bin_pt' => 0,
12341 
                    'is_floating_block' => 1,
12342 
                    'must_be_hdl_vector' => 1,
12343 
                    'period' => 1,
12344 
                    'port_id' => 0,
12345 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12346 
                    'type' => 'Bool',
12347 
                  },
12348 
                  'direction' => 'out',
12349 
                  'hdlType' => 'std_logic',
12350 
                  'width' => 1,
12351 
                },
12352 
                'data_in_x20' => {
12353 
                  'attributes' => {
12354 
                    'bin_pt' => 0,
12355 
                    'is_floating_block' => 1,
12356 
                    'must_be_hdl_vector' => 1,
12357 
                    'period' => 1,
12358 
                    'port_id' => 0,
12359 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12360 
                    'type' => 'Bool',
12361 
                  },
12362 
                  'direction' => 'out',
12363 
                  'hdlType' => 'std_logic',
12364 
                  'width' => 1,
12365 
                },
12366 
                'data_in_x21' => {
12367 
                  'attributes' => {
12368 
                    'bin_pt' => 0,
12369 
                    'is_floating_block' => 1,
12370 
                    'must_be_hdl_vector' => 1,
12371 
                    'period' => 1,
12372 
                    'port_id' => 0,
12373 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12374 
                    'type' => 'Bool',
12375 
                  },
12376 
                  'direction' => 'out',
12377 
                  'hdlType' => 'std_logic',
12378 
                  'width' => 1,
12379 
                },
12380 
                'data_in_x22' => {
12381 
                  'attributes' => {
12382 
                    'bin_pt' => 0,
12383 
                    'is_floating_block' => 1,
12384 
                    'must_be_hdl_vector' => 1,
12385 
                    'period' => 1,
12386 
                    'port_id' => 0,
12387 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12388 
                    'type' => 'UFix_32_0',
12389 
                  },
12390 
                  'direction' => 'out',
12391 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12392 
                  'width' => 32,
12393 
                },
12394 
                'data_in_x23' => {
12395 
                  'attributes' => {
12396 
                    'bin_pt' => 0,
12397 
                    'is_floating_block' => 1,
12398 
                    'must_be_hdl_vector' => 1,
12399 
                    'period' => 1,
12400 
                    'port_id' => 0,
12401 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12402 
                    'type' => 'Bool',
12403 
                  },
12404 
                  'direction' => 'out',
12405 
                  'hdlType' => 'std_logic',
12406 
                  'width' => 1,
12407 
                },
12408 
                'data_in_x24' => {
12409 
                  'attributes' => {
12410 
                    'bin_pt' => 0,
12411 
                    'is_floating_block' => 1,
12412 
                    'must_be_hdl_vector' => 1,
12413 
                    'period' => 1,
12414 
                    'port_id' => 0,
12415 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12416 
                    'type' => 'UFix_32_0',
12417 
                  },
12418 
                  'direction' => 'out',
12419 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12420 
                  'width' => 32,
12421 
                },
12422 
                'data_in_x25' => {
12423 
                  'attributes' => {
12424 
                    'bin_pt' => 0,
12425 
                    'is_floating_block' => 1,
12426 
                    'must_be_hdl_vector' => 1,
12427 
                    'period' => 1,
12428 
                    'port_id' => 0,
12429 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12430 
                    'type' => 'Bool',
12431 
                  },
12432 
                  'direction' => 'out',
12433 
                  'hdlType' => 'std_logic',
12434 
                  'width' => 1,
12435 
                },
12436 
                'data_in_x26' => {
12437 
                  'attributes' => {
12438 
                    'bin_pt' => 0,
12439 
                    'is_floating_block' => 1,
12440 
                    'must_be_hdl_vector' => 1,
12441 
                    'period' => 1,
12442 
                    'port_id' => 0,
12443 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12444 
                    'type' => 'UFix_32_0',
12445 
                  },
12446 
                  'direction' => 'out',
12447 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12448 
                  'width' => 32,
12449 
                },
12450 
                'data_in_x27' => {
12451 
                  'attributes' => {
12452 
                    'bin_pt' => 0,
12453 
                    'is_floating_block' => 1,
12454 
                    'must_be_hdl_vector' => 1,
12455 
                    'period' => 1,
12456 
                    'port_id' => 0,
12457 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12458 
                    'type' => 'Bool',
12459 
                  },
12460 
                  'direction' => 'out',
12461 
                  'hdlType' => 'std_logic',
12462 
                  'width' => 1,
12463 
                },
12464 
                'data_in_x28' => {
12465 
                  'attributes' => {
12466 
                    'bin_pt' => 0,
12467 
                    'is_floating_block' => 1,
12468 
                    'must_be_hdl_vector' => 1,
12469 
                    'period' => 1,
12470 
                    'port_id' => 0,
12471 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12472 
                    'type' => 'UFix_32_0',
12473 
                  },
12474 
                  'direction' => 'out',
12475 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12476 
                  'width' => 32,
12477 
                },
12478 
                'data_in_x29' => {
12479 
                  'attributes' => {
12480 
                    'bin_pt' => 0,
12481 
                    'is_floating_block' => 1,
12482 
                    'must_be_hdl_vector' => 1,
12483 
                    'period' => 1,
12484 
                    'port_id' => 0,
12485 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12486 
                    'type' => 'UFix_32_0',
12487 
                  },
12488 
                  'direction' => 'out',
12489 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12490 
                  'width' => 32,
12491 
                },
12492 
                'data_in_x3' => {
12493 
                  'attributes' => {
12494 
                    'bin_pt' => 0,
12495 
                    'is_floating_block' => 1,
12496 
                    'must_be_hdl_vector' => 1,
12497 
                    'period' => 1,
12498 
                    'port_id' => 0,
12499 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12500 
                    'type' => 'UFix_32_0',
12501 
                  },
12502 
                  'direction' => 'out',
12503 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12504 
                  'width' => 32,
12505 
                },
12506 
                'data_in_x30' => {
12507 
                  'attributes' => {
12508 
                    'bin_pt' => 0,
12509 
                    'is_floating_block' => 1,
12510 
                    'must_be_hdl_vector' => 1,
12511 
                    'period' => 1,
12512 
                    'port_id' => 0,
12513 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12514 
                    'type' => 'UFix_32_0',
12515 
                  },
12516 
                  'direction' => 'out',
12517 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12518 
                  'width' => 32,
12519 
                },
12520 
                'data_in_x31' => {
12521 
                  'attributes' => {
12522 
                    'bin_pt' => 0,
12523 
                    'is_floating_block' => 1,
12524 
                    'must_be_hdl_vector' => 1,
12525 
                    'period' => 1,
12526 
                    'port_id' => 0,
12527 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12528 
                    'type' => 'Bool',
12529 
                  },
12530 
                  'direction' => 'out',
12531 
                  'hdlType' => 'std_logic',
12532 
                  'width' => 1,
12533 
                },
12534 
                'data_in_x32' => {
12535 
                  'attributes' => {
12536 
                    'bin_pt' => 0,
12537 
                    'is_floating_block' => 1,
12538 
                    'must_be_hdl_vector' => 1,
12539 
                    'period' => 1,
12540 
                    'port_id' => 0,
12541 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12542 
                    'type' => 'UFix_32_0',
12543 
                  },
12544 
                  'direction' => 'out',
12545 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12546 
                  'width' => 32,
12547 
                },
12548 
                'data_in_x4' => {
12549 
                  'attributes' => {
12550 
                    'bin_pt' => 0,
12551 
                    'is_floating_block' => 1,
12552 
                    'must_be_hdl_vector' => 1,
12553 
                    'period' => 1,
12554 
                    'port_id' => 0,
12555 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12556 
                    'type' => 'Bool',
12557 
                  },
12558 
                  'direction' => 'out',
12559 
                  'hdlType' => 'std_logic',
12560 
                  'width' => 1,
12561 
                },
12562 
                'data_in_x5' => {
12563 
                  'attributes' => {
12564 
                    'bin_pt' => 0,
12565 
                    'is_floating_block' => 1,
12566 
                    'must_be_hdl_vector' => 1,
12567 
                    'period' => 1,
12568 
                    'port_id' => 0,
12569 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12570 
                    'type' => 'UFix_32_0',
12571 
                  },
12572 
                  'direction' => 'out',
12573 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12574 
                  'width' => 32,
12575 
                },
12576 
                'data_in_x6' => {
12577 
                  'attributes' => {
12578 
                    'bin_pt' => 0,
12579 
                    'is_floating_block' => 1,
12580 
                    'must_be_hdl_vector' => 1,
12581 
                    'period' => 1,
12582 
                    'port_id' => 0,
12583 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12584 
                    'type' => 'Bool',
12585 
                  },
12586 
                  'direction' => 'out',
12587 
                  'hdlType' => 'std_logic',
12588 
                  'width' => 1,
12589 
                },
12590 
                'data_in_x7' => {
12591 
                  'attributes' => {
12592 
                    'bin_pt' => 0,
12593 
                    'is_floating_block' => 1,
12594 
                    'must_be_hdl_vector' => 1,
12595 
                    'period' => 1,
12596 
                    'port_id' => 0,
12597 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12598 
                    'type' => 'UFix_32_0',
12599 
                  },
12600 
                  'direction' => 'out',
12601 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12602 
                  'width' => 32,
12603 
                },
12604 
                'data_in_x8' => {
12605 
                  'attributes' => {
12606 
                    'bin_pt' => 0,
12607 
                    'is_floating_block' => 1,
12608 
                    'must_be_hdl_vector' => 1,
12609 
                    'period' => 1,
12610 
                    'port_id' => 0,
12611 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12612 
                    'type' => 'UFix_1_0',
12613 
                  },
12614 
                  'direction' => 'out',
12615 
                  'hdlType' => 'std_logic',
12616 
                  'width' => 1,
12617 
                },
12618 
                'data_in_x9' => {
12619 
                  'attributes' => {
12620 
                    'bin_pt' => 0,
12621 
                    'is_floating_block' => 1,
12622 
                    'must_be_hdl_vector' => 1,
12623 
                    'period' => 1,
12624 
                    'port_id' => 0,
12625 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
12626 
                    'type' => 'UFix_1_0',
12627 
                  },
12628 
                  'direction' => 'out',
12629 
                  'hdlType' => 'std_logic',
12630 
                  'width' => 1,
12631 
                },
12632 
                'data_out' => {
12633 
                  'attributes' => {
12634 
                    'bin_pt' => 0,
12635 
                    'is_floating_block' => 1,
12636 
                    'must_be_hdl_vector' => 1,
12637 
                    'period' => 1,
12638 
                    'port_id' => 0,
12639 
                    'simulinkName' => 'INOUT_LOGIC/From Register1',
12640 
                    'type' => 'UFix_1_0',
12641 
                  },
12642 
                  'direction' => 'in',
12643 
                  'hdlType' => 'std_logic',
12644 
                  'width' => 1,
12645 
                },
12646 
                'data_out_x0' => {
12647 
                  'attributes' => {
12648 
                    'bin_pt' => 0,
12649 
                    'is_floating_block' => 1,
12650 
                    'must_be_hdl_vector' => 1,
12651 
                    'period' => 1,
12652 
                    'port_id' => 0,
12653 
                    'simulinkName' => 'INOUT_LOGIC/From Register10',
12654 
                    'type' => 'UFix_32_0',
12655 
                  },
12656 
                  'direction' => 'in',
12657 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12658 
                  'width' => 32,
12659 
                },
12660 
                'data_out_x1' => {
12661 
                  'attributes' => {
12662 
                    'bin_pt' => 0,
12663 
                    'is_floating_block' => 1,
12664 
                    'must_be_hdl_vector' => 1,
12665 
                    'period' => 1,
12666 
                    'port_id' => 0,
12667 
                    'simulinkName' => 'INOUT_LOGIC/From Register11',
12668 
                    'type' => 'UFix_32_0',
12669 
                  },
12670 
                  'direction' => 'in',
12671 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12672 
                  'width' => 32,
12673 
                },
12674 
                'data_out_x10' => {
12675 
                  'attributes' => {
12676 
                    'bin_pt' => 0,
12677 
                    'is_floating_block' => 1,
12678 
                    'must_be_hdl_vector' => 1,
12679 
                    'period' => 1,
12680 
                    'port_id' => 0,
12681 
                    'simulinkName' => 'INOUT_LOGIC/From Register2',
12682 
                    'type' => 'UFix_1_0',
12683 
                  },
12684 
                  'direction' => 'in',
12685 
                  'hdlType' => 'std_logic',
12686 
                  'width' => 1,
12687 
                },
12688 
                'data_out_x11' => {
12689 
                  'attributes' => {
12690 
                    'bin_pt' => 0,
12691 
                    'is_floating_block' => 1,
12692 
                    'must_be_hdl_vector' => 1,
12693 
                    'period' => 1,
12694 
                    'port_id' => 0,
12695 
                    'simulinkName' => 'INOUT_LOGIC/From Register20',
12696 
                    'type' => 'UFix_1_0',
12697 
                  },
12698 
                  'direction' => 'in',
12699 
                  'hdlType' => 'std_logic',
12700 
                  'width' => 1,
12701 
                },
12702 
                'data_out_x12' => {
12703 
                  'attributes' => {
12704 
                    'bin_pt' => 0,
12705 
                    'is_floating_block' => 1,
12706 
                    'must_be_hdl_vector' => 1,
12707 
                    'period' => 1,
12708 
                    'port_id' => 0,
12709 
                    'simulinkName' => 'INOUT_LOGIC/From Register21',
12710 
                    'type' => 'UFix_32_0',
12711 
                  },
12712 
                  'direction' => 'in',
12713 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12714 
                  'width' => 32,
12715 
                },
12716 
                'data_out_x13' => {
12717 
                  'attributes' => {
12718 
                    'bin_pt' => 0,
12719 
                    'is_floating_block' => 1,
12720 
                    'must_be_hdl_vector' => 1,
12721 
                    'period' => 1,
12722 
                    'port_id' => 0,
12723 
                    'simulinkName' => 'INOUT_LOGIC/From Register22',
12724 
                    'type' => 'UFix_1_0',
12725 
                  },
12726 
                  'direction' => 'in',
12727 
                  'hdlType' => 'std_logic',
12728 
                  'width' => 1,
12729 
                },
12730 
                'data_out_x14' => {
12731 
                  'attributes' => {
12732 
                    'bin_pt' => 0,
12733 
                    'is_floating_block' => 1,
12734 
                    'must_be_hdl_vector' => 1,
12735 
                    'period' => 1,
12736 
                    'port_id' => 0,
12737 
                    'simulinkName' => 'INOUT_LOGIC/From Register23',
12738 
                    'type' => 'UFix_32_0',
12739 
                  },
12740 
                  'direction' => 'in',
12741 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12742 
                  'width' => 32,
12743 
                },
12744 
                'data_out_x15' => {
12745 
                  'attributes' => {
12746 
                    'bin_pt' => 0,
12747 
                    'is_floating_block' => 1,
12748 
                    'must_be_hdl_vector' => 1,
12749 
                    'period' => 1,
12750 
                    'port_id' => 0,
12751 
                    'simulinkName' => 'INOUT_LOGIC/From Register24',
12752 
                    'type' => 'UFix_1_0',
12753 
                  },
12754 
                  'direction' => 'in',
12755 
                  'hdlType' => 'std_logic',
12756 
                  'width' => 1,
12757 
                },
12758 
                'data_out_x16' => {
12759 
                  'attributes' => {
12760 
                    'bin_pt' => 0,
12761 
                    'is_floating_block' => 1,
12762 
                    'must_be_hdl_vector' => 1,
12763 
                    'period' => 1,
12764 
                    'port_id' => 0,
12765 
                    'simulinkName' => 'INOUT_LOGIC/From Register25',
12766 
                    'type' => 'UFix_32_0',
12767 
                  },
12768 
                  'direction' => 'in',
12769 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12770 
                  'width' => 32,
12771 
                },
12772 
                'data_out_x17' => {
12773 
                  'attributes' => {
12774 
                    'bin_pt' => 0,
12775 
                    'is_floating_block' => 1,
12776 
                    'must_be_hdl_vector' => 1,
12777 
                    'period' => 1,
12778 
                    'port_id' => 0,
12779 
                    'simulinkName' => 'INOUT_LOGIC/From Register26',
12780 
                    'type' => 'UFix_1_0',
12781 
                  },
12782 
                  'direction' => 'in',
12783 
                  'hdlType' => 'std_logic',
12784 
                  'width' => 1,
12785 
                },
12786 
                'data_out_x18' => {
12787 
                  'attributes' => {
12788 
                    'bin_pt' => 0,
12789 
                    'is_floating_block' => 1,
12790 
                    'must_be_hdl_vector' => 1,
12791 
                    'period' => 1,
12792 
                    'port_id' => 0,
12793 
                    'simulinkName' => 'INOUT_LOGIC/From Register27',
12794 
                    'type' => 'UFix_32_0',
12795 
                  },
12796 
                  'direction' => 'in',
12797 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12798 
                  'width' => 32,
12799 
                },
12800 
                'data_out_x19' => {
12801 
                  'attributes' => {
12802 
                    'bin_pt' => 0,
12803 
                    'is_floating_block' => 1,
12804 
                    'must_be_hdl_vector' => 1,
12805 
                    'period' => 1,
12806 
                    'port_id' => 0,
12807 
                    'simulinkName' => 'INOUT_LOGIC/From Register28',
12808 
                    'type' => 'UFix_1_0',
12809 
                  },
12810 
                  'direction' => 'in',
12811 
                  'hdlType' => 'std_logic',
12812 
                  'width' => 1,
12813 
                },
12814 
                'data_out_x2' => {
12815 
                  'attributes' => {
12816 
                    'bin_pt' => 0,
12817 
                    'is_floating_block' => 1,
12818 
                    'must_be_hdl_vector' => 1,
12819 
                    'period' => 1,
12820 
                    'port_id' => 0,
12821 
                    'simulinkName' => 'INOUT_LOGIC/From Register12',
12822 
                    'type' => 'UFix_1_0',
12823 
                  },
12824 
                  'direction' => 'in',
12825 
                  'hdlType' => 'std_logic',
12826 
                  'width' => 1,
12827 
                },
12828 
                'data_out_x20' => {
12829 
                  'attributes' => {
12830 
                    'bin_pt' => 0,
12831 
                    'is_floating_block' => 1,
12832 
                    'must_be_hdl_vector' => 1,
12833 
                    'period' => 1,
12834 
                    'port_id' => 0,
12835 
                    'simulinkName' => 'INOUT_LOGIC/From Register3',
12836 
                    'type' => 'UFix_32_0',
12837 
                  },
12838 
                  'direction' => 'in',
12839 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12840 
                  'width' => 32,
12841 
                },
12842 
                'data_out_x21' => {
12843 
                  'attributes' => {
12844 
                    'bin_pt' => 0,
12845 
                    'is_floating_block' => 1,
12846 
                    'must_be_hdl_vector' => 1,
12847 
                    'period' => 1,
12848 
                    'port_id' => 0,
12849 
                    'simulinkName' => 'INOUT_LOGIC/From Register4',
12850 
                    'type' => 'UFix_1_0',
12851 
                  },
12852 
                  'direction' => 'in',
12853 
                  'hdlType' => 'std_logic',
12854 
                  'width' => 1,
12855 
                },
12856 
                'data_out_x22' => {
12857 
                  'attributes' => {
12858 
                    'bin_pt' => 0,
12859 
                    'is_floating_block' => 1,
12860 
                    'must_be_hdl_vector' => 1,
12861 
                    'period' => 1,
12862 
                    'port_id' => 0,
12863 
                    'simulinkName' => 'INOUT_LOGIC/From Register5',
12864 
                    'type' => 'UFix_32_0',
12865 
                  },
12866 
                  'direction' => 'in',
12867 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12868 
                  'width' => 32,
12869 
                },
12870 
                'data_out_x23' => {
12871 
                  'attributes' => {
12872 
                    'bin_pt' => 0,
12873 
                    'is_floating_block' => 1,
12874 
                    'must_be_hdl_vector' => 1,
12875 
                    'period' => 1,
12876 
                    'port_id' => 0,
12877 
                    'simulinkName' => 'INOUT_LOGIC/From Register6',
12878 
                    'type' => 'UFix_1_0',
12879 
                  },
12880 
                  'direction' => 'in',
12881 
                  'hdlType' => 'std_logic',
12882 
                  'width' => 1,
12883 
                },
12884 
                'data_out_x24' => {
12885 
                  'attributes' => {
12886 
                    'bin_pt' => 0,
12887 
                    'is_floating_block' => 1,
12888 
                    'must_be_hdl_vector' => 1,
12889 
                    'period' => 1,
12890 
                    'port_id' => 0,
12891 
                    'simulinkName' => 'INOUT_LOGIC/From Register7',
12892 
                    'type' => 'UFix_32_0',
12893 
                  },
12894 
                  'direction' => 'in',
12895 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12896 
                  'width' => 32,
12897 
                },
12898 
                'data_out_x25' => {
12899 
                  'attributes' => {
12900 
                    'bin_pt' => 0,
12901 
                    'is_floating_block' => 1,
12902 
                    'must_be_hdl_vector' => 1,
12903 
                    'period' => 1,
12904 
                    'port_id' => 0,
12905 
                    'simulinkName' => 'INOUT_LOGIC/From Register8',
12906 
                    'type' => 'UFix_32_0',
12907 
                  },
12908 
                  'direction' => 'in',
12909 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12910 
                  'width' => 32,
12911 
                },
12912 
                'data_out_x26' => {
12913 
                  'attributes' => {
12914 
                    'bin_pt' => 0,
12915 
                    'is_floating_block' => 1,
12916 
                    'must_be_hdl_vector' => 1,
12917 
                    'period' => 1,
12918 
                    'port_id' => 0,
12919 
                    'simulinkName' => 'INOUT_LOGIC/From Register9',
12920 
                    'type' => 'UFix_1_0',
12921 
                  },
12922 
                  'direction' => 'in',
12923 
                  'hdlType' => 'std_logic',
12924 
                  'width' => 1,
12925 
                },
12926 
                'data_out_x3' => {
12927 
                  'attributes' => {
12928 
                    'bin_pt' => 0,
12929 
                    'is_floating_block' => 1,
12930 
                    'must_be_hdl_vector' => 1,
12931 
                    'period' => 1,
12932 
                    'port_id' => 0,
12933 
                    'simulinkName' => 'INOUT_LOGIC/From Register13',
12934 
                    'type' => 'UFix_32_0',
12935 
                  },
12936 
                  'direction' => 'in',
12937 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12938 
                  'width' => 32,
12939 
                },
12940 
                'data_out_x4' => {
12941 
                  'attributes' => {
12942 
                    'bin_pt' => 0,
12943 
                    'is_floating_block' => 1,
12944 
                    'must_be_hdl_vector' => 1,
12945 
                    'period' => 1,
12946 
                    'port_id' => 0,
12947 
                    'simulinkName' => 'INOUT_LOGIC/From Register14',
12948 
                    'type' => 'UFix_1_0',
12949 
                  },
12950 
                  'direction' => 'in',
12951 
                  'hdlType' => 'std_logic',
12952 
                  'width' => 1,
12953 
                },
12954 
                'data_out_x5' => {
12955 
                  'attributes' => {
12956 
                    'bin_pt' => 0,
12957 
                    'is_floating_block' => 1,
12958 
                    'must_be_hdl_vector' => 1,
12959 
                    'period' => 1,
12960 
                    'port_id' => 0,
12961 
                    'simulinkName' => 'INOUT_LOGIC/From Register15',
12962 
                    'type' => 'UFix_32_0',
12963 
                  },
12964 
                  'direction' => 'in',
12965 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12966 
                  'width' => 32,
12967 
                },
12968 
                'data_out_x6' => {
12969 
                  'attributes' => {
12970 
                    'bin_pt' => 0,
12971 
                    'is_floating_block' => 1,
12972 
                    'must_be_hdl_vector' => 1,
12973 
                    'period' => 1,
12974 
                    'port_id' => 0,
12975 
                    'simulinkName' => 'INOUT_LOGIC/From Register16',
12976 
                    'type' => 'UFix_1_0',
12977 
                  },
12978 
                  'direction' => 'in',
12979 
                  'hdlType' => 'std_logic',
12980 
                  'width' => 1,
12981 
                },
12982 
                'data_out_x7' => {
12983 
                  'attributes' => {
12984 
                    'bin_pt' => 0,
12985 
                    'is_floating_block' => 1,
12986 
                    'must_be_hdl_vector' => 1,
12987 
                    'period' => 1,
12988 
                    'port_id' => 0,
12989 
                    'simulinkName' => 'INOUT_LOGIC/From Register17',
12990 
                    'type' => 'UFix_32_0',
12991 
                  },
12992 
                  'direction' => 'in',
12993 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12994 
                  'width' => 32,
12995 
                },
12996 
                'data_out_x8' => {
12997 
                  'attributes' => {
12998 
                    'bin_pt' => 0,
12999 
                    'is_floating_block' => 1,
13000 
                    'must_be_hdl_vector' => 1,
13001 
                    'period' => 1,
13002 
                    'port_id' => 0,
13003 
                    'simulinkName' => 'INOUT_LOGIC/From Register18',
13004 
                    'type' => 'UFix_1_0',
13005 
                  },
13006 
                  'direction' => 'in',
13007 
                  'hdlType' => 'std_logic',
13008 
                  'width' => 1,
13009 
                },
13010 
                'data_out_x9' => {
13011 
                  'attributes' => {
13012 
                    'bin_pt' => 0,
13013 
                    'is_floating_block' => 1,
13014 
                    'must_be_hdl_vector' => 1,
13015 
                    'period' => 1,
13016 
                    'port_id' => 0,
13017 
                    'simulinkName' => 'INOUT_LOGIC/From Register19',
13018 
                    'type' => 'UFix_32_0',
13019 
                  },
13020 
                  'direction' => 'in',
13021 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13022 
                  'width' => 32,
13023 
                },
13024 
                'debug_in_1i' => {
13025 
                  'attributes' => {
13026 
                    'bin_pt' => 0,
13027 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_1i.dat',
13028 
                    'is_floating_block' => 1,
13029 
                    'is_gateway_port' => 1,
13030 
                    'must_be_hdl_vector' => 1,
13031 
                    'period' => 1,
13032 
                    'port_id' => 0,
13033 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_1i',
13034 
                    'source_block' => 'INOUT_LOGIC',
13035 
                    'timingConstraint' => 'none',
13036 
                    'type' => 'UFix_32_0',
13037 
                  },
13038 
                  'direction' => 'in',
13039 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13040 
                  'width' => 32,
13041 
                },
13042 
                'debug_in_2i' => {
13043 
                  'attributes' => {
13044 
                    'bin_pt' => 0,
13045 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_2i.dat',
13046 
                    'is_floating_block' => 1,
13047 
                    'is_gateway_port' => 1,
13048 
                    'must_be_hdl_vector' => 1,
13049 
                    'period' => 1,
13050 
                    'port_id' => 0,
13051 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_2i',
13052 
                    'source_block' => 'INOUT_LOGIC',
13053 
                    'timingConstraint' => 'none',
13054 
                    'type' => 'UFix_32_0',
13055 
                  },
13056 
                  'direction' => 'in',
13057 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13058 
                  'width' => 32,
13059 
                },
13060 
                'debug_in_3i' => {
13061 
                  'attributes' => {
13062 
                    'bin_pt' => 0,
13063 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_3i.dat',
13064 
                    'is_floating_block' => 1,
13065 
                    'is_gateway_port' => 1,
13066 
                    'must_be_hdl_vector' => 1,
13067 
                    'period' => 1,
13068 
                    'port_id' => 0,
13069 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_3i',
13070 
                    'source_block' => 'INOUT_LOGIC',
13071 
                    'timingConstraint' => 'none',
13072 
                    'type' => 'UFix_32_0',
13073 
                  },
13074 
                  'direction' => 'in',
13075 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13076 
                  'width' => 32,
13077 
                },
13078 
                'debug_in_4i' => {
13079 
                  'attributes' => {
13080 
                    'bin_pt' => 0,
13081 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_debug_in_4i.dat',
13082 
                    'is_floating_block' => 1,
13083 
                    'is_gateway_port' => 1,
13084 
                    'must_be_hdl_vector' => 1,
13085 
                    'period' => 1,
13086 
                    'port_id' => 0,
13087 
                    'simulinkName' => 'INOUT_LOGIC/debug_in_4i',
13088 
                    'source_block' => 'INOUT_LOGIC',
13089 
                    'timingConstraint' => 'none',
13090 
                    'type' => 'UFix_32_0',
13091 
                  },
13092 
                  'direction' => 'in',
13093 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13094 
                  'width' => 32,
13095 
                },
13096 
                'dma_host2board_busy' => {
13097 
                  'attributes' => {
13098 
                    'bin_pt' => 0,
13099 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_busy.dat',
13100 
                    'is_floating_block' => 1,
13101 
                    'is_gateway_port' => 1,
13102 
                    'must_be_hdl_vector' => 1,
13103 
                    'period' => 1,
13104 
                    'port_id' => 0,
13105 
                    'simulinkName' => 'INOUT_LOGIC/DMA_Host2Board_Busy',
13106 
                    'source_block' => 'INOUT_LOGIC',
13107 
                    'timingConstraint' => 'none',
13108 
                    'type' => 'UFix_1_0',
13109 
                  },
13110 
                  'direction' => 'in',
13111 
                  'hdlType' => 'std_logic',
13112 
                  'width' => 1,
13113 
                },
13114 
                'dma_host2board_done' => {
13115 
                  'attributes' => {
13116 
                    'bin_pt' => 0,
13117 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_dma_host2board_done.dat',
13118 
                    'is_floating_block' => 1,
13119 
                    'is_gateway_port' => 1,
13120 
                    'must_be_hdl_vector' => 1,
13121 
                    'period' => 1,
13122 
                    'port_id' => 0,
13123 
                    'simulinkName' => 'INOUT_LOGIC/DMA_Host2Board_Done',
13124 
                    'source_block' => 'INOUT_LOGIC',
13125 
                    'timingConstraint' => 'none',
13126 
                    'type' => 'UFix_1_0',
13127 
                  },
13128 
                  'direction' => 'in',
13129 
                  'hdlType' => 'std_logic',
13130 
                  'width' => 1,
13131 
                },
13132 
                'en' => {
13133 
                  'attributes' => {
13134 
                    'bin_pt' => 0,
13135 
                    'is_floating_block' => 1,
13136 
                    'must_be_hdl_vector' => 1,
13137 
                    'period' => 1,
13138 
                    'port_id' => 0,
13139 
                    'simulinkName' => 'INOUT_LOGIC/en',
13140 
                    'type' => 'Bool',
13141 
                  },
13142 
                  'direction' => 'out',
13143 
                  'hdlType' => 'std_logic',
13144 
                  'width' => 1,
13145 
                },
13146 
                'en_x0' => {
13147 
                  'attributes' => {
13148 
                    'bin_pt' => 0,
13149 
                    'is_floating_block' => 1,
13150 
                    'must_be_hdl_vector' => 1,
13151 
                    'period' => 1,
13152 
                    'port_id' => 0,
13153 
                    'simulinkName' => 'INOUT_LOGIC/en',
13154 
                    'type' => 'Bool',
13155 
                  },
13156 
                  'direction' => 'out',
13157 
                  'hdlType' => 'std_logic',
13158 
                  'width' => 1,
13159 
                },
13160 
                'en_x1' => {
13161 
                  'attributes' => {
13162 
                    'bin_pt' => 0,
13163 
                    'is_floating_block' => 1,
13164 
                    'must_be_hdl_vector' => 1,
13165 
                    'period' => 1,
13166 
                    'port_id' => 0,
13167 
                    'simulinkName' => 'INOUT_LOGIC/en',
13168 
                    'type' => 'Bool',
13169 
                  },
13170 
                  'direction' => 'out',
13171 
                  'hdlType' => 'std_logic',
13172 
                  'width' => 1,
13173 
                },
13174 
                'en_x10' => {
13175 
                  'attributes' => {
13176 
                    'bin_pt' => 0,
13177 
                    'is_floating_block' => 1,
13178 
                    'must_be_hdl_vector' => 1,
13179 
                    'period' => 1,
13180 
                    'port_id' => 0,
13181 
                    'simulinkName' => 'INOUT_LOGIC/en',
13182 
                    'type' => 'Bool',
13183 
                  },
13184 
                  'direction' => 'out',
13185 
                  'hdlType' => 'std_logic',
13186 
                  'width' => 1,
13187 
                },
13188 
                'en_x11' => {
13189 
                  'attributes' => {
13190 
                    'bin_pt' => 0,
13191 
                    'is_floating_block' => 1,
13192 
                    'must_be_hdl_vector' => 1,
13193 
                    'period' => 1,
13194 
                    'port_id' => 0,
13195 
                    'simulinkName' => 'INOUT_LOGIC/en',
13196 
                    'type' => 'Bool',
13197 
                  },
13198 
                  'direction' => 'out',
13199 
                  'hdlType' => 'std_logic',
13200 
                  'width' => 1,
13201 
                },
13202 
                'en_x12' => {
13203 
                  'attributes' => {
13204 
                    'bin_pt' => 0,
13205 
                    'is_floating_block' => 1,
13206 
                    'must_be_hdl_vector' => 1,
13207 
                    'period' => 1,
13208 
                    'port_id' => 0,
13209 
                    'simulinkName' => 'INOUT_LOGIC/en',
13210 
                    'type' => 'Bool',
13211 
                  },
13212 
                  'direction' => 'out',
13213 
                  'hdlType' => 'std_logic',
13214 
                  'width' => 1,
13215 
                },
13216 
                'en_x13' => {
13217 
                  'attributes' => {
13218 
                    'bin_pt' => 0,
13219 
                    'is_floating_block' => 1,
13220 
                    'must_be_hdl_vector' => 1,
13221 
                    'period' => 1,
13222 
                    'port_id' => 0,
13223 
                    'simulinkName' => 'INOUT_LOGIC/en',
13224 
                    'type' => 'Bool',
13225 
                  },
13226 
                  'direction' => 'out',
13227 
                  'hdlType' => 'std_logic',
13228 
                  'width' => 1,
13229 
                },
13230 
                'en_x14' => {
13231 
                  'attributes' => {
13232 
                    'bin_pt' => 0,
13233 
                    'is_floating_block' => 1,
13234 
                    'must_be_hdl_vector' => 1,
13235 
                    'period' => 1,
13236 
                    'port_id' => 0,
13237 
                    'simulinkName' => 'INOUT_LOGIC/en',
13238 
                    'type' => 'Bool',
13239 
                  },
13240 
                  'direction' => 'out',
13241 
                  'hdlType' => 'std_logic',
13242 
                  'width' => 1,
13243 
                },
13244 
                'en_x15' => {
13245 
                  'attributes' => {
13246 
                    'bin_pt' => 0,
13247 
                    'is_floating_block' => 1,
13248 
                    'must_be_hdl_vector' => 1,
13249 
                    'period' => 1,
13250 
                    'port_id' => 0,
13251 
                    'simulinkName' => 'INOUT_LOGIC/en',
13252 
                    'type' => 'Bool',
13253 
                  },
13254 
                  'direction' => 'out',
13255 
                  'hdlType' => 'std_logic',
13256 
                  'width' => 1,
13257 
                },
13258 
                'en_x16' => {
13259 
                  'attributes' => {
13260 
                    'bin_pt' => 0,
13261 
                    'is_floating_block' => 1,
13262 
                    'must_be_hdl_vector' => 1,
13263 
                    'period' => 1,
13264 
                    'port_id' => 0,
13265 
                    'simulinkName' => 'INOUT_LOGIC/en',
13266 
                    'type' => 'Bool',
13267 
                  },
13268 
                  'direction' => 'out',
13269 
                  'hdlType' => 'std_logic',
13270 
                  'width' => 1,
13271 
                },
13272 
                'en_x17' => {
13273 
                  'attributes' => {
13274 
                    'bin_pt' => 0,
13275 
                    'is_floating_block' => 1,
13276 
                    'must_be_hdl_vector' => 1,
13277 
                    'period' => 1,
13278 
                    'port_id' => 0,
13279 
                    'simulinkName' => 'INOUT_LOGIC/en',
13280 
                    'type' => 'Bool',
13281 
                  },
13282 
                  'direction' => 'out',
13283 
                  'hdlType' => 'std_logic',
13284 
                  'width' => 1,
13285 
                },
13286 
                'en_x18' => {
13287 
                  'attributes' => {
13288 
                    'bin_pt' => 0,
13289 
                    'is_floating_block' => 1,
13290 
                    'must_be_hdl_vector' => 1,
13291 
                    'period' => 1,
13292 
                    'port_id' => 0,
13293 
                    'simulinkName' => 'INOUT_LOGIC/en',
13294 
                    'type' => 'Bool',
13295 
                  },
13296 
                  'direction' => 'out',
13297 
                  'hdlType' => 'std_logic',
13298 
                  'width' => 1,
13299 
                },
13300 
                'en_x19' => {
13301 
                  'attributes' => {
13302 
                    'bin_pt' => 0,
13303 
                    'is_floating_block' => 1,
13304 
                    'must_be_hdl_vector' => 1,
13305 
                    'period' => 1,
13306 
                    'port_id' => 0,
13307 
                    'simulinkName' => 'INOUT_LOGIC/en',
13308 
                    'type' => 'Bool',
13309 
                  },
13310 
                  'direction' => 'out',
13311 
                  'hdlType' => 'std_logic',
13312 
                  'width' => 1,
13313 
                },
13314 
                'en_x2' => {
13315 
                  'attributes' => {
13316 
                    'bin_pt' => 0,
13317 
                    'is_floating_block' => 1,
13318 
                    'must_be_hdl_vector' => 1,
13319 
                    'period' => 1,
13320 
                    'port_id' => 0,
13321 
                    'simulinkName' => 'INOUT_LOGIC/en',
13322 
                    'type' => 'Bool',
13323 
                  },
13324 
                  'direction' => 'out',
13325 
                  'hdlType' => 'std_logic',
13326 
                  'width' => 1,
13327 
                },
13328 
                'en_x20' => {
13329 
                  'attributes' => {
13330 
                    'bin_pt' => 0,
13331 
                    'is_floating_block' => 1,
13332 
                    'must_be_hdl_vector' => 1,
13333 
                    'period' => 1,
13334 
                    'port_id' => 0,
13335 
                    'simulinkName' => 'INOUT_LOGIC/en',
13336 
                    'type' => 'Bool',
13337 
                  },
13338 
                  'direction' => 'out',
13339 
                  'hdlType' => 'std_logic',
13340 
                  'width' => 1,
13341 
                },
13342 
                'en_x21' => {
13343 
                  'attributes' => {
13344 
                    'bin_pt' => 0,
13345 
                    'is_floating_block' => 1,
13346 
                    'must_be_hdl_vector' => 1,
13347 
                    'period' => 1,
13348 
                    'port_id' => 0,
13349 
                    'simulinkName' => 'INOUT_LOGIC/en',
13350 
                    'type' => 'Bool',
13351 
                  },
13352 
                  'direction' => 'out',
13353 
                  'hdlType' => 'std_logic',
13354 
                  'width' => 1,
13355 
                },
13356 
                'en_x22' => {
13357 
                  'attributes' => {
13358 
                    'bin_pt' => 0,
13359 
                    'is_floating_block' => 1,
13360 
                    'must_be_hdl_vector' => 1,
13361 
                    'period' => 1,
13362 
                    'port_id' => 0,
13363 
                    'simulinkName' => 'INOUT_LOGIC/en',
13364 
                    'type' => 'Bool',
13365 
                  },
13366 
                  'direction' => 'out',
13367 
                  'hdlType' => 'std_logic',
13368 
                  'width' => 1,
13369 
                },
13370 
                'en_x23' => {
13371 
                  'attributes' => {
13372 
                    'bin_pt' => 0,
13373 
                    'is_floating_block' => 1,
13374 
                    'must_be_hdl_vector' => 1,
13375 
                    'period' => 1,
13376 
                    'port_id' => 0,
13377 
                    'simulinkName' => 'INOUT_LOGIC/en',
13378 
                    'type' => 'Bool',
13379 
                  },
13380 
                  'direction' => 'out',
13381 
                  'hdlType' => 'std_logic',
13382 
                  'width' => 1,
13383 
                },
13384 
                'en_x24' => {
13385 
                  'attributes' => {
13386 
                    'bin_pt' => 0,
13387 
                    'is_floating_block' => 1,
13388 
                    'must_be_hdl_vector' => 1,
13389 
                    'period' => 1,
13390 
                    'port_id' => 0,
13391 
                    'simulinkName' => 'INOUT_LOGIC/en',
13392 
                    'type' => 'Bool',
13393 
                  },
13394 
                  'direction' => 'out',
13395 
                  'hdlType' => 'std_logic',
13396 
                  'width' => 1,
13397 
                },
13398 
                'en_x25' => {
13399 
                  'attributes' => {
13400 
                    'bin_pt' => 0,
13401 
                    'is_floating_block' => 1,
13402 
                    'must_be_hdl_vector' => 1,
13403 
                    'period' => 1,
13404 
                    'port_id' => 0,
13405 
                    'simulinkName' => 'INOUT_LOGIC/en',
13406 
                    'type' => 'Bool',
13407 
                  },
13408 
                  'direction' => 'out',
13409 
                  'hdlType' => 'std_logic',
13410 
                  'width' => 1,
13411 
                },
13412 
                'en_x26' => {
13413 
                  'attributes' => {
13414 
                    'bin_pt' => 0,
13415 
                    'is_floating_block' => 1,
13416 
                    'must_be_hdl_vector' => 1,
13417 
                    'period' => 1,
13418 
                    'port_id' => 0,
13419 
                    'simulinkName' => 'INOUT_LOGIC/en',
13420 
                    'type' => 'Bool',
13421 
                  },
13422 
                  'direction' => 'out',
13423 
                  'hdlType' => 'std_logic',
13424 
                  'width' => 1,
13425 
                },
13426 
                'en_x27' => {
13427 
                  'attributes' => {
13428 
                    'bin_pt' => 0,
13429 
                    'is_floating_block' => 1,
13430 
                    'must_be_hdl_vector' => 1,
13431 
                    'period' => 1,
13432 
                    'port_id' => 0,
13433 
                    'simulinkName' => 'INOUT_LOGIC/en',
13434 
                    'type' => 'Bool',
13435 
                  },
13436 
                  'direction' => 'out',
13437 
                  'hdlType' => 'std_logic',
13438 
                  'width' => 1,
13439 
                },
13440 
                'en_x28' => {
13441 
                  'attributes' => {
13442 
                    'bin_pt' => 0,
13443 
                    'is_floating_block' => 1,
13444 
                    'must_be_hdl_vector' => 1,
13445 
                    'period' => 1,
13446 
                    'port_id' => 0,
13447 
                    'simulinkName' => 'INOUT_LOGIC/en',
13448 
                    'type' => 'Bool',
13449 
                  },
13450 
                  'direction' => 'out',
13451 
                  'hdlType' => 'std_logic',
13452 
                  'width' => 1,
13453 
                },
13454 
                'en_x29' => {
13455 
                  'attributes' => {
13456 
                    'bin_pt' => 0,
13457 
                    'is_floating_block' => 1,
13458 
                    'must_be_hdl_vector' => 1,
13459 
                    'period' => 1,
13460 
                    'port_id' => 0,
13461 
                    'simulinkName' => 'INOUT_LOGIC/en',
13462 
                    'type' => 'Bool',
13463 
                  },
13464 
                  'direction' => 'out',
13465 
                  'hdlType' => 'std_logic',
13466 
                  'width' => 1,
13467 
                },
13468 
                'en_x3' => {
13469 
                  'attributes' => {
13470 
                    'bin_pt' => 0,
13471 
                    'is_floating_block' => 1,
13472 
                    'must_be_hdl_vector' => 1,
13473 
                    'period' => 1,
13474 
                    'port_id' => 0,
13475 
                    'simulinkName' => 'INOUT_LOGIC/en',
13476 
                    'type' => 'Bool',
13477 
                  },
13478 
                  'direction' => 'out',
13479 
                  'hdlType' => 'std_logic',
13480 
                  'width' => 1,
13481 
                },
13482 
                'en_x30' => {
13483 
                  'attributes' => {
13484 
                    'bin_pt' => 0,
13485 
                    'is_floating_block' => 1,
13486 
                    'must_be_hdl_vector' => 1,
13487 
                    'period' => 1,
13488 
                    'port_id' => 0,
13489 
                    'simulinkName' => 'INOUT_LOGIC/en',
13490 
                    'type' => 'Bool',
13491 
                  },
13492 
                  'direction' => 'out',
13493 
                  'hdlType' => 'std_logic',
13494 
                  'width' => 1,
13495 
                },
13496 
                'en_x31' => {
13497 
                  'attributes' => {
13498 
                    'bin_pt' => 0,
13499 
                    'is_floating_block' => 1,
13500 
                    'must_be_hdl_vector' => 1,
13501 
                    'period' => 1,
13502 
                    'port_id' => 0,
13503 
                    'simulinkName' => 'INOUT_LOGIC/en',
13504 
                    'type' => 'Bool',
13505 
                  },
13506 
                  'direction' => 'out',
13507 
                  'hdlType' => 'std_logic',
13508 
                  'width' => 1,
13509 
                },
13510 
                'en_x32' => {
13511 
                  'attributes' => {
13512 
                    'bin_pt' => 0,
13513 
                    'is_floating_block' => 1,
13514 
                    'must_be_hdl_vector' => 1,
13515 
                    'period' => 1,
13516 
                    'port_id' => 0,
13517 
                    'simulinkName' => 'INOUT_LOGIC/en',
13518 
                    'type' => 'Bool',
13519 
                  },
13520 
                  'direction' => 'out',
13521 
                  'hdlType' => 'std_logic',
13522 
                  'width' => 1,
13523 
                },
13524 
                'en_x4' => {
13525 
                  'attributes' => {
13526 
                    'bin_pt' => 0,
13527 
                    'is_floating_block' => 1,
13528 
                    'must_be_hdl_vector' => 1,
13529 
                    'period' => 1,
13530 
                    'port_id' => 0,
13531 
                    'simulinkName' => 'INOUT_LOGIC/en',
13532 
                    'type' => 'Bool',
13533 
                  },
13534 
                  'direction' => 'out',
13535 
                  'hdlType' => 'std_logic',
13536 
                  'width' => 1,
13537 
                },
13538 
                'en_x5' => {
13539 
                  'attributes' => {
13540 
                    'bin_pt' => 0,
13541 
                    'is_floating_block' => 1,
13542 
                    'must_be_hdl_vector' => 1,
13543 
                    'period' => 1,
13544 
                    'port_id' => 0,
13545 
                    'simulinkName' => 'INOUT_LOGIC/en',
13546 
                    'type' => 'Bool',
13547 
                  },
13548 
                  'direction' => 'out',
13549 
                  'hdlType' => 'std_logic',
13550 
                  'width' => 1,
13551 
                },
13552 
                'en_x6' => {
13553 
                  'attributes' => {
13554 
                    'bin_pt' => 0,
13555 
                    'is_floating_block' => 1,
13556 
                    'must_be_hdl_vector' => 1,
13557 
                    'period' => 1,
13558 
                    'port_id' => 0,
13559 
                    'simulinkName' => 'INOUT_LOGIC/en',
13560 
                    'type' => 'Bool',
13561 
                  },
13562 
                  'direction' => 'out',
13563 
                  'hdlType' => 'std_logic',
13564 
                  'width' => 1,
13565 
                },
13566 
                'en_x7' => {
13567 
                  'attributes' => {
13568 
                    'bin_pt' => 0,
13569 
                    'is_floating_block' => 1,
13570 
                    'must_be_hdl_vector' => 1,
13571 
                    'period' => 1,
13572 
                    'port_id' => 0,
13573 
                    'simulinkName' => 'INOUT_LOGIC/en',
13574 
                    'type' => 'Bool',
13575 
                  },
13576 
                  'direction' => 'out',
13577 
                  'hdlType' => 'std_logic',
13578 
                  'width' => 1,
13579 
                },
13580 
                'en_x8' => {
13581 
                  'attributes' => {
13582 
                    'bin_pt' => 0,
13583 
                    'is_floating_block' => 1,
13584 
                    'must_be_hdl_vector' => 1,
13585 
                    'period' => 1,
13586 
                    'port_id' => 0,
13587 
                    'simulinkName' => 'INOUT_LOGIC/en',
13588 
                    'type' => 'Bool',
13589 
                  },
13590 
                  'direction' => 'out',
13591 
                  'hdlType' => 'std_logic',
13592 
                  'width' => 1,
13593 
                },
13594 
                'en_x9' => {
13595 
                  'attributes' => {
13596 
                    'bin_pt' => 0,
13597 
                    'is_floating_block' => 1,
13598 
                    'must_be_hdl_vector' => 1,
13599 
                    'period' => 1,
13600 
                    'port_id' => 0,
13601 
                    'simulinkName' => 'INOUT_LOGIC/en',
13602 
                    'type' => 'Bool',
13603 
                  },
13604 
                  'direction' => 'out',
13605 
                  'hdlType' => 'std_logic',
13606 
                  'width' => 1,
13607 
                },
13608 
                'reg01_rd' => {
13609 
                  'attributes' => {
13610 
                    'bin_pt' => 0,
13611 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rd.dat',
13612 
                    'is_floating_block' => 1,
13613 
                    'is_gateway_port' => 1,
13614 
                    'must_be_hdl_vector' => 1,
13615 
                    'period' => 1,
13616 
                    'port_id' => 0,
13617 
                    'simulinkName' => 'INOUT_LOGIC/reg01_rd',
13618 
                    'source_block' => 'INOUT_LOGIC',
13619 
                    'timingConstraint' => 'none',
13620 
                    'type' => 'UFix_32_0',
13621 
                  },
13622 
                  'direction' => 'out',
13623 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13624 
                  'width' => 32,
13625 
                },
13626 
                'reg01_rv' => {
13627 
                  'attributes' => {
13628 
                    'bin_pt' => 0,
13629 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_rv.dat',
13630 
                    'is_floating_block' => 1,
13631 
                    'is_gateway_port' => 1,
13632 
                    'must_be_hdl_vector' => 1,
13633 
                    'period' => 1,
13634 
                    'port_id' => 0,
13635 
                    'simulinkName' => 'INOUT_LOGIC/reg01_rv',
13636 
                    'source_block' => 'INOUT_LOGIC',
13637 
                    'timingConstraint' => 'none',
13638 
                    'type' => 'UFix_1_0',
13639 
                  },
13640 
                  'direction' => 'out',
13641 
                  'hdlType' => 'std_logic',
13642 
                  'width' => 1,
13643 
                },
13644 
                'reg01_td' => {
13645 
                  'attributes' => {
13646 
                    'bin_pt' => 0,
13647 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_td.dat',
13648 
                    'is_floating_block' => 1,
13649 
                    'is_gateway_port' => 1,
13650 
                    'must_be_hdl_vector' => 1,
13651 
                    'period' => 1,
13652 
                    'port_id' => 0,
13653 
                    'simulinkName' => 'INOUT_LOGIC/reg01_td',
13654 
                    'source_block' => 'INOUT_LOGIC',
13655 
                    'timingConstraint' => 'none',
13656 
                    'type' => 'UFix_32_0',
13657 
                  },
13658 
                  'direction' => 'in',
13659 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13660 
                  'width' => 32,
13661 
                },
13662 
                'reg01_tv' => {
13663 
                  'attributes' => {
13664 
                    'bin_pt' => 0,
13665 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg01_tv.dat',
13666 
                    'is_floating_block' => 1,
13667 
                    'is_gateway_port' => 1,
13668 
                    'must_be_hdl_vector' => 1,
13669 
                    'period' => 1,
13670 
                    'port_id' => 0,
13671 
                    'simulinkName' => 'INOUT_LOGIC/reg01_tv',
13672 
                    'source_block' => 'INOUT_LOGIC',
13673 
                    'timingConstraint' => 'none',
13674 
                    'type' => 'Bool',
13675 
                  },
13676 
                  'direction' => 'in',
13677 
                  'hdlType' => 'std_logic',
13678 
                  'width' => 1,
13679 
                },
13680 
                'reg02_rd' => {
13681 
                  'attributes' => {
13682 
                    'bin_pt' => 0,
13683 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
13684 
                    'is_floating_block' => 1,
13685 
                    'is_gateway_port' => 1,
13686 
                    'must_be_hdl_vector' => 1,
13687 
                    'period' => 1,
13688 
                    'port_id' => 0,
13689 
                    'simulinkName' => 'INOUT_LOGIC/reg02_rd',
13690 
                    'source_block' => 'INOUT_LOGIC',
13691 
                    'timingConstraint' => 'none',
13692 
                    'type' => 'UFix_32_0',
13693 
                  },
13694 
                  'direction' => 'out',
13695 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13696 
                  'width' => 32,
13697 
                },
13698 
                'reg02_rv' => {
13699 
                  'attributes' => {
13700 
                    'bin_pt' => 0,
13701 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
13702 
                    'is_floating_block' => 1,
13703 
                    'is_gateway_port' => 1,
13704 
                    'must_be_hdl_vector' => 1,
13705 
                    'period' => 1,
13706 
                    'port_id' => 0,
13707 
                    'simulinkName' => 'INOUT_LOGIC/reg02_rv',
13708 
                    'source_block' => 'INOUT_LOGIC',
13709 
                    'timingConstraint' => 'none',
13710 
                    'type' => 'UFix_1_0',
13711 
                  },
13712 
                  'direction' => 'out',
13713 
                  'hdlType' => 'std_logic',
13714 
                  'width' => 1,
13715 
                },
13716 
                'reg02_td' => {
13717 
                  'attributes' => {
13718 
                    'bin_pt' => 0,
13719 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
13720 
                    'is_floating_block' => 1,
13721 
                    'is_gateway_port' => 1,
13722 
                    'must_be_hdl_vector' => 1,
13723 
                    'period' => 1,
13724 
                    'port_id' => 0,
13725 
                    'simulinkName' => 'INOUT_LOGIC/reg02_td',
13726 
                    'source_block' => 'INOUT_LOGIC',
13727 
                    'timingConstraint' => 'none',
13728 
                    'type' => 'UFix_32_0',
13729 
                  },
13730 
                  'direction' => 'in',
13731 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13732 
                  'width' => 32,
13733 
                },
13734 
                'reg02_tv' => {
13735 
                  'attributes' => {
13736 
                    'bin_pt' => 0,
13737 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
13738 
                    'is_floating_block' => 1,
13739 
                    'is_gateway_port' => 1,
13740 
                    'must_be_hdl_vector' => 1,
13741 
                    'period' => 1,
13742 
                    'port_id' => 0,
13743 
                    'simulinkName' => 'INOUT_LOGIC/reg02_tv',
13744 
                    'source_block' => 'INOUT_LOGIC',
13745 
                    'timingConstraint' => 'none',
13746 
                    'type' => 'Bool',
13747 
                  },
13748 
                  'direction' => 'in',
13749 
                  'hdlType' => 'std_logic',
13750 
                  'width' => 1,
13751 
                },
13752 
                'reg03_rd' => {
13753 
                  'attributes' => {
13754 
                    'bin_pt' => 0,
13755 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
13756 
                    'is_floating_block' => 1,
13757 
                    'is_gateway_port' => 1,
13758 
                    'must_be_hdl_vector' => 1,
13759 
                    'period' => 1,
13760 
                    'port_id' => 0,
13761 
                    'simulinkName' => 'INOUT_LOGIC/reg03_rd',
13762 
                    'source_block' => 'INOUT_LOGIC',
13763 
                    'timingConstraint' => 'none',
13764 
                    'type' => 'UFix_32_0',
13765 
                  },
13766 
                  'direction' => 'out',
13767 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13768 
                  'width' => 32,
13769 
                },
13770 
                'reg03_rv' => {
13771 
                  'attributes' => {
13772 
                    'bin_pt' => 0,
13773 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rv.dat',
13774 
                    'is_floating_block' => 1,
13775 
                    'is_gateway_port' => 1,
13776 
                    'must_be_hdl_vector' => 1,
13777 
                    'period' => 1,
13778 
                    'port_id' => 0,
13779 
                    'simulinkName' => 'INOUT_LOGIC/reg03_rv',
13780 
                    'source_block' => 'INOUT_LOGIC',
13781 
                    'timingConstraint' => 'none',
13782 
                    'type' => 'UFix_1_0',
13783 
                  },
13784 
                  'direction' => 'out',
13785 
                  'hdlType' => 'std_logic',
13786 
                  'width' => 1,
13787 
                },
13788 
                'reg03_td' => {
13789 
                  'attributes' => {
13790 
                    'bin_pt' => 0,
13791 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_td.dat',
13792 
                    'is_floating_block' => 1,
13793 
                    'is_gateway_port' => 1,
13794 
                    'must_be_hdl_vector' => 1,
13795 
                    'period' => 1,
13796 
                    'port_id' => 0,
13797 
                    'simulinkName' => 'INOUT_LOGIC/reg03_td',
13798 
                    'source_block' => 'INOUT_LOGIC',
13799 
                    'timingConstraint' => 'none',
13800 
                    'type' => 'UFix_32_0',
13801 
                  },
13802 
                  'direction' => 'in',
13803 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13804 
                  'width' => 32,
13805 
                },
13806 
                'reg03_tv' => {
13807 
                  'attributes' => {
13808 
                    'bin_pt' => 0,
13809 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_tv.dat',
13810 
                    'is_floating_block' => 1,
13811 
                    'is_gateway_port' => 1,
13812 
                    'must_be_hdl_vector' => 1,
13813 
                    'period' => 1,
13814 
                    'port_id' => 0,
13815 
                    'simulinkName' => 'INOUT_LOGIC/reg03_tv',
13816 
                    'source_block' => 'INOUT_LOGIC',
13817 
                    'timingConstraint' => 'none',
13818 
                    'type' => 'Bool',
13819 
                  },
13820 
                  'direction' => 'in',
13821 
                  'hdlType' => 'std_logic',
13822 
                  'width' => 1,
13823 
                },
13824 
                'reg04_rd' => {
13825 
                  'attributes' => {
13826 
                    'bin_pt' => 0,
13827 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
13828 
                    'is_floating_block' => 1,
13829 
                    'is_gateway_port' => 1,
13830 
                    'must_be_hdl_vector' => 1,
13831 
                    'period' => 1,
13832 
                    'port_id' => 0,
13833 
                    'simulinkName' => 'INOUT_LOGIC/reg04_rd',
13834 
                    'source_block' => 'INOUT_LOGIC',
13835 
                    'timingConstraint' => 'none',
13836 
                    'type' => 'UFix_32_0',
13837 
                  },
13838 
                  'direction' => 'out',
13839 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13840 
                  'width' => 32,
13841 
                },
13842 
                'reg04_rv' => {
13843 
                  'attributes' => {
13844 
                    'bin_pt' => 0,
13845 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
13846 
                    'is_floating_block' => 1,
13847 
                    'is_gateway_port' => 1,
13848 
                    'must_be_hdl_vector' => 1,
13849 
                    'period' => 1,
13850 
                    'port_id' => 0,
13851 
                    'simulinkName' => 'INOUT_LOGIC/reg04_rv',
13852 
                    'source_block' => 'INOUT_LOGIC',
13853 
                    'timingConstraint' => 'none',
13854 
                    'type' => 'UFix_1_0',
13855 
                  },
13856 
                  'direction' => 'out',
13857 
                  'hdlType' => 'std_logic',
13858 
                  'width' => 1,
13859 
                },
13860 
                'reg04_td' => {
13861 
                  'attributes' => {
13862 
                    'bin_pt' => 0,
13863 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_td.dat',
13864 
                    'is_floating_block' => 1,
13865 
                    'is_gateway_port' => 1,
13866 
                    'must_be_hdl_vector' => 1,
13867 
                    'period' => 1,
13868 
                    'port_id' => 0,
13869 
                    'simulinkName' => 'INOUT_LOGIC/reg04_td',
13870 
                    'source_block' => 'INOUT_LOGIC',
13871 
                    'timingConstraint' => 'none',
13872 
                    'type' => 'UFix_32_0',
13873 
                  },
13874 
                  'direction' => 'in',
13875 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13876 
                  'width' => 32,
13877 
                },
13878 
                'reg04_tv' => {
13879 
                  'attributes' => {
13880 
                    'bin_pt' => 0,
13881 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_tv.dat',
13882 
                    'is_floating_block' => 1,
13883 
                    'is_gateway_port' => 1,
13884 
                    'must_be_hdl_vector' => 1,
13885 
                    'period' => 1,
13886 
                    'port_id' => 0,
13887 
                    'simulinkName' => 'INOUT_LOGIC/reg04_tv',
13888 
                    'source_block' => 'INOUT_LOGIC',
13889 
                    'timingConstraint' => 'none',
13890 
                    'type' => 'Bool',
13891 
                  },
13892 
                  'direction' => 'in',
13893 
                  'hdlType' => 'std_logic',
13894 
                  'width' => 1,
13895 
                },
13896 
                'reg05_rd' => {
13897 
                  'attributes' => {
13898 
                    'bin_pt' => 0,
13899 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
13900 
                    'is_floating_block' => 1,
13901 
                    'is_gateway_port' => 1,
13902 
                    'must_be_hdl_vector' => 1,
13903 
                    'period' => 1,
13904 
                    'port_id' => 0,
13905 
                    'simulinkName' => 'INOUT_LOGIC/reg05_rd',
13906 
                    'source_block' => 'INOUT_LOGIC',
13907 
                    'timingConstraint' => 'none',
13908 
                    'type' => 'UFix_32_0',
13909 
                  },
13910 
                  'direction' => 'out',
13911 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13912 
                  'width' => 32,
13913 
                },
13914 
                'reg05_rv' => {
13915 
                  'attributes' => {
13916 
                    'bin_pt' => 0,
13917 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rv.dat',
13918 
                    'is_floating_block' => 1,
13919 
                    'is_gateway_port' => 1,
13920 
                    'must_be_hdl_vector' => 1,
13921 
                    'period' => 1,
13922 
                    'port_id' => 0,
13923 
                    'simulinkName' => 'INOUT_LOGIC/reg05_rv',
13924 
                    'source_block' => 'INOUT_LOGIC',
13925 
                    'timingConstraint' => 'none',
13926 
                    'type' => 'UFix_1_0',
13927 
                  },
13928 
                  'direction' => 'out',
13929 
                  'hdlType' => 'std_logic',
13930 
                  'width' => 1,
13931 
                },
13932 
                'reg05_td' => {
13933 
                  'attributes' => {
13934 
                    'bin_pt' => 0,
13935 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_td.dat',
13936 
                    'is_floating_block' => 1,
13937 
                    'is_gateway_port' => 1,
13938 
                    'must_be_hdl_vector' => 1,
13939 
                    'period' => 1,
13940 
                    'port_id' => 0,
13941 
                    'simulinkName' => 'INOUT_LOGIC/reg05_td',
13942 
                    'source_block' => 'INOUT_LOGIC',
13943 
                    'timingConstraint' => 'none',
13944 
                    'type' => 'UFix_32_0',
13945 
                  },
13946 
                  'direction' => 'in',
13947 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13948 
                  'width' => 32,
13949 
                },
13950 
                'reg05_tv' => {
13951 
                  'attributes' => {
13952 
                    'bin_pt' => 0,
13953 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
13954 
                    'is_floating_block' => 1,
13955 
                    'is_gateway_port' => 1,
13956 
                    'must_be_hdl_vector' => 1,
13957 
                    'period' => 1,
13958 
                    'port_id' => 0,
13959 
                    'simulinkName' => 'INOUT_LOGIC/reg05_tv',
13960 
                    'source_block' => 'INOUT_LOGIC',
13961 
                    'timingConstraint' => 'none',
13962 
                    'type' => 'Bool',
13963 
                  },
13964 
                  'direction' => 'in',
13965 
                  'hdlType' => 'std_logic',
13966 
                  'width' => 1,
13967 
                },
13968 
                'reg06_rd' => {
13969 
                  'attributes' => {
13970 
                    'bin_pt' => 0,
13971 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
13972 
                    'is_floating_block' => 1,
13973 
                    'is_gateway_port' => 1,
13974 
                    'must_be_hdl_vector' => 1,
13975 
                    'period' => 1,
13976 
                    'port_id' => 0,
13977 
                    'simulinkName' => 'INOUT_LOGIC/reg06_rd',
13978 
                    'source_block' => 'INOUT_LOGIC',
13979 
                    'timingConstraint' => 'none',
13980 
                    'type' => 'UFix_32_0',
13981 
                  },
13982 
                  'direction' => 'out',
13983 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13984 
                  'width' => 32,
13985 
                },
13986 
                'reg06_rv' => {
13987 
                  'attributes' => {
13988 
                    'bin_pt' => 0,
13989 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rv.dat',
13990 
                    'is_floating_block' => 1,
13991 
                    'is_gateway_port' => 1,
13992 
                    'must_be_hdl_vector' => 1,
13993 
                    'period' => 1,
13994 
                    'port_id' => 0,
13995 
                    'simulinkName' => 'INOUT_LOGIC/reg06_rv',
13996 
                    'source_block' => 'INOUT_LOGIC',
13997 
                    'timingConstraint' => 'none',
13998 
                    'type' => 'UFix_1_0',
13999 
                  },
14000 
                  'direction' => 'out',
14001 
                  'hdlType' => 'std_logic',
14002 
                  'width' => 1,
14003 
                },
14004 
                'reg06_td' => {
14005 
                  'attributes' => {
14006 
                    'bin_pt' => 0,
14007 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_td.dat',
14008 
                    'is_floating_block' => 1,
14009 
                    'is_gateway_port' => 1,
14010 
                    'must_be_hdl_vector' => 1,
14011 
                    'period' => 1,
14012 
                    'port_id' => 0,
14013 
                    'simulinkName' => 'INOUT_LOGIC/reg06_td',
14014 
                    'source_block' => 'INOUT_LOGIC',
14015 
                    'timingConstraint' => 'none',
14016 
                    'type' => 'UFix_32_0',
14017 
                  },
14018 
                  'direction' => 'in',
14019 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14020 
                  'width' => 32,
14021 
                },
14022 
                'reg06_tv' => {
14023 
                  'attributes' => {
14024 
                    'bin_pt' => 0,
14025 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
14026 
                    'is_floating_block' => 1,
14027 
                    'is_gateway_port' => 1,
14028 
                    'must_be_hdl_vector' => 1,
14029 
                    'period' => 1,
14030 
                    'port_id' => 0,
14031 
                    'simulinkName' => 'INOUT_LOGIC/reg06_tv',
14032 
                    'source_block' => 'INOUT_LOGIC',
14033 
                    'timingConstraint' => 'none',
14034 
                    'type' => 'Bool',
14035 
                  },
14036 
                  'direction' => 'in',
14037 
                  'hdlType' => 'std_logic',
14038 
                  'width' => 1,
14039 
                },
14040 
                'reg07_rd' => {
14041 
                  'attributes' => {
14042 
                    'bin_pt' => 0,
14043 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
14044 
                    'is_floating_block' => 1,
14045 
                    'is_gateway_port' => 1,
14046 
                    'must_be_hdl_vector' => 1,
14047 
                    'period' => 1,
14048 
                    'port_id' => 0,
14049 
                    'simulinkName' => 'INOUT_LOGIC/reg07_rd',
14050 
                    'source_block' => 'INOUT_LOGIC',
14051 
                    'timingConstraint' => 'none',
14052 
                    'type' => 'UFix_32_0',
14053 
                  },
14054 
                  'direction' => 'out',
14055 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14056 
                  'width' => 32,
14057 
                },
14058 
                'reg07_rv' => {
14059 
                  'attributes' => {
14060 
                    'bin_pt' => 0,
14061 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
14062 
                    'is_floating_block' => 1,
14063 
                    'is_gateway_port' => 1,
14064 
                    'must_be_hdl_vector' => 1,
14065 
                    'period' => 1,
14066 
                    'port_id' => 0,
14067 
                    'simulinkName' => 'INOUT_LOGIC/reg07_rv',
14068 
                    'source_block' => 'INOUT_LOGIC',
14069 
                    'timingConstraint' => 'none',
14070 
                    'type' => 'UFix_1_0',
14071 
                  },
14072 
                  'direction' => 'out',
14073 
                  'hdlType' => 'std_logic',
14074 
                  'width' => 1,
14075 
                },
14076 
                'reg07_td' => {
14077 
                  'attributes' => {
14078 
                    'bin_pt' => 0,
14079 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
14080 
                    'is_floating_block' => 1,
14081 
                    'is_gateway_port' => 1,
14082 
                    'must_be_hdl_vector' => 1,
14083 
                    'period' => 1,
14084 
                    'port_id' => 0,
14085 
                    'simulinkName' => 'INOUT_LOGIC/reg07_td',
14086 
                    'source_block' => 'INOUT_LOGIC',
14087 
                    'timingConstraint' => 'none',
14088 
                    'type' => 'UFix_32_0',
14089 
                  },
14090 
                  'direction' => 'in',
14091 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14092 
                  'width' => 32,
14093 
                },
14094 
                'reg07_tv' => {
14095 
                  'attributes' => {
14096 
                    'bin_pt' => 0,
14097 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
14098 
                    'is_floating_block' => 1,
14099 
                    'is_gateway_port' => 1,
14100 
                    'must_be_hdl_vector' => 1,
14101 
                    'period' => 1,
14102 
                    'port_id' => 0,
14103 
                    'simulinkName' => 'INOUT_LOGIC/reg07_tv',
14104 
                    'source_block' => 'INOUT_LOGIC',
14105 
                    'timingConstraint' => 'none',
14106 
                    'type' => 'Bool',
14107 
                  },
14108 
                  'direction' => 'in',
14109 
                  'hdlType' => 'std_logic',
14110 
                  'width' => 1,
14111 
                },
14112 
                'reg08_rd' => {
14113 
                  'attributes' => {
14114 
                    'bin_pt' => 0,
14115 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
14116 
                    'is_floating_block' => 1,
14117 
                    'is_gateway_port' => 1,
14118 
                    'must_be_hdl_vector' => 1,
14119 
                    'period' => 1,
14120 
                    'port_id' => 0,
14121 
                    'simulinkName' => 'INOUT_LOGIC/reg08_rd',
14122 
                    'source_block' => 'INOUT_LOGIC',
14123 
                    'timingConstraint' => 'none',
14124 
                    'type' => 'UFix_32_0',
14125 
                  },
14126 
                  'direction' => 'out',
14127 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14128 
                  'width' => 32,
14129 
                },
14130 
                'reg08_rv' => {
14131 
                  'attributes' => {
14132 
                    'bin_pt' => 0,
14133 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
14134 
                    'is_floating_block' => 1,
14135 
                    'is_gateway_port' => 1,
14136 
                    'must_be_hdl_vector' => 1,
14137 
                    'period' => 1,
14138 
                    'port_id' => 0,
14139 
                    'simulinkName' => 'INOUT_LOGIC/reg08_rv',
14140 
                    'source_block' => 'INOUT_LOGIC',
14141 
                    'timingConstraint' => 'none',
14142 
                    'type' => 'UFix_1_0',
14143 
                  },
14144 
                  'direction' => 'out',
14145 
                  'hdlType' => 'std_logic',
14146 
                  'width' => 1,
14147 
                },
14148 
                'reg08_td' => {
14149 
                  'attributes' => {
14150 
                    'bin_pt' => 0,
14151 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
14152 
                    'is_floating_block' => 1,
14153 
                    'is_gateway_port' => 1,
14154 
                    'must_be_hdl_vector' => 1,
14155 
                    'period' => 1,
14156 
                    'port_id' => 0,
14157 
                    'simulinkName' => 'INOUT_LOGIC/reg08_td',
14158 
                    'source_block' => 'INOUT_LOGIC',
14159 
                    'timingConstraint' => 'none',
14160 
                    'type' => 'UFix_32_0',
14161 
                  },
14162 
                  'direction' => 'in',
14163 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14164 
                  'width' => 32,
14165 
                },
14166 
                'reg08_tv' => {
14167 
                  'attributes' => {
14168 
                    'bin_pt' => 0,
14169 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
14170 
                    'is_floating_block' => 1,
14171 
                    'is_gateway_port' => 1,
14172 
                    'must_be_hdl_vector' => 1,
14173 
                    'period' => 1,
14174 
                    'port_id' => 0,
14175 
                    'simulinkName' => 'INOUT_LOGIC/reg08_tv',
14176 
                    'source_block' => 'INOUT_LOGIC',
14177 
                    'timingConstraint' => 'none',
14178 
                    'type' => 'Bool',
14179 
                  },
14180 
                  'direction' => 'in',
14181 
                  'hdlType' => 'std_logic',
14182 
                  'width' => 1,
14183 
                },
14184 
                'reg09_rd' => {
14185 
                  'attributes' => {
14186 
                    'bin_pt' => 0,
14187 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
14188 
                    'is_floating_block' => 1,
14189 
                    'is_gateway_port' => 1,
14190 
                    'must_be_hdl_vector' => 1,
14191 
                    'period' => 1,
14192 
                    'port_id' => 0,
14193 
                    'simulinkName' => 'INOUT_LOGIC/reg09_rd',
14194 
                    'source_block' => 'INOUT_LOGIC',
14195 
                    'timingConstraint' => 'none',
14196 
                    'type' => 'UFix_32_0',
14197 
                  },
14198 
                  'direction' => 'out',
14199 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14200 
                  'width' => 32,
14201 
                },
14202 
                'reg09_rv' => {
14203 
                  'attributes' => {
14204 
                    'bin_pt' => 0,
14205 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
14206 
                    'is_floating_block' => 1,
14207 
                    'is_gateway_port' => 1,
14208 
                    'must_be_hdl_vector' => 1,
14209 
                    'period' => 1,
14210 
                    'port_id' => 0,
14211 
                    'simulinkName' => 'INOUT_LOGIC/reg09_rv',
14212 
                    'source_block' => 'INOUT_LOGIC',
14213 
                    'timingConstraint' => 'none',
14214 
                    'type' => 'UFix_1_0',
14215 
                  },
14216 
                  'direction' => 'out',
14217 
                  'hdlType' => 'std_logic',
14218 
                  'width' => 1,
14219 
                },
14220 
                'reg09_td' => {
14221 
                  'attributes' => {
14222 
                    'bin_pt' => 0,
14223 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
14224 
                    'is_floating_block' => 1,
14225 
                    'is_gateway_port' => 1,
14226 
                    'must_be_hdl_vector' => 1,
14227 
                    'period' => 1,
14228 
                    'port_id' => 0,
14229 
                    'simulinkName' => 'INOUT_LOGIC/reg09_td',
14230 
                    'source_block' => 'INOUT_LOGIC',
14231 
                    'timingConstraint' => 'none',
14232 
                    'type' => 'UFix_32_0',
14233 
                  },
14234 
                  'direction' => 'in',
14235 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14236 
                  'width' => 32,
14237 
                },
14238 
                'reg09_tv' => {
14239 
                  'attributes' => {
14240 
                    'bin_pt' => 0,
14241 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
14242 
                    'is_floating_block' => 1,
14243 
                    'is_gateway_port' => 1,
14244 
                    'must_be_hdl_vector' => 1,
14245 
                    'period' => 1,
14246 
                    'port_id' => 0,
14247 
                    'simulinkName' => 'INOUT_LOGIC/reg09_tv',
14248 
                    'source_block' => 'INOUT_LOGIC',
14249 
                    'timingConstraint' => 'none',
14250 
                    'type' => 'Bool',
14251 
                  },
14252 
                  'direction' => 'in',
14253 
                  'hdlType' => 'std_logic',
14254 
                  'width' => 1,
14255 
                },
14256 
                'reg10_rd' => {
14257 
                  'attributes' => {
14258 
                    'bin_pt' => 0,
14259 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
14260 
                    'is_floating_block' => 1,
14261 
                    'is_gateway_port' => 1,
14262 
                    'must_be_hdl_vector' => 1,
14263 
                    'period' => 1,
14264 
                    'port_id' => 0,
14265 
                    'simulinkName' => 'INOUT_LOGIC/reg10_rd',
14266 
                    'source_block' => 'INOUT_LOGIC',
14267 
                    'timingConstraint' => 'none',
14268 
                    'type' => 'UFix_32_0',
14269 
                  },
14270 
                  'direction' => 'out',
14271 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14272 
                  'width' => 32,
14273 
                },
14274 
                'reg10_rv' => {
14275 
                  'attributes' => {
14276 
                    'bin_pt' => 0,
14277 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
14278 
                    'is_floating_block' => 1,
14279 
                    'is_gateway_port' => 1,
14280 
                    'must_be_hdl_vector' => 1,
14281 
                    'period' => 1,
14282 
                    'port_id' => 0,
14283 
                    'simulinkName' => 'INOUT_LOGIC/reg10_rv',
14284 
                    'source_block' => 'INOUT_LOGIC',
14285 
                    'timingConstraint' => 'none',
14286 
                    'type' => 'UFix_1_0',
14287 
                  },
14288 
                  'direction' => 'out',
14289 
                  'hdlType' => 'std_logic',
14290 
                  'width' => 1,
14291 
                },
14292 
                'reg10_td' => {
14293 
                  'attributes' => {
14294 
                    'bin_pt' => 0,
14295 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
14296 
                    'is_floating_block' => 1,
14297 
                    'is_gateway_port' => 1,
14298 
                    'must_be_hdl_vector' => 1,
14299 
                    'period' => 1,
14300 
                    'port_id' => 0,
14301 
                    'simulinkName' => 'INOUT_LOGIC/reg10_td',
14302 
                    'source_block' => 'INOUT_LOGIC',
14303 
                    'timingConstraint' => 'none',
14304 
                    'type' => 'UFix_32_0',
14305 
                  },
14306 
                  'direction' => 'in',
14307 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14308 
                  'width' => 32,
14309 
                },
14310 
                'reg10_tv' => {
14311 
                  'attributes' => {
14312 
                    'bin_pt' => 0,
14313 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
14314 
                    'is_floating_block' => 1,
14315 
                    'is_gateway_port' => 1,
14316 
                    'must_be_hdl_vector' => 1,
14317 
                    'period' => 1,
14318 
                    'port_id' => 0,
14319 
                    'simulinkName' => 'INOUT_LOGIC/reg10_tv',
14320 
                    'source_block' => 'INOUT_LOGIC',
14321 
                    'timingConstraint' => 'none',
14322 
                    'type' => 'Bool',
14323 
                  },
14324 
                  'direction' => 'in',
14325 
                  'hdlType' => 'std_logic',
14326 
                  'width' => 1,
14327 
                },
14328 
                'reg11_rd' => {
14329 
                  'attributes' => {
14330 
                    'bin_pt' => 0,
14331 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
14332 
                    'is_floating_block' => 1,
14333 
                    'is_gateway_port' => 1,
14334 
                    'must_be_hdl_vector' => 1,
14335 
                    'period' => 1,
14336 
                    'port_id' => 0,
14337 
                    'simulinkName' => 'INOUT_LOGIC/reg11_rd',
14338 
                    'source_block' => 'INOUT_LOGIC',
14339 
                    'timingConstraint' => 'none',
14340 
                    'type' => 'UFix_32_0',
14341 
                  },
14342 
                  'direction' => 'out',
14343 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14344 
                  'width' => 32,
14345 
                },
14346 
                'reg11_rv' => {
14347 
                  'attributes' => {
14348 
                    'bin_pt' => 0,
14349 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
14350 
                    'is_floating_block' => 1,
14351 
                    'is_gateway_port' => 1,
14352 
                    'must_be_hdl_vector' => 1,
14353 
                    'period' => 1,
14354 
                    'port_id' => 0,
14355 
                    'simulinkName' => 'INOUT_LOGIC/reg11_rv',
14356 
                    'source_block' => 'INOUT_LOGIC',
14357 
                    'timingConstraint' => 'none',
14358 
                    'type' => 'UFix_1_0',
14359 
                  },
14360 
                  'direction' => 'out',
14361 
                  'hdlType' => 'std_logic',
14362 
                  'width' => 1,
14363 
                },
14364 
                'reg11_td' => {
14365 
                  'attributes' => {
14366 
                    'bin_pt' => 0,
14367 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
14368 
                    'is_floating_block' => 1,
14369 
                    'is_gateway_port' => 1,
14370 
                    'must_be_hdl_vector' => 1,
14371 
                    'period' => 1,
14372 
                    'port_id' => 0,
14373 
                    'simulinkName' => 'INOUT_LOGIC/reg11_td',
14374 
                    'source_block' => 'INOUT_LOGIC',
14375 
                    'timingConstraint' => 'none',
14376 
                    'type' => 'UFix_32_0',
14377 
                  },
14378 
                  'direction' => 'in',
14379 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14380 
                  'width' => 32,
14381 
                },
14382 
                'reg11_tv' => {
14383 
                  'attributes' => {
14384 
                    'bin_pt' => 0,
14385 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
14386 
                    'is_floating_block' => 1,
14387 
                    'is_gateway_port' => 1,
14388 
                    'must_be_hdl_vector' => 1,
14389 
                    'period' => 1,
14390 
                    'port_id' => 0,
14391 
                    'simulinkName' => 'INOUT_LOGIC/reg11_tv',
14392 
                    'source_block' => 'INOUT_LOGIC',
14393 
                    'timingConstraint' => 'none',
14394 
                    'type' => 'Bool',
14395 
                  },
14396 
                  'direction' => 'in',
14397 
                  'hdlType' => 'std_logic',
14398 
                  'width' => 1,
14399 
                },
14400 
                'reg12_rd' => {
14401 
                  'attributes' => {
14402 
                    'bin_pt' => 0,
14403 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
14404 
                    'is_floating_block' => 1,
14405 
                    'is_gateway_port' => 1,
14406 
                    'must_be_hdl_vector' => 1,
14407 
                    'period' => 1,
14408 
                    'port_id' => 0,
14409 
                    'simulinkName' => 'INOUT_LOGIC/reg12_rd',
14410 
                    'source_block' => 'INOUT_LOGIC',
14411 
                    'timingConstraint' => 'none',
14412 
                    'type' => 'UFix_32_0',
14413 
                  },
14414 
                  'direction' => 'out',
14415 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14416 
                  'width' => 32,
14417 
                },
14418 
                'reg12_rv' => {
14419 
                  'attributes' => {
14420 
                    'bin_pt' => 0,
14421 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
14422 
                    'is_floating_block' => 1,
14423 
                    'is_gateway_port' => 1,
14424 
                    'must_be_hdl_vector' => 1,
14425 
                    'period' => 1,
14426 
                    'port_id' => 0,
14427 
                    'simulinkName' => 'INOUT_LOGIC/reg12_rv',
14428 
                    'source_block' => 'INOUT_LOGIC',
14429 
                    'timingConstraint' => 'none',
14430 
                    'type' => 'UFix_1_0',
14431 
                  },
14432 
                  'direction' => 'out',
14433 
                  'hdlType' => 'std_logic',
14434 
                  'width' => 1,
14435 
                },
14436 
                'reg12_td' => {
14437 
                  'attributes' => {
14438 
                    'bin_pt' => 0,
14439 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
14440 
                    'is_floating_block' => 1,
14441 
                    'is_gateway_port' => 1,
14442 
                    'must_be_hdl_vector' => 1,
14443 
                    'period' => 1,
14444 
                    'port_id' => 0,
14445 
                    'simulinkName' => 'INOUT_LOGIC/reg12_td',
14446 
                    'source_block' => 'INOUT_LOGIC',
14447 
                    'timingConstraint' => 'none',
14448 
                    'type' => 'UFix_32_0',
14449 
                  },
14450 
                  'direction' => 'in',
14451 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14452 
                  'width' => 32,
14453 
                },
14454 
                'reg12_tv' => {
14455 
                  'attributes' => {
14456 
                    'bin_pt' => 0,
14457 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
14458 
                    'is_floating_block' => 1,
14459 
                    'is_gateway_port' => 1,
14460 
                    'must_be_hdl_vector' => 1,
14461 
                    'period' => 1,
14462 
                    'port_id' => 0,
14463 
                    'simulinkName' => 'INOUT_LOGIC/reg12_tv',
14464 
                    'source_block' => 'INOUT_LOGIC',
14465 
                    'timingConstraint' => 'none',
14466 
                    'type' => 'Bool',
14467 
                  },
14468 
                  'direction' => 'in',
14469 
                  'hdlType' => 'std_logic',
14470 
                  'width' => 1,
14471 
                },
14472 
                'reg13_rd' => {
14473 
                  'attributes' => {
14474 
                    'bin_pt' => 0,
14475 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
14476 
                    'is_floating_block' => 1,
14477 
                    'is_gateway_port' => 1,
14478 
                    'must_be_hdl_vector' => 1,
14479 
                    'period' => 1,
14480 
                    'port_id' => 0,
14481 
                    'simulinkName' => 'INOUT_LOGIC/reg13_rd',
14482 
                    'source_block' => 'INOUT_LOGIC',
14483 
                    'timingConstraint' => 'none',
14484 
                    'type' => 'UFix_32_0',
14485 
                  },
14486 
                  'direction' => 'out',
14487 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14488 
                  'width' => 32,
14489 
                },
14490 
                'reg13_rv' => {
14491 
                  'attributes' => {
14492 
                    'bin_pt' => 0,
14493 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
14494 
                    'is_floating_block' => 1,
14495 
                    'is_gateway_port' => 1,
14496 
                    'must_be_hdl_vector' => 1,
14497 
                    'period' => 1,
14498 
                    'port_id' => 0,
14499 
                    'simulinkName' => 'INOUT_LOGIC/reg13_rv',
14500 
                    'source_block' => 'INOUT_LOGIC',
14501 
                    'timingConstraint' => 'none',
14502 
                    'type' => 'UFix_1_0',
14503 
                  },
14504 
                  'direction' => 'out',
14505 
                  'hdlType' => 'std_logic',
14506 
                  'width' => 1,
14507 
                },
14508 
                'reg13_td' => {
14509 
                  'attributes' => {
14510 
                    'bin_pt' => 0,
14511 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
14512 
                    'is_floating_block' => 1,
14513 
                    'is_gateway_port' => 1,
14514 
                    'must_be_hdl_vector' => 1,
14515 
                    'period' => 1,
14516 
                    'port_id' => 0,
14517 
                    'simulinkName' => 'INOUT_LOGIC/reg13_td',
14518 
                    'source_block' => 'INOUT_LOGIC',
14519 
                    'timingConstraint' => 'none',
14520 
                    'type' => 'UFix_32_0',
14521 
                  },
14522 
                  'direction' => 'in',
14523 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14524 
                  'width' => 32,
14525 
                },
14526 
                'reg13_tv' => {
14527 
                  'attributes' => {
14528 
                    'bin_pt' => 0,
14529 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
14530 
                    'is_floating_block' => 1,
14531 
                    'is_gateway_port' => 1,
14532 
                    'must_be_hdl_vector' => 1,
14533 
                    'period' => 1,
14534 
                    'port_id' => 0,
14535 
                    'simulinkName' => 'INOUT_LOGIC/reg13_tv',
14536 
                    'source_block' => 'INOUT_LOGIC',
14537 
                    'timingConstraint' => 'none',
14538 
                    'type' => 'Bool',
14539 
                  },
14540 
                  'direction' => 'in',
14541 
                  'hdlType' => 'std_logic',
14542 
                  'width' => 1,
14543 
                },
14544 
                'reg14_rd' => {
14545 
                  'attributes' => {
14546 
                    'bin_pt' => 0,
14547 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
14548 
                    'is_floating_block' => 1,
14549 
                    'is_gateway_port' => 1,
14550 
                    'must_be_hdl_vector' => 1,
14551 
                    'period' => 1,
14552 
                    'port_id' => 0,
14553 
                    'simulinkName' => 'INOUT_LOGIC/reg14_rd',
14554 
                    'source_block' => 'INOUT_LOGIC',
14555 
                    'timingConstraint' => 'none',
14556 
                    'type' => 'UFix_32_0',
14557 
                  },
14558 
                  'direction' => 'out',
14559 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14560 
                  'width' => 32,
14561 
                },
14562 
                'reg14_rv' => {
14563 
                  'attributes' => {
14564 
                    'bin_pt' => 0,
14565 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
14566 
                    'is_floating_block' => 1,
14567 
                    'is_gateway_port' => 1,
14568 
                    'must_be_hdl_vector' => 1,
14569 
                    'period' => 1,
14570 
                    'port_id' => 0,
14571 
                    'simulinkName' => 'INOUT_LOGIC/reg14_rv',
14572 
                    'source_block' => 'INOUT_LOGIC',
14573 
                    'timingConstraint' => 'none',
14574 
                    'type' => 'UFix_1_0',
14575 
                  },
14576 
                  'direction' => 'out',
14577 
                  'hdlType' => 'std_logic',
14578 
                  'width' => 1,
14579 
                },
14580 
                'reg14_td' => {
14581 
                  'attributes' => {
14582 
                    'bin_pt' => 0,
14583 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
14584 
                    'is_floating_block' => 1,
14585 
                    'is_gateway_port' => 1,
14586 
                    'must_be_hdl_vector' => 1,
14587 
                    'period' => 1,
14588 
                    'port_id' => 0,
14589 
                    'simulinkName' => 'INOUT_LOGIC/reg14_td',
14590 
                    'source_block' => 'INOUT_LOGIC',
14591 
                    'timingConstraint' => 'none',
14592 
                    'type' => 'UFix_32_0',
14593 
                  },
14594 
                  'direction' => 'in',
14595 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14596 
                  'width' => 32,
14597 
                },
14598 
                'reg14_tv' => {
14599 
                  'attributes' => {
14600 
                    'bin_pt' => 0,
14601 
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
14602 
                    'is_floating_block' => 1,
14603 
                    'is_gateway_port' => 1,
14604 
                    'must_be_hdl_vector' => 1,
14605 
                    'period' => 1,
14606 
                    'port_id' => 0,
14607 
                    'simulinkName' => 'INOUT_LOGIC/reg14_tv',
14608 
                    'source_block' => 'INOUT_LOGIC',
14609 
                    'timingConstraint' => 'none',
14610 
                    'type' => 'Bool',
14611 
                  },
14612 
                  'direction' => 'in',
14613 
                  'hdlType' => 'std_logic',
14614 
                  'width' => 1,
14615 
                },
14616 
              },
14617 
            },
14618 
            'entityName' => 'inout_logic',
14619 
          },
14620 
          'persistentdff_inst' => {
14621 
            'connections' => {
14622 
              'clk' => 'clkNet',
14623 
              'd' => 'persistentdff_inst_q',
14624 
              'q' => 'persistentdff_inst_q',
14625 
            },
14626 
            'entity' => {
14627 
              'attributes' => {
14628 
                'entityAlreadyNetlisted' => 1,
14629 
                'hdlCompAttributes' => [
14630 
                  [
14631 
                    'syn_black_box',
14632 
                    'boolean',
14633 
                    'true',
14634 
                  ],
14635 
                  [
14636 
                    'box_type',
14637 
                    'string',
14638 
                    '"black_box"',
14639 
                  ],
14640 
                ],
14641 
                'is_persistent_dff' => 1,
14642 
                'needsComponentDeclaration' => 1,
14643 
              },
14644 
              'entityName' => 'xlpersistentdff',
14645 
              'ports' => {
14646 
                'clk' => {
14647 
                  'direction' => 'in',
14648 
                  'hdlType' => 'std_logic',
14649 
                  'width' => 1,
14650 
                },
14651 
                'd' => {
14652 
                  'direction' => 'in',
14653 
                  'hdlType' => 'std_logic',
14654 
                  'width' => 1,
14655 
                },
14656 
                'q' => {
14657 
                  'direction' => 'out',
14658 
                  'hdlType' => 'std_logic',
14659 
                  'width' => 1,
14660 
                },
14661 
              },
14662 
            },
14663 
            'entityName' => 'xlpersistentdff',
14664 
          },
14665 
        },
14666 
      },
14667 
      'entityName' => 'inout_logic_cw',
14668 
    },
14669 
    'sysgen_gw_clk' => {
14670 
      'connections' => {
14671 
        'clk' => '.clk',
14672 
      },
14673 
      'entity' => {
14674 
        'attributes' => {
14675 
          'entityAlreadyNetlisted' => 1,
14676 
          'isClk' => 1,
14677 
          'isGateway' => 1,
14678 
          'is_floating_block' => 1,
14679 
        },
14680 
        'entityName' => 'sysgen_gw_clk',
14681 
        'ports' => {
14682 
          'clk' => {
14683 
            'attributes' => {
14684 
              'isClk' => 1,
14685 
            },
14686 
            'direction' => 'out',
14687 
            'hdlType' => 'std_logic',
14688 
            'width' => 1,
14689 
          },
14690 
        },
14691 
      },
14692 
      'entityName' => 'sysgen_gw_clk',
14693 
    },
14694 
    'to_register1' => {
14695 
      'connections' => {
14696 
        'ce' => 'sysgen_dut.to_register1_ce',
14697 
        'clk' => 'sysgen_dut.to_register1_clk',
14698 
        'clr' => 'sysgen_dut.to_register1_clr',
14699 
        'data_in' => 'sysgen_dut.to_register1_data_in',
14700 
        'dout' => 'to_register1.dout',
14701 
        'en' => 'sysgen_dut.to_register1_en',
14702 
      },
14703 
      'entity' => {
14704 
        'attributes' => {
14705 
          'entityAlreadyNetlisted' => 1,
14706 
          'generics' => [
14707 
          ],
14708 
          'is_floating_block' => 1,
14709 
          'mask' => {
14710 
            'Block_Handle' => 2118.00048828125,
14711 
            'Block_handle' => 2118.00048828125,
14712 
            'MDL_Handle' => 2083.00048828125,
14713 
            'MDL_handle' => 2083.00048828125,
14714 
            'arith_type' => 1,
14715 
            'bin_pt' => 14,
14716 
            'block_config' => 'sysgen_blockset:toreg_config',
14717 
            'block_handle' => 2118.00048828125,
14718 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1',
14719 
            'block_type' => 'toreg',
14720 
            'dbl_ovrd' => 0,
14721 
            'explicit_data_type' => 0,
14722 
            'gui_display_data_type' => 1,
14723 
            'init' => 0,
14724 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
14725 
            'mdl_handle' => 2083.00048828125,
14726 
            'model_handle' => 2083.00048828125,
14727 
            'n_bits' => 16,
14728 
            'ownership' => 1,
14729 
            'preci_type' => 1,
14730 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14731 
            'shared_memory_name' => 'debug2i',
14732 
          },
14733 
          'needs_vhdl_wrapper' => 0,
14734 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1',
14735 
        },
14736 
        'entityName' => 'x',
14737 
        'ports' => {
14738 
          'ce' => {
14739 
            'attributes' => {
14740 
              'domain' => '',
14741 
              'group' => 1,
14742 
              'isCe' => 1,
14743 
              'is_floating_block' => 1,
14744 
              'period' => 1,
14745 
              'type' => 'logic',
14746 
            },
14747 
            'direction' => 'in',
14748 
            'hdlType' => 'std_logic',
14749 
            'width' => 1,
14750 
          },
14751 
          'clk' => {
14752 
            'attributes' => {
14753 
              'domain' => '',
14754 
              'group' => 1,
14755 
              'isClk' => 1,
14756 
              'is_floating_block' => 1,
14757 
              'period' => 1,
14758 
              'type' => 'logic',
14759 
            },
14760 
            'direction' => 'in',
14761 
            'hdlType' => 'std_logic',
14762 
            'width' => 1,
14763 
          },
14764 
          'clr' => {
14765 
            'attributes' => {
14766 
              'domain' => '',
14767 
              'group' => 1,
14768 
              'isClr' => 1,
14769 
              'is_floating_block' => 1,
14770 
              'period' => 1,
14771 
              'type' => 'logic',
14772 
              'valid_bit_used' => 0,
14773 
            },
14774 
            'direction' => 'in',
14775 
            'hdlType' => 'std_logic',
14776 
            'width' => 1,
14777 
          },
14778 
          'data_in' => {
14779 
            'attributes' => {
14780 
              'bin_pt' => 0,
14781 
              'is_floating_block' => 1,
14782 
              'must_be_hdl_vector' => 1,
14783 
              'period' => 1,
14784 
              'port_id' => 0,
14785 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/data_in',
14786 
              'type' => 'UFix_32_0',
14787 
            },
14788 
            'direction' => 'in',
14789 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14790 
            'width' => 32,
14791 
          },
14792 
          'dout' => {
14793 
            'attributes' => {
14794 
              'bin_pt' => 0,
14795 
              'is_floating_block' => 1,
14796 
              'must_be_hdl_vector' => 1,
14797 
              'period' => 1,
14798 
              'port_id' => 0,
14799 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/dout',
14800 
              'type' => 'UFix_32_0',
14801 
            },
14802 
            'direction' => 'out',
14803 
            'hdlType' => 'std_logic_vector(31 downto 0)',
14804 
            'width' => 32,
14805 
          },
14806 
          'en' => {
14807 
            'attributes' => {
14808 
              'bin_pt' => 0,
14809 
              'is_floating_block' => 1,
14810 
              'must_be_hdl_vector' => 1,
14811 
              'period' => 1,
14812 
              'port_id' => 1,
14813 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/en',
14814 
              'type' => 'Bool',
14815 
            },
14816 
            'direction' => 'in',
14817 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14818 
            'width' => 1,
14819 
          },
14820 
        },
14821 
      },
14822 
      'entityName' => 'x',
14823 
    },
14824 
    'to_register10' => {
14825 
      'connections' => {
14826 
        'ce' => 'sysgen_dut.to_register10_ce',
14827 
        'clk' => 'sysgen_dut.to_register10_clk',
14828 
        'clr' => 'sysgen_dut.to_register10_clr',
14829 
        'data_in' => 'sysgen_dut.to_register10_data_in',
14830 
        'dout' => 'to_register10.dout',
14831 
        'en' => 'sysgen_dut.to_register10_en',
14832 
      },
14833 
      'entity' => {
14834 
        'attributes' => {
14835 
          'entityAlreadyNetlisted' => 1,
14836 
          'generics' => [
14837 
          ],
14838 
          'is_floating_block' => 1,
14839 
          'mask' => {
14840 
            'Block_Handle' => 2119.00048828125,
14841 
            'Block_handle' => 2119.00048828125,
14842 
            'MDL_Handle' => 2083.00048828125,
14843 
            'MDL_handle' => 2083.00048828125,
14844 
            'arith_type' => 1,
14845 
            'bin_pt' => 14,
14846 
            'block_config' => 'sysgen_blockset:toreg_config',
14847 
            'block_handle' => 2119.00048828125,
14848 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10',
14849 
            'block_type' => 'toreg',
14850 
            'dbl_ovrd' => 0,
14851 
            'explicit_data_type' => 0,
14852 
            'gui_display_data_type' => 1,
14853 
            'init' => 0,
14854 
            'init_bit_vector' => '\'b0',
14855 
            'mdl_handle' => 2083.00048828125,
14856 
            'model_handle' => 2083.00048828125,
14857 
            'n_bits' => 16,
14858 
            'ownership' => 1,
14859 
            'preci_type' => 1,
14860 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14861 
            'shared_memory_name' => 'register04tv',
14862 
          },
14863 
          'needs_vhdl_wrapper' => 0,
14864 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10',
14865 
        },
14866 
        'entityName' => 'x_x0',
14867 
        'ports' => {
14868 
          'ce' => {
14869 
            'attributes' => {
14870 
              'domain' => '',
14871 
              'group' => 1,
14872 
              'isCe' => 1,
14873 
              'is_floating_block' => 1,
14874 
              'period' => 1,
14875 
              'type' => 'logic',
14876 
            },
14877 
            'direction' => 'in',
14878 
            'hdlType' => 'std_logic',
14879 
            'width' => 1,
14880 
          },
14881 
          'clk' => {
14882 
            'attributes' => {
14883 
              'domain' => '',
14884 
              'group' => 1,
14885 
              'isClk' => 1,
14886 
              'is_floating_block' => 1,
14887 
              'period' => 1,
14888 
              'type' => 'logic',
14889 
            },
14890 
            'direction' => 'in',
14891 
            'hdlType' => 'std_logic',
14892 
            'width' => 1,
14893 
          },
14894 
          'clr' => {
14895 
            'attributes' => {
14896 
              'domain' => '',
14897 
              'group' => 1,
14898 
              'isClr' => 1,
14899 
              'is_floating_block' => 1,
14900 
              'period' => 1,
14901 
              'type' => 'logic',
14902 
              'valid_bit_used' => 0,
14903 
            },
14904 
            'direction' => 'in',
14905 
            'hdlType' => 'std_logic',
14906 
            'width' => 1,
14907 
          },
14908 
          'data_in' => {
14909 
            'attributes' => {
14910 
              'bin_pt' => 0,
14911 
              'is_floating_block' => 1,
14912 
              'must_be_hdl_vector' => 1,
14913 
              'period' => 1,
14914 
              'port_id' => 0,
14915 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/data_in',
14916 
              'type' => 'Bool',
14917 
            },
14918 
            'direction' => 'in',
14919 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14920 
            'width' => 1,
14921 
          },
14922 
          'dout' => {
14923 
            'attributes' => {
14924 
              'bin_pt' => 0,
14925 
              'is_floating_block' => 1,
14926 
              'must_be_hdl_vector' => 1,
14927 
              'period' => 1,
14928 
              'port_id' => 0,
14929 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/dout',
14930 
              'type' => 'Bool',
14931 
            },
14932 
            'direction' => 'out',
14933 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14934 
            'width' => 1,
14935 
          },
14936 
          'en' => {
14937 
            'attributes' => {
14938 
              'bin_pt' => 0,
14939 
              'is_floating_block' => 1,
14940 
              'must_be_hdl_vector' => 1,
14941 
              'period' => 1,
14942 
              'port_id' => 1,
14943 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register10/en',
14944 
              'type' => 'Bool',
14945 
            },
14946 
            'direction' => 'in',
14947 
            'hdlType' => 'std_logic_vector(0 downto 0)',
14948 
            'width' => 1,
14949 
          },
14950 
        },
14951 
      },
14952 
      'entityName' => 'x_x0',
14953 
    },
14954 
    'to_register11' => {
14955 
      'connections' => {
14956 
        'ce' => 'sysgen_dut.to_register11_ce',
14957 
        'clk' => 'sysgen_dut.to_register11_clk',
14958 
        'clr' => 'sysgen_dut.to_register11_clr',
14959 
        'data_in' => 'sysgen_dut.to_register11_data_in',
14960 
        'dout' => 'to_register11.dout',
14961 
        'en' => 'sysgen_dut.to_register11_en',
14962 
      },
14963 
      'entity' => {
14964 
        'attributes' => {
14965 
          'entityAlreadyNetlisted' => 1,
14966 
          'generics' => [
14967 
          ],
14968 
          'is_floating_block' => 1,
14969 
          'mask' => {
14970 
            'Block_Handle' => 2120.00048828125,
14971 
            'Block_handle' => 2120.00048828125,
14972 
            'MDL_Handle' => 2083.00048828125,
14973 
            'MDL_handle' => 2083.00048828125,
14974 
            'arith_type' => 1,
14975 
            'bin_pt' => 14,
14976 
            'block_config' => 'sysgen_blockset:toreg_config',
14977 
            'block_handle' => 2120.00048828125,
14978 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11',
14979 
            'block_type' => 'toreg',
14980 
            'dbl_ovrd' => 0,
14981 
            'explicit_data_type' => 0,
14982 
            'gui_display_data_type' => 1,
14983 
            'init' => 0,
14984 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
14985 
            'mdl_handle' => 2083.00048828125,
14986 
            'model_handle' => 2083.00048828125,
14987 
            'n_bits' => 16,
14988 
            'ownership' => 1,
14989 
            'preci_type' => 1,
14990 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
14991 
            'shared_memory_name' => 'register04td',
14992 
          },
14993 
          'needs_vhdl_wrapper' => 0,
14994 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11',
14995 
        },
14996 
        'entityName' => 'x_x1',
14997 
        'ports' => {
14998 
          'ce' => {
14999 
            'attributes' => {
15000 
              'domain' => '',
15001 
              'group' => 1,
15002 
              'isCe' => 1,
15003 
              'is_floating_block' => 1,
15004 
              'period' => 1,
15005 
              'type' => 'logic',
15006 
            },
15007 
            'direction' => 'in',
15008 
            'hdlType' => 'std_logic',
15009 
            'width' => 1,
15010 
          },
15011 
          'clk' => {
15012 
            'attributes' => {
15013 
              'domain' => '',
15014 
              'group' => 1,
15015 
              'isClk' => 1,
15016 
              'is_floating_block' => 1,
15017 
              'period' => 1,
15018 
              'type' => 'logic',
15019 
            },
15020 
            'direction' => 'in',
15021 
            'hdlType' => 'std_logic',
15022 
            'width' => 1,
15023 
          },
15024 
          'clr' => {
15025 
            'attributes' => {
15026 
              'domain' => '',
15027 
              'group' => 1,
15028 
              'isClr' => 1,
15029 
              'is_floating_block' => 1,
15030 
              'period' => 1,
15031 
              'type' => 'logic',
15032 
              'valid_bit_used' => 0,
15033 
            },
15034 
            'direction' => 'in',
15035 
            'hdlType' => 'std_logic',
15036 
            'width' => 1,
15037 
          },
15038 
          'data_in' => {
15039 
            'attributes' => {
15040 
              'bin_pt' => 0,
15041 
              'is_floating_block' => 1,
15042 
              'must_be_hdl_vector' => 1,
15043 
              'period' => 1,
15044 
              'port_id' => 0,
15045 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/data_in',
15046 
              'type' => 'UFix_32_0',
15047 
            },
15048 
            'direction' => 'in',
15049 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15050 
            'width' => 32,
15051 
          },
15052 
          'dout' => {
15053 
            'attributes' => {
15054 
              'bin_pt' => 0,
15055 
              'is_floating_block' => 1,
15056 
              'must_be_hdl_vector' => 1,
15057 
              'period' => 1,
15058 
              'port_id' => 0,
15059 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/dout',
15060 
              'type' => 'UFix_32_0',
15061 
            },
15062 
            'direction' => 'out',
15063 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15064 
            'width' => 32,
15065 
          },
15066 
          'en' => {
15067 
            'attributes' => {
15068 
              'bin_pt' => 0,
15069 
              'is_floating_block' => 1,
15070 
              'must_be_hdl_vector' => 1,
15071 
              'period' => 1,
15072 
              'port_id' => 1,
15073 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register11/en',
15074 
              'type' => 'Bool',
15075 
            },
15076 
            'direction' => 'in',
15077 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15078 
            'width' => 1,
15079 
          },
15080 
        },
15081 
      },
15082 
      'entityName' => 'x_x1',
15083 
    },
15084 
    'to_register12' => {
15085 
      'connections' => {
15086 
        'ce' => 'sysgen_dut.to_register12_ce',
15087 
        'clk' => 'sysgen_dut.to_register12_clk',
15088 
        'clr' => 'sysgen_dut.to_register12_clr',
15089 
        'data_in' => 'sysgen_dut.to_register12_data_in',
15090 
        'dout' => 'to_register12.dout',
15091 
        'en' => 'sysgen_dut.to_register12_en',
15092 
      },
15093 
      'entity' => {
15094 
        'attributes' => {
15095 
          'entityAlreadyNetlisted' => 1,
15096 
          'generics' => [
15097 
          ],
15098 
          'is_floating_block' => 1,
15099 
          'mask' => {
15100 
            'Block_Handle' => 2121.00048828125,
15101 
            'Block_handle' => 2121.00048828125,
15102 
            'MDL_Handle' => 2083.00048828125,
15103 
            'MDL_handle' => 2083.00048828125,
15104 
            'arith_type' => 1,
15105 
            'bin_pt' => 14,
15106 
            'block_config' => 'sysgen_blockset:toreg_config',
15107 
            'block_handle' => 2121.00048828125,
15108 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12',
15109 
            'block_type' => 'toreg',
15110 
            'dbl_ovrd' => 0,
15111 
            'explicit_data_type' => 0,
15112 
            'gui_display_data_type' => 1,
15113 
            'init' => 0,
15114 
            'init_bit_vector' => '\'b0',
15115 
            'mdl_handle' => 2083.00048828125,
15116 
            'model_handle' => 2083.00048828125,
15117 
            'n_bits' => 16,
15118 
            'ownership' => 1,
15119 
            'preci_type' => 1,
15120 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15121 
            'shared_memory_name' => 'register05tv',
15122 
          },
15123 
          'needs_vhdl_wrapper' => 0,
15124 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12',
15125 
        },
15126 
        'entityName' => 'x_x2',
15127 
        'ports' => {
15128 
          'ce' => {
15129 
            'attributes' => {
15130 
              'domain' => '',
15131 
              'group' => 1,
15132 
              'isCe' => 1,
15133 
              'is_floating_block' => 1,
15134 
              'period' => 1,
15135 
              'type' => 'logic',
15136 
            },
15137 
            'direction' => 'in',
15138 
            'hdlType' => 'std_logic',
15139 
            'width' => 1,
15140 
          },
15141 
          'clk' => {
15142 
            'attributes' => {
15143 
              'domain' => '',
15144 
              'group' => 1,
15145 
              'isClk' => 1,
15146 
              'is_floating_block' => 1,
15147 
              'period' => 1,
15148 
              'type' => 'logic',
15149 
            },
15150 
            'direction' => 'in',
15151 
            'hdlType' => 'std_logic',
15152 
            'width' => 1,
15153 
          },
15154 
          'clr' => {
15155 
            'attributes' => {
15156 
              'domain' => '',
15157 
              'group' => 1,
15158 
              'isClr' => 1,
15159 
              'is_floating_block' => 1,
15160 
              'period' => 1,
15161 
              'type' => 'logic',
15162 
              'valid_bit_used' => 0,
15163 
            },
15164 
            'direction' => 'in',
15165 
            'hdlType' => 'std_logic',
15166 
            'width' => 1,
15167 
          },
15168 
          'data_in' => {
15169 
            'attributes' => {
15170 
              'bin_pt' => 0,
15171 
              'is_floating_block' => 1,
15172 
              'must_be_hdl_vector' => 1,
15173 
              'period' => 1,
15174 
              'port_id' => 0,
15175 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/data_in',
15176 
              'type' => 'Bool',
15177 
            },
15178 
            'direction' => 'in',
15179 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15180 
            'width' => 1,
15181 
          },
15182 
          'dout' => {
15183 
            'attributes' => {
15184 
              'bin_pt' => 0,
15185 
              'is_floating_block' => 1,
15186 
              'must_be_hdl_vector' => 1,
15187 
              'period' => 1,
15188 
              'port_id' => 0,
15189 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/dout',
15190 
              'type' => 'Bool',
15191 
            },
15192 
            'direction' => 'out',
15193 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15194 
            'width' => 1,
15195 
          },
15196 
          'en' => {
15197 
            'attributes' => {
15198 
              'bin_pt' => 0,
15199 
              'is_floating_block' => 1,
15200 
              'must_be_hdl_vector' => 1,
15201 
              'period' => 1,
15202 
              'port_id' => 1,
15203 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register12/en',
15204 
              'type' => 'Bool',
15205 
            },
15206 
            'direction' => 'in',
15207 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15208 
            'width' => 1,
15209 
          },
15210 
        },
15211 
      },
15212 
      'entityName' => 'x_x2',
15213 
    },
15214 
    'to_register13' => {
15215 
      'connections' => {
15216 
        'ce' => 'sysgen_dut.to_register13_ce',
15217 
        'clk' => 'sysgen_dut.to_register13_clk',
15218 
        'clr' => 'sysgen_dut.to_register13_clr',
15219 
        'data_in' => 'sysgen_dut.to_register13_data_in',
15220 
        'dout' => 'to_register13.dout',
15221 
        'en' => 'sysgen_dut.to_register13_en',
15222 
      },
15223 
      'entity' => {
15224 
        'attributes' => {
15225 
          'entityAlreadyNetlisted' => 1,
15226 
          'generics' => [
15227 
          ],
15228 
          'is_floating_block' => 1,
15229 
          'mask' => {
15230 
            'Block_Handle' => 2122.00048828125,
15231 
            'Block_handle' => 2122.00048828125,
15232 
            'MDL_Handle' => 2083.00048828125,
15233 
            'MDL_handle' => 2083.00048828125,
15234 
            'arith_type' => 1,
15235 
            'bin_pt' => 14,
15236 
            'block_config' => 'sysgen_blockset:toreg_config',
15237 
            'block_handle' => 2122.00048828125,
15238 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13',
15239 
            'block_type' => 'toreg',
15240 
            'dbl_ovrd' => 0,
15241 
            'explicit_data_type' => 0,
15242 
            'gui_display_data_type' => 1,
15243 
            'init' => 0,
15244 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
15245 
            'mdl_handle' => 2083.00048828125,
15246 
            'model_handle' => 2083.00048828125,
15247 
            'n_bits' => 16,
15248 
            'ownership' => 1,
15249 
            'preci_type' => 1,
15250 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15251 
            'shared_memory_name' => 'register05td',
15252 
          },
15253 
          'needs_vhdl_wrapper' => 0,
15254 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13',
15255 
        },
15256 
        'entityName' => 'x_x3',
15257 
        'ports' => {
15258 
          'ce' => {
15259 
            'attributes' => {
15260 
              'domain' => '',
15261 
              'group' => 1,
15262 
              'isCe' => 1,
15263 
              'is_floating_block' => 1,
15264 
              'period' => 1,
15265 
              'type' => 'logic',
15266 
            },
15267 
            'direction' => 'in',
15268 
            'hdlType' => 'std_logic',
15269 
            'width' => 1,
15270 
          },
15271 
          'clk' => {
15272 
            'attributes' => {
15273 
              'domain' => '',
15274 
              'group' => 1,
15275 
              'isClk' => 1,
15276 
              'is_floating_block' => 1,
15277 
              'period' => 1,
15278 
              'type' => 'logic',
15279 
            },
15280 
            'direction' => 'in',
15281 
            'hdlType' => 'std_logic',
15282 
            'width' => 1,
15283 
          },
15284 
          'clr' => {
15285 
            'attributes' => {
15286 
              'domain' => '',
15287 
              'group' => 1,
15288 
              'isClr' => 1,
15289 
              'is_floating_block' => 1,
15290 
              'period' => 1,
15291 
              'type' => 'logic',
15292 
              'valid_bit_used' => 0,
15293 
            },
15294 
            'direction' => 'in',
15295 
            'hdlType' => 'std_logic',
15296 
            'width' => 1,
15297 
          },
15298 
          'data_in' => {
15299 
            'attributes' => {
15300 
              'bin_pt' => 0,
15301 
              'is_floating_block' => 1,
15302 
              'must_be_hdl_vector' => 1,
15303 
              'period' => 1,
15304 
              'port_id' => 0,
15305 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/data_in',
15306 
              'type' => 'UFix_32_0',
15307 
            },
15308 
            'direction' => 'in',
15309 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15310 
            'width' => 32,
15311 
          },
15312 
          'dout' => {
15313 
            'attributes' => {
15314 
              'bin_pt' => 0,
15315 
              'is_floating_block' => 1,
15316 
              'must_be_hdl_vector' => 1,
15317 
              'period' => 1,
15318 
              'port_id' => 0,
15319 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/dout',
15320 
              'type' => 'UFix_32_0',
15321 
            },
15322 
            'direction' => 'out',
15323 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15324 
            'width' => 32,
15325 
          },
15326 
          'en' => {
15327 
            'attributes' => {
15328 
              'bin_pt' => 0,
15329 
              'is_floating_block' => 1,
15330 
              'must_be_hdl_vector' => 1,
15331 
              'period' => 1,
15332 
              'port_id' => 1,
15333 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register13/en',
15334 
              'type' => 'Bool',
15335 
            },
15336 
            'direction' => 'in',
15337 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15338 
            'width' => 1,
15339 
          },
15340 
        },
15341 
      },
15342 
      'entityName' => 'x_x3',
15343 
    },
15344 
    'to_register14' => {
15345 
      'connections' => {
15346 
        'ce' => 'sysgen_dut.to_register14_ce',
15347 
        'clk' => 'sysgen_dut.to_register14_clk',
15348 
        'clr' => 'sysgen_dut.to_register14_clr',
15349 
        'data_in' => 'sysgen_dut.to_register14_data_in',
15350 
        'dout' => 'to_register14.dout',
15351 
        'en' => 'sysgen_dut.to_register14_en',
15352 
      },
15353 
      'entity' => {
15354 
        'attributes' => {
15355 
          'entityAlreadyNetlisted' => 1,
15356 
          'generics' => [
15357 
          ],
15358 
          'is_floating_block' => 1,
15359 
          'mask' => {
15360 
            'Block_Handle' => 2123.00048828125,
15361 
            'Block_handle' => 2123.00048828125,
15362 
            'MDL_Handle' => 2083.00048828125,
15363 
            'MDL_handle' => 2083.00048828125,
15364 
            'arith_type' => 1,
15365 
            'bin_pt' => 14,
15366 
            'block_config' => 'sysgen_blockset:toreg_config',
15367 
            'block_handle' => 2123.00048828125,
15368 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14',
15369 
            'block_type' => 'toreg',
15370 
            'dbl_ovrd' => 0,
15371 
            'explicit_data_type' => 0,
15372 
            'gui_display_data_type' => 1,
15373 
            'init' => 0,
15374 
            'init_bit_vector' => '\'b0',
15375 
            'mdl_handle' => 2083.00048828125,
15376 
            'model_handle' => 2083.00048828125,
15377 
            'n_bits' => 16,
15378 
            'ownership' => 1,
15379 
            'preci_type' => 1,
15380 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15381 
            'shared_memory_name' => 'register06tv',
15382 
          },
15383 
          'needs_vhdl_wrapper' => 0,
15384 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14',
15385 
        },
15386 
        'entityName' => 'x_x4',
15387 
        'ports' => {
15388 
          'ce' => {
15389 
            'attributes' => {
15390 
              'domain' => '',
15391 
              'group' => 1,
15392 
              'isCe' => 1,
15393 
              'is_floating_block' => 1,
15394 
              'period' => 1,
15395 
              'type' => 'logic',
15396 
            },
15397 
            'direction' => 'in',
15398 
            'hdlType' => 'std_logic',
15399 
            'width' => 1,
15400 
          },
15401 
          'clk' => {
15402 
            'attributes' => {
15403 
              'domain' => '',
15404 
              'group' => 1,
15405 
              'isClk' => 1,
15406 
              'is_floating_block' => 1,
15407 
              'period' => 1,
15408 
              'type' => 'logic',
15409 
            },
15410 
            'direction' => 'in',
15411 
            'hdlType' => 'std_logic',
15412 
            'width' => 1,
15413 
          },
15414 
          'clr' => {
15415 
            'attributes' => {
15416 
              'domain' => '',
15417 
              'group' => 1,
15418 
              'isClr' => 1,
15419 
              'is_floating_block' => 1,
15420 
              'period' => 1,
15421 
              'type' => 'logic',
15422 
              'valid_bit_used' => 0,
15423 
            },
15424 
            'direction' => 'in',
15425 
            'hdlType' => 'std_logic',
15426 
            'width' => 1,
15427 
          },
15428 
          'data_in' => {
15429 
            'attributes' => {
15430 
              'bin_pt' => 0,
15431 
              'is_floating_block' => 1,
15432 
              'must_be_hdl_vector' => 1,
15433 
              'period' => 1,
15434 
              'port_id' => 0,
15435 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/data_in',
15436 
              'type' => 'Bool',
15437 
            },
15438 
            'direction' => 'in',
15439 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15440 
            'width' => 1,
15441 
          },
15442 
          'dout' => {
15443 
            'attributes' => {
15444 
              'bin_pt' => 0,
15445 
              'is_floating_block' => 1,
15446 
              'must_be_hdl_vector' => 1,
15447 
              'period' => 1,
15448 
              'port_id' => 0,
15449 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/dout',
15450 
              'type' => 'Bool',
15451 
            },
15452 
            'direction' => 'out',
15453 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15454 
            'width' => 1,
15455 
          },
15456 
          'en' => {
15457 
            'attributes' => {
15458 
              'bin_pt' => 0,
15459 
              'is_floating_block' => 1,
15460 
              'must_be_hdl_vector' => 1,
15461 
              'period' => 1,
15462 
              'port_id' => 1,
15463 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/en',
15464 
              'type' => 'Bool',
15465 
            },
15466 
            'direction' => 'in',
15467 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15468 
            'width' => 1,
15469 
          },
15470 
        },
15471 
      },
15472 
      'entityName' => 'x_x4',
15473 
    },
15474 
    'to_register15' => {
15475 
      'connections' => {
15476 
        'ce' => 'sysgen_dut.to_register15_ce',
15477 
        'clk' => 'sysgen_dut.to_register15_clk',
15478 
        'clr' => 'sysgen_dut.to_register15_clr',
15479 
        'data_in' => 'sysgen_dut.to_register15_data_in',
15480 
        'dout' => 'to_register15.dout',
15481 
        'en' => 'sysgen_dut.to_register15_en',
15482 
      },
15483 
      'entity' => {
15484 
        'attributes' => {
15485 
          'entityAlreadyNetlisted' => 1,
15486 
          'generics' => [
15487 
          ],
15488 
          'is_floating_block' => 1,
15489 
          'mask' => {
15490 
            'Block_Handle' => 2124.00048828125,
15491 
            'Block_handle' => 2124.00048828125,
15492 
            'MDL_Handle' => 2083.00048828125,
15493 
            'MDL_handle' => 2083.00048828125,
15494 
            'arith_type' => 1,
15495 
            'bin_pt' => 14,
15496 
            'block_config' => 'sysgen_blockset:toreg_config',
15497 
            'block_handle' => 2124.00048828125,
15498 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15',
15499 
            'block_type' => 'toreg',
15500 
            'dbl_ovrd' => 0,
15501 
            'explicit_data_type' => 0,
15502 
            'gui_display_data_type' => 1,
15503 
            'init' => 0,
15504 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
15505 
            'mdl_handle' => 2083.00048828125,
15506 
            'model_handle' => 2083.00048828125,
15507 
            'n_bits' => 16,
15508 
            'ownership' => 1,
15509 
            'preci_type' => 1,
15510 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15511 
            'shared_memory_name' => 'register06td',
15512 
          },
15513 
          'needs_vhdl_wrapper' => 0,
15514 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15',
15515 
        },
15516 
        'entityName' => 'x_x5',
15517 
        'ports' => {
15518 
          'ce' => {
15519 
            'attributes' => {
15520 
              'domain' => '',
15521 
              'group' => 1,
15522 
              'isCe' => 1,
15523 
              'is_floating_block' => 1,
15524 
              'period' => 1,
15525 
              'type' => 'logic',
15526 
            },
15527 
            'direction' => 'in',
15528 
            'hdlType' => 'std_logic',
15529 
            'width' => 1,
15530 
          },
15531 
          'clk' => {
15532 
            'attributes' => {
15533 
              'domain' => '',
15534 
              'group' => 1,
15535 
              'isClk' => 1,
15536 
              'is_floating_block' => 1,
15537 
              'period' => 1,
15538 
              'type' => 'logic',
15539 
            },
15540 
            'direction' => 'in',
15541 
            'hdlType' => 'std_logic',
15542 
            'width' => 1,
15543 
          },
15544 
          'clr' => {
15545 
            'attributes' => {
15546 
              'domain' => '',
15547 
              'group' => 1,
15548 
              'isClr' => 1,
15549 
              'is_floating_block' => 1,
15550 
              'period' => 1,
15551 
              'type' => 'logic',
15552 
              'valid_bit_used' => 0,
15553 
            },
15554 
            'direction' => 'in',
15555 
            'hdlType' => 'std_logic',
15556 
            'width' => 1,
15557 
          },
15558 
          'data_in' => {
15559 
            'attributes' => {
15560 
              'bin_pt' => 0,
15561 
              'is_floating_block' => 1,
15562 
              'must_be_hdl_vector' => 1,
15563 
              'period' => 1,
15564 
              'port_id' => 0,
15565 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/data_in',
15566 
              'type' => 'UFix_32_0',
15567 
            },
15568 
            'direction' => 'in',
15569 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15570 
            'width' => 32,
15571 
          },
15572 
          'dout' => {
15573 
            'attributes' => {
15574 
              'bin_pt' => 0,
15575 
              'is_floating_block' => 1,
15576 
              'must_be_hdl_vector' => 1,
15577 
              'period' => 1,
15578 
              'port_id' => 0,
15579 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/dout',
15580 
              'type' => 'UFix_32_0',
15581 
            },
15582 
            'direction' => 'out',
15583 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15584 
            'width' => 32,
15585 
          },
15586 
          'en' => {
15587 
            'attributes' => {
15588 
              'bin_pt' => 0,
15589 
              'is_floating_block' => 1,
15590 
              'must_be_hdl_vector' => 1,
15591 
              'period' => 1,
15592 
              'port_id' => 1,
15593 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/en',
15594 
              'type' => 'Bool',
15595 
            },
15596 
            'direction' => 'in',
15597 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15598 
            'width' => 1,
15599 
          },
15600 
        },
15601 
      },
15602 
      'entityName' => 'x_x5',
15603 
    },
15604 
    'to_register16' => {
15605 
      'connections' => {
15606 
        'ce' => 'sysgen_dut.to_register16_ce',
15607 
        'clk' => 'sysgen_dut.to_register16_clk',
15608 
        'clr' => 'sysgen_dut.to_register16_clr',
15609 
        'data_in' => 'sysgen_dut.to_register16_data_in',
15610 
        'dout' => 'to_register16.dout',
15611 
        'en' => 'sysgen_dut.to_register16_en',
15612 
      },
15613 
      'entity' => {
15614 
        'attributes' => {
15615 
          'entityAlreadyNetlisted' => 1,
15616 
          'generics' => [
15617 
          ],
15618 
          'is_floating_block' => 1,
15619 
          'mask' => {
15620 
            'Block_Handle' => 2125.00048828125,
15621 
            'Block_handle' => 2125.00048828125,
15622 
            'MDL_Handle' => 2083.00048828125,
15623 
            'MDL_handle' => 2083.00048828125,
15624 
            'arith_type' => 1,
15625 
            'bin_pt' => 14,
15626 
            'block_config' => 'sysgen_blockset:toreg_config',
15627 
            'block_handle' => 2125.00048828125,
15628 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16',
15629 
            'block_type' => 'toreg',
15630 
            'dbl_ovrd' => 0,
15631 
            'explicit_data_type' => 0,
15632 
            'gui_display_data_type' => 1,
15633 
            'init' => 0,
15634 
            'init_bit_vector' => '\'b0',
15635 
            'mdl_handle' => 2083.00048828125,
15636 
            'model_handle' => 2083.00048828125,
15637 
            'n_bits' => 16,
15638 
            'ownership' => 1,
15639 
            'preci_type' => 1,
15640 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15641 
            'shared_memory_name' => 'register07tv',
15642 
          },
15643 
          'needs_vhdl_wrapper' => 0,
15644 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16',
15645 
        },
15646 
        'entityName' => 'x_x6',
15647 
        'ports' => {
15648 
          'ce' => {
15649 
            'attributes' => {
15650 
              'domain' => '',
15651 
              'group' => 1,
15652 
              'isCe' => 1,
15653 
              'is_floating_block' => 1,
15654 
              'period' => 1,
15655 
              'type' => 'logic',
15656 
            },
15657 
            'direction' => 'in',
15658 
            'hdlType' => 'std_logic',
15659 
            'width' => 1,
15660 
          },
15661 
          'clk' => {
15662 
            'attributes' => {
15663 
              'domain' => '',
15664 
              'group' => 1,
15665 
              'isClk' => 1,
15666 
              'is_floating_block' => 1,
15667 
              'period' => 1,
15668 
              'type' => 'logic',
15669 
            },
15670 
            'direction' => 'in',
15671 
            'hdlType' => 'std_logic',
15672 
            'width' => 1,
15673 
          },
15674 
          'clr' => {
15675 
            'attributes' => {
15676 
              'domain' => '',
15677 
              'group' => 1,
15678 
              'isClr' => 1,
15679 
              'is_floating_block' => 1,
15680 
              'period' => 1,
15681 
              'type' => 'logic',
15682 
              'valid_bit_used' => 0,
15683 
            },
15684 
            'direction' => 'in',
15685 
            'hdlType' => 'std_logic',
15686 
            'width' => 1,
15687 
          },
15688 
          'data_in' => {
15689 
            'attributes' => {
15690 
              'bin_pt' => 0,
15691 
              'is_floating_block' => 1,
15692 
              'must_be_hdl_vector' => 1,
15693 
              'period' => 1,
15694 
              'port_id' => 0,
15695 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/data_in',
15696 
              'type' => 'Bool',
15697 
            },
15698 
            'direction' => 'in',
15699 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15700 
            'width' => 1,
15701 
          },
15702 
          'dout' => {
15703 
            'attributes' => {
15704 
              'bin_pt' => 0,
15705 
              'is_floating_block' => 1,
15706 
              'must_be_hdl_vector' => 1,
15707 
              'period' => 1,
15708 
              'port_id' => 0,
15709 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/dout',
15710 
              'type' => 'Bool',
15711 
            },
15712 
            'direction' => 'out',
15713 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15714 
            'width' => 1,
15715 
          },
15716 
          'en' => {
15717 
            'attributes' => {
15718 
              'bin_pt' => 0,
15719 
              'is_floating_block' => 1,
15720 
              'must_be_hdl_vector' => 1,
15721 
              'period' => 1,
15722 
              'port_id' => 1,
15723 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/en',
15724 
              'type' => 'Bool',
15725 
            },
15726 
            'direction' => 'in',
15727 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15728 
            'width' => 1,
15729 
          },
15730 
        },
15731 
      },
15732 
      'entityName' => 'x_x6',
15733 
    },
15734 
    'to_register17' => {
15735 
      'connections' => {
15736 
        'ce' => 'sysgen_dut.to_register17_ce',
15737 
        'clk' => 'sysgen_dut.to_register17_clk',
15738 
        'clr' => 'sysgen_dut.to_register17_clr',
15739 
        'data_in' => 'sysgen_dut.to_register17_data_in',
15740 
        'dout' => 'to_register17.dout',
15741 
        'en' => 'sysgen_dut.to_register17_en',
15742 
      },
15743 
      'entity' => {
15744 
        'attributes' => {
15745 
          'entityAlreadyNetlisted' => 1,
15746 
          'generics' => [
15747 
          ],
15748 
          'is_floating_block' => 1,
15749 
          'mask' => {
15750 
            'Block_Handle' => 2126.00048828125,
15751 
            'Block_handle' => 2126.00048828125,
15752 
            'MDL_Handle' => 2083.00048828125,
15753 
            'MDL_handle' => 2083.00048828125,
15754 
            'arith_type' => 1,
15755 
            'bin_pt' => 14,
15756 
            'block_config' => 'sysgen_blockset:toreg_config',
15757 
            'block_handle' => 2126.00048828125,
15758 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17',
15759 
            'block_type' => 'toreg',
15760 
            'dbl_ovrd' => 0,
15761 
            'explicit_data_type' => 0,
15762 
            'gui_display_data_type' => 1,
15763 
            'init' => 0,
15764 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
15765 
            'mdl_handle' => 2083.00048828125,
15766 
            'model_handle' => 2083.00048828125,
15767 
            'n_bits' => 16,
15768 
            'ownership' => 1,
15769 
            'preci_type' => 1,
15770 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15771 
            'shared_memory_name' => 'register07td',
15772 
          },
15773 
          'needs_vhdl_wrapper' => 0,
15774 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17',
15775 
        },
15776 
        'entityName' => 'x_x7',
15777 
        'ports' => {
15778 
          'ce' => {
15779 
            'attributes' => {
15780 
              'domain' => '',
15781 
              'group' => 1,
15782 
              'isCe' => 1,
15783 
              'is_floating_block' => 1,
15784 
              'period' => 1,
15785 
              'type' => 'logic',
15786 
            },
15787 
            'direction' => 'in',
15788 
            'hdlType' => 'std_logic',
15789 
            'width' => 1,
15790 
          },
15791 
          'clk' => {
15792 
            'attributes' => {
15793 
              'domain' => '',
15794 
              'group' => 1,
15795 
              'isClk' => 1,
15796 
              'is_floating_block' => 1,
15797 
              'period' => 1,
15798 
              'type' => 'logic',
15799 
            },
15800 
            'direction' => 'in',
15801 
            'hdlType' => 'std_logic',
15802 
            'width' => 1,
15803 
          },
15804 
          'clr' => {
15805 
            'attributes' => {
15806 
              'domain' => '',
15807 
              'group' => 1,
15808 
              'isClr' => 1,
15809 
              'is_floating_block' => 1,
15810 
              'period' => 1,
15811 
              'type' => 'logic',
15812 
              'valid_bit_used' => 0,
15813 
            },
15814 
            'direction' => 'in',
15815 
            'hdlType' => 'std_logic',
15816 
            'width' => 1,
15817 
          },
15818 
          'data_in' => {
15819 
            'attributes' => {
15820 
              'bin_pt' => 0,
15821 
              'is_floating_block' => 1,
15822 
              'must_be_hdl_vector' => 1,
15823 
              'period' => 1,
15824 
              'port_id' => 0,
15825 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/data_in',
15826 
              'type' => 'UFix_32_0',
15827 
            },
15828 
            'direction' => 'in',
15829 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15830 
            'width' => 32,
15831 
          },
15832 
          'dout' => {
15833 
            'attributes' => {
15834 
              'bin_pt' => 0,
15835 
              'is_floating_block' => 1,
15836 
              'must_be_hdl_vector' => 1,
15837 
              'period' => 1,
15838 
              'port_id' => 0,
15839 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/dout',
15840 
              'type' => 'UFix_32_0',
15841 
            },
15842 
            'direction' => 'out',
15843 
            'hdlType' => 'std_logic_vector(31 downto 0)',
15844 
            'width' => 32,
15845 
          },
15846 
          'en' => {
15847 
            'attributes' => {
15848 
              'bin_pt' => 0,
15849 
              'is_floating_block' => 1,
15850 
              'must_be_hdl_vector' => 1,
15851 
              'period' => 1,
15852 
              'port_id' => 1,
15853 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/en',
15854 
              'type' => 'Bool',
15855 
            },
15856 
            'direction' => 'in',
15857 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15858 
            'width' => 1,
15859 
          },
15860 
        },
15861 
      },
15862 
      'entityName' => 'x_x7',
15863 
    },
15864 
    'to_register18' => {
15865 
      'connections' => {
15866 
        'ce' => 'sysgen_dut.to_register18_ce',
15867 
        'clk' => 'sysgen_dut.to_register18_clk',
15868 
        'clr' => 'sysgen_dut.to_register18_clr',
15869 
        'data_in' => 'sysgen_dut.to_register18_data_in',
15870 
        'dout' => 'to_register18.dout',
15871 
        'en' => 'sysgen_dut.to_register18_en',
15872 
      },
15873 
      'entity' => {
15874 
        'attributes' => {
15875 
          'entityAlreadyNetlisted' => 1,
15876 
          'generics' => [
15877 
          ],
15878 
          'is_floating_block' => 1,
15879 
          'mask' => {
15880 
            'Block_Handle' => 2127.00048828125,
15881 
            'Block_handle' => 2127.00048828125,
15882 
            'MDL_Handle' => 2083.00048828125,
15883 
            'MDL_handle' => 2083.00048828125,
15884 
            'arith_type' => 1,
15885 
            'bin_pt' => 14,
15886 
            'block_config' => 'sysgen_blockset:toreg_config',
15887 
            'block_handle' => 2127.00048828125,
15888 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18',
15889 
            'block_type' => 'toreg',
15890 
            'dbl_ovrd' => 0,
15891 
            'explicit_data_type' => 0,
15892 
            'gui_display_data_type' => 1,
15893 
            'init' => 0,
15894 
            'init_bit_vector' => '\'b0',
15895 
            'mdl_handle' => 2083.00048828125,
15896 
            'model_handle' => 2083.00048828125,
15897 
            'n_bits' => 16,
15898 
            'ownership' => 1,
15899 
            'preci_type' => 1,
15900 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
15901 
            'shared_memory_name' => 'DMA_Host2Board_Busy',
15902 
          },
15903 
          'needs_vhdl_wrapper' => 0,
15904 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18',
15905 
        },
15906 
        'entityName' => 'x_x8',
15907 
        'ports' => {
15908 
          'ce' => {
15909 
            'attributes' => {
15910 
              'domain' => '',
15911 
              'group' => 1,
15912 
              'isCe' => 1,
15913 
              'is_floating_block' => 1,
15914 
              'period' => 1,
15915 
              'type' => 'logic',
15916 
            },
15917 
            'direction' => 'in',
15918 
            'hdlType' => 'std_logic',
15919 
            'width' => 1,
15920 
          },
15921 
          'clk' => {
15922 
            'attributes' => {
15923 
              'domain' => '',
15924 
              'group' => 1,
15925 
              'isClk' => 1,
15926 
              'is_floating_block' => 1,
15927 
              'period' => 1,
15928 
              'type' => 'logic',
15929 
            },
15930 
            'direction' => 'in',
15931 
            'hdlType' => 'std_logic',
15932 
            'width' => 1,
15933 
          },
15934 
          'clr' => {
15935 
            'attributes' => {
15936 
              'domain' => '',
15937 
              'group' => 1,
15938 
              'isClr' => 1,
15939 
              'is_floating_block' => 1,
15940 
              'period' => 1,
15941 
              'type' => 'logic',
15942 
              'valid_bit_used' => 0,
15943 
            },
15944 
            'direction' => 'in',
15945 
            'hdlType' => 'std_logic',
15946 
            'width' => 1,
15947 
          },
15948 
          'data_in' => {
15949 
            'attributes' => {
15950 
              'bin_pt' => 0,
15951 
              'is_floating_block' => 1,
15952 
              'must_be_hdl_vector' => 1,
15953 
              'period' => 1,
15954 
              'port_id' => 0,
15955 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/data_in',
15956 
              'type' => 'UFix_1_0',
15957 
            },
15958 
            'direction' => 'in',
15959 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15960 
            'width' => 1,
15961 
          },
15962 
          'dout' => {
15963 
            'attributes' => {
15964 
              'bin_pt' => 0,
15965 
              'is_floating_block' => 1,
15966 
              'must_be_hdl_vector' => 1,
15967 
              'period' => 1,
15968 
              'port_id' => 0,
15969 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/dout',
15970 
              'type' => 'UFix_1_0',
15971 
            },
15972 
            'direction' => 'out',
15973 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15974 
            'width' => 1,
15975 
          },
15976 
          'en' => {
15977 
            'attributes' => {
15978 
              'bin_pt' => 0,
15979 
              'is_floating_block' => 1,
15980 
              'must_be_hdl_vector' => 1,
15981 
              'period' => 1,
15982 
              'port_id' => 1,
15983 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/en',
15984 
              'type' => 'Bool',
15985 
            },
15986 
            'direction' => 'in',
15987 
            'hdlType' => 'std_logic_vector(0 downto 0)',
15988 
            'width' => 1,
15989 
          },
15990 
        },
15991 
      },
15992 
      'entityName' => 'x_x8',
15993 
    },
15994 
    'to_register19' => {
15995 
      'connections' => {
15996 
        'ce' => 'sysgen_dut.to_register19_ce',
15997 
        'clk' => 'sysgen_dut.to_register19_clk',
15998 
        'clr' => 'sysgen_dut.to_register19_clr',
15999 
        'data_in' => 'sysgen_dut.to_register19_data_in',
16000 
        'dout' => 'to_register19.dout',
16001 
        'en' => 'sysgen_dut.to_register19_en',
16002 
      },
16003 
      'entity' => {
16004 
        'attributes' => {
16005 
          'entityAlreadyNetlisted' => 1,
16006 
          'generics' => [
16007 
          ],
16008 
          'is_floating_block' => 1,
16009 
          'mask' => {
16010 
            'Block_Handle' => 2128.00048828125,
16011 
            'Block_handle' => 2128.00048828125,
16012 
            'MDL_Handle' => 2083.00048828125,
16013 
            'MDL_handle' => 2083.00048828125,
16014 
            'arith_type' => 1,
16015 
            'bin_pt' => 14,
16016 
            'block_config' => 'sysgen_blockset:toreg_config',
16017 
            'block_handle' => 2128.00048828125,
16018 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19',
16019 
            'block_type' => 'toreg',
16020 
            'dbl_ovrd' => 0,
16021 
            'explicit_data_type' => 0,
16022 
            'gui_display_data_type' => 1,
16023 
            'init' => 0,
16024 
            'init_bit_vector' => '\'b0',
16025 
            'mdl_handle' => 2083.00048828125,
16026 
            'model_handle' => 2083.00048828125,
16027 
            'n_bits' => 16,
16028 
            'ownership' => 1,
16029 
            'preci_type' => 1,
16030 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16031 
            'shared_memory_name' => 'DMA_Host2Board_Done',
16032 
          },
16033 
          'needs_vhdl_wrapper' => 0,
16034 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19',
16035 
        },
16036 
        'entityName' => 'x_x9',
16037 
        'ports' => {
16038 
          'ce' => {
16039 
            'attributes' => {
16040 
              'domain' => '',
16041 
              'group' => 1,
16042 
              'isCe' => 1,
16043 
              'is_floating_block' => 1,
16044 
              'period' => 1,
16045 
              'type' => 'logic',
16046 
            },
16047 
            'direction' => 'in',
16048 
            'hdlType' => 'std_logic',
16049 
            'width' => 1,
16050 
          },
16051 
          'clk' => {
16052 
            'attributes' => {
16053 
              'domain' => '',
16054 
              'group' => 1,
16055 
              'isClk' => 1,
16056 
              'is_floating_block' => 1,
16057 
              'period' => 1,
16058 
              'type' => 'logic',
16059 
            },
16060 
            'direction' => 'in',
16061 
            'hdlType' => 'std_logic',
16062 
            'width' => 1,
16063 
          },
16064 
          'clr' => {
16065 
            'attributes' => {
16066 
              'domain' => '',
16067 
              'group' => 1,
16068 
              'isClr' => 1,
16069 
              'is_floating_block' => 1,
16070 
              'period' => 1,
16071 
              'type' => 'logic',
16072 
              'valid_bit_used' => 0,
16073 
            },
16074 
            'direction' => 'in',
16075 
            'hdlType' => 'std_logic',
16076 
            'width' => 1,
16077 
          },
16078 
          'data_in' => {
16079 
            'attributes' => {
16080 
              'bin_pt' => 0,
16081 
              'is_floating_block' => 1,
16082 
              'must_be_hdl_vector' => 1,
16083 
              'period' => 1,
16084 
              'port_id' => 0,
16085 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/data_in',
16086 
              'type' => 'UFix_1_0',
16087 
            },
16088 
            'direction' => 'in',
16089 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16090 
            'width' => 1,
16091 
          },
16092 
          'dout' => {
16093 
            'attributes' => {
16094 
              'bin_pt' => 0,
16095 
              'is_floating_block' => 1,
16096 
              'must_be_hdl_vector' => 1,
16097 
              'period' => 1,
16098 
              'port_id' => 0,
16099 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/dout',
16100 
              'type' => 'UFix_1_0',
16101 
            },
16102 
            'direction' => 'out',
16103 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16104 
            'width' => 1,
16105 
          },
16106 
          'en' => {
16107 
            'attributes' => {
16108 
              'bin_pt' => 0,
16109 
              'is_floating_block' => 1,
16110 
              'must_be_hdl_vector' => 1,
16111 
              'period' => 1,
16112 
              'port_id' => 1,
16113 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/en',
16114 
              'type' => 'Bool',
16115 
            },
16116 
            'direction' => 'in',
16117 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16118 
            'width' => 1,
16119 
          },
16120 
        },
16121 
      },
16122 
      'entityName' => 'x_x9',
16123 
    },
16124 
    'to_register2' => {
16125 
      'connections' => {
16126 
        'ce' => 'sysgen_dut.to_register2_ce',
16127 
        'clk' => 'sysgen_dut.to_register2_clk',
16128 
        'clr' => 'sysgen_dut.to_register2_clr',
16129 
        'data_in' => 'sysgen_dut.to_register2_data_in',
16130 
        'dout' => 'to_register2.dout',
16131 
        'en' => 'sysgen_dut.to_register2_en',
16132 
      },
16133 
      'entity' => {
16134 
        'attributes' => {
16135 
          'entityAlreadyNetlisted' => 1,
16136 
          'generics' => [
16137 
          ],
16138 
          'is_floating_block' => 1,
16139 
          'mask' => {
16140 
            'Block_Handle' => 2129.00048828125,
16141 
            'Block_handle' => 2129.00048828125,
16142 
            'MDL_Handle' => 2083.00048828125,
16143 
            'MDL_handle' => 2083.00048828125,
16144 
            'arith_type' => 1,
16145 
            'bin_pt' => 14,
16146 
            'block_config' => 'sysgen_blockset:toreg_config',
16147 
            'block_handle' => 2129.00048828125,
16148 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2',
16149 
            'block_type' => 'toreg',
16150 
            'dbl_ovrd' => 0,
16151 
            'explicit_data_type' => 0,
16152 
            'gui_display_data_type' => 1,
16153 
            'init' => 0,
16154 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
16155 
            'mdl_handle' => 2083.00048828125,
16156 
            'model_handle' => 2083.00048828125,
16157 
            'n_bits' => 16,
16158 
            'ownership' => 1,
16159 
            'preci_type' => 1,
16160 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16161 
            'shared_memory_name' => 'debug3i',
16162 
          },
16163 
          'needs_vhdl_wrapper' => 0,
16164 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2',
16165 
        },
16166 
        'entityName' => 'x_x10',
16167 
        'ports' => {
16168 
          'ce' => {
16169 
            'attributes' => {
16170 
              'domain' => '',
16171 
              'group' => 1,
16172 
              'isCe' => 1,
16173 
              'is_floating_block' => 1,
16174 
              'period' => 1,
16175 
              'type' => 'logic',
16176 
            },
16177 
            'direction' => 'in',
16178 
            'hdlType' => 'std_logic',
16179 
            'width' => 1,
16180 
          },
16181 
          'clk' => {
16182 
            'attributes' => {
16183 
              'domain' => '',
16184 
              'group' => 1,
16185 
              'isClk' => 1,
16186 
              'is_floating_block' => 1,
16187 
              'period' => 1,
16188 
              'type' => 'logic',
16189 
            },
16190 
            'direction' => 'in',
16191 
            'hdlType' => 'std_logic',
16192 
            'width' => 1,
16193 
          },
16194 
          'clr' => {
16195 
            'attributes' => {
16196 
              'domain' => '',
16197 
              'group' => 1,
16198 
              'isClr' => 1,
16199 
              'is_floating_block' => 1,
16200 
              'period' => 1,
16201 
              'type' => 'logic',
16202 
              'valid_bit_used' => 0,
16203 
            },
16204 
            'direction' => 'in',
16205 
            'hdlType' => 'std_logic',
16206 
            'width' => 1,
16207 
          },
16208 
          'data_in' => {
16209 
            'attributes' => {
16210 
              'bin_pt' => 0,
16211 
              'is_floating_block' => 1,
16212 
              'must_be_hdl_vector' => 1,
16213 
              'period' => 1,
16214 
              'port_id' => 0,
16215 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/data_in',
16216 
              'type' => 'UFix_32_0',
16217 
            },
16218 
            'direction' => 'in',
16219 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16220 
            'width' => 32,
16221 
          },
16222 
          'dout' => {
16223 
            'attributes' => {
16224 
              'bin_pt' => 0,
16225 
              'is_floating_block' => 1,
16226 
              'must_be_hdl_vector' => 1,
16227 
              'period' => 1,
16228 
              'port_id' => 0,
16229 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/dout',
16230 
              'type' => 'UFix_32_0',
16231 
            },
16232 
            'direction' => 'out',
16233 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16234 
            'width' => 32,
16235 
          },
16236 
          'en' => {
16237 
            'attributes' => {
16238 
              'bin_pt' => 0,
16239 
              'is_floating_block' => 1,
16240 
              'must_be_hdl_vector' => 1,
16241 
              'period' => 1,
16242 
              'port_id' => 1,
16243 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register2/en',
16244 
              'type' => 'Bool',
16245 
            },
16246 
            'direction' => 'in',
16247 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16248 
            'width' => 1,
16249 
          },
16250 
        },
16251 
      },
16252 
      'entityName' => 'x_x10',
16253 
    },
16254 
    'to_register20' => {
16255 
      'connections' => {
16256 
        'ce' => 'sysgen_dut.to_register20_ce',
16257 
        'clk' => 'sysgen_dut.to_register20_clk',
16258 
        'clr' => 'sysgen_dut.to_register20_clr',
16259 
        'data_in' => 'sysgen_dut.to_register20_data_in',
16260 
        'dout' => 'to_register20.dout',
16261 
        'en' => 'sysgen_dut.to_register20_en',
16262 
      },
16263 
      'entity' => {
16264 
        'attributes' => {
16265 
          'entityAlreadyNetlisted' => 1,
16266 
          'generics' => [
16267 
          ],
16268 
          'is_floating_block' => 1,
16269 
          'mask' => {
16270 
            'Block_Handle' => 2130.00048828125,
16271 
            'Block_handle' => 2130.00048828125,
16272 
            'MDL_Handle' => 2083.00048828125,
16273 
            'MDL_handle' => 2083.00048828125,
16274 
            'arith_type' => 1,
16275 
            'bin_pt' => 14,
16276 
            'block_config' => 'sysgen_blockset:toreg_config',
16277 
            'block_handle' => 2130.00048828125,
16278 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20',
16279 
            'block_type' => 'toreg',
16280 
            'dbl_ovrd' => 0,
16281 
            'explicit_data_type' => 0,
16282 
            'gui_display_data_type' => 1,
16283 
            'init' => 0,
16284 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
16285 
            'mdl_handle' => 2083.00048828125,
16286 
            'model_handle' => 2083.00048828125,
16287 
            'n_bits' => 16,
16288 
            'ownership' => 1,
16289 
            'preci_type' => 1,
16290 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16291 
            'shared_memory_name' => 'debug4i',
16292 
          },
16293 
          'needs_vhdl_wrapper' => 0,
16294 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20',
16295 
        },
16296 
        'entityName' => 'x_x11',
16297 
        'ports' => {
16298 
          'ce' => {
16299 
            'attributes' => {
16300 
              'domain' => '',
16301 
              'group' => 1,
16302 
              'isCe' => 1,
16303 
              'is_floating_block' => 1,
16304 
              'period' => 1,
16305 
              'type' => 'logic',
16306 
            },
16307 
            'direction' => 'in',
16308 
            'hdlType' => 'std_logic',
16309 
            'width' => 1,
16310 
          },
16311 
          'clk' => {
16312 
            'attributes' => {
16313 
              'domain' => '',
16314 
              'group' => 1,
16315 
              'isClk' => 1,
16316 
              'is_floating_block' => 1,
16317 
              'period' => 1,
16318 
              'type' => 'logic',
16319 
            },
16320 
            'direction' => 'in',
16321 
            'hdlType' => 'std_logic',
16322 
            'width' => 1,
16323 
          },
16324 
          'clr' => {
16325 
            'attributes' => {
16326 
              'domain' => '',
16327 
              'group' => 1,
16328 
              'isClr' => 1,
16329 
              'is_floating_block' => 1,
16330 
              'period' => 1,
16331 
              'type' => 'logic',
16332 
              'valid_bit_used' => 0,
16333 
            },
16334 
            'direction' => 'in',
16335 
            'hdlType' => 'std_logic',
16336 
            'width' => 1,
16337 
          },
16338 
          'data_in' => {
16339 
            'attributes' => {
16340 
              'bin_pt' => 0,
16341 
              'is_floating_block' => 1,
16342 
              'must_be_hdl_vector' => 1,
16343 
              'period' => 1,
16344 
              'port_id' => 0,
16345 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/data_in',
16346 
              'type' => 'UFix_32_0',
16347 
            },
16348 
            'direction' => 'in',
16349 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16350 
            'width' => 32,
16351 
          },
16352 
          'dout' => {
16353 
            'attributes' => {
16354 
              'bin_pt' => 0,
16355 
              'is_floating_block' => 1,
16356 
              'must_be_hdl_vector' => 1,
16357 
              'period' => 1,
16358 
              'port_id' => 0,
16359 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/dout',
16360 
              'type' => 'UFix_32_0',
16361 
            },
16362 
            'direction' => 'out',
16363 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16364 
            'width' => 32,
16365 
          },
16366 
          'en' => {
16367 
            'attributes' => {
16368 
              'bin_pt' => 0,
16369 
              'is_floating_block' => 1,
16370 
              'must_be_hdl_vector' => 1,
16371 
              'period' => 1,
16372 
              'port_id' => 1,
16373 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/en',
16374 
              'type' => 'Bool',
16375 
            },
16376 
            'direction' => 'in',
16377 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16378 
            'width' => 1,
16379 
          },
16380 
        },
16381 
      },
16382 
      'entityName' => 'x_x11',
16383 
    },
16384 
    'to_register21' => {
16385 
      'connections' => {
16386 
        'ce' => 'sysgen_dut.to_register21_ce',
16387 
        'clk' => 'sysgen_dut.to_register21_clk',
16388 
        'clr' => 'sysgen_dut.to_register21_clr',
16389 
        'data_in' => 'sysgen_dut.to_register21_data_in',
16390 
        'dout' => 'to_register21.dout',
16391 
        'en' => 'sysgen_dut.to_register21_en',
16392 
      },
16393 
      'entity' => {
16394 
        'attributes' => {
16395 
          'entityAlreadyNetlisted' => 1,
16396 
          'generics' => [
16397 
          ],
16398 
          'is_floating_block' => 1,
16399 
          'mask' => {
16400 
            'Block_Handle' => 2131.00048828125,
16401 
            'Block_handle' => 2131.00048828125,
16402 
            'MDL_Handle' => 2083.00048828125,
16403 
            'MDL_handle' => 2083.00048828125,
16404 
            'arith_type' => 1,
16405 
            'bin_pt' => 14,
16406 
            'block_config' => 'sysgen_blockset:toreg_config',
16407 
            'block_handle' => 2131.00048828125,
16408 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21',
16409 
            'block_type' => 'toreg',
16410 
            'dbl_ovrd' => 0,
16411 
            'explicit_data_type' => 0,
16412 
            'gui_display_data_type' => 1,
16413 
            'init' => 0,
16414 
            'init_bit_vector' => '\'b0',
16415 
            'mdl_handle' => 2083.00048828125,
16416 
            'model_handle' => 2083.00048828125,
16417 
            'n_bits' => 16,
16418 
            'ownership' => 1,
16419 
            'preci_type' => 1,
16420 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16421 
            'shared_memory_name' => 'register09tv',
16422 
          },
16423 
          'needs_vhdl_wrapper' => 0,
16424 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21',
16425 
        },
16426 
        'entityName' => 'x_x12',
16427 
        'ports' => {
16428 
          'ce' => {
16429 
            'attributes' => {
16430 
              'domain' => '',
16431 
              'group' => 1,
16432 
              'isCe' => 1,
16433 
              'is_floating_block' => 1,
16434 
              'period' => 1,
16435 
              'type' => 'logic',
16436 
            },
16437 
            'direction' => 'in',
16438 
            'hdlType' => 'std_logic',
16439 
            'width' => 1,
16440 
          },
16441 
          'clk' => {
16442 
            'attributes' => {
16443 
              'domain' => '',
16444 
              'group' => 1,
16445 
              'isClk' => 1,
16446 
              'is_floating_block' => 1,
16447 
              'period' => 1,
16448 
              'type' => 'logic',
16449 
            },
16450 
            'direction' => 'in',
16451 
            'hdlType' => 'std_logic',
16452 
            'width' => 1,
16453 
          },
16454 
          'clr' => {
16455 
            'attributes' => {
16456 
              'domain' => '',
16457 
              'group' => 1,
16458 
              'isClr' => 1,
16459 
              'is_floating_block' => 1,
16460 
              'period' => 1,
16461 
              'type' => 'logic',
16462 
              'valid_bit_used' => 0,
16463 
            },
16464 
            'direction' => 'in',
16465 
            'hdlType' => 'std_logic',
16466 
            'width' => 1,
16467 
          },
16468 
          'data_in' => {
16469 
            'attributes' => {
16470 
              'bin_pt' => 0,
16471 
              'is_floating_block' => 1,
16472 
              'must_be_hdl_vector' => 1,
16473 
              'period' => 1,
16474 
              'port_id' => 0,
16475 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/data_in',
16476 
              'type' => 'Bool',
16477 
            },
16478 
            'direction' => 'in',
16479 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16480 
            'width' => 1,
16481 
          },
16482 
          'dout' => {
16483 
            'attributes' => {
16484 
              'bin_pt' => 0,
16485 
              'is_floating_block' => 1,
16486 
              'must_be_hdl_vector' => 1,
16487 
              'period' => 1,
16488 
              'port_id' => 0,
16489 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/dout',
16490 
              'type' => 'Bool',
16491 
            },
16492 
            'direction' => 'out',
16493 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16494 
            'width' => 1,
16495 
          },
16496 
          'en' => {
16497 
            'attributes' => {
16498 
              'bin_pt' => 0,
16499 
              'is_floating_block' => 1,
16500 
              'must_be_hdl_vector' => 1,
16501 
              'period' => 1,
16502 
              'port_id' => 1,
16503 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/en',
16504 
              'type' => 'Bool',
16505 
            },
16506 
            'direction' => 'in',
16507 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16508 
            'width' => 1,
16509 
          },
16510 
        },
16511 
      },
16512 
      'entityName' => 'x_x12',
16513 
    },
16514 
    'to_register22' => {
16515 
      'connections' => {
16516 
        'ce' => 'sysgen_dut.to_register22_ce',
16517 
        'clk' => 'sysgen_dut.to_register22_clk',
16518 
        'clr' => 'sysgen_dut.to_register22_clr',
16519 
        'data_in' => 'sysgen_dut.to_register22_data_in',
16520 
        'dout' => 'to_register22.dout',
16521 
        'en' => 'sysgen_dut.to_register22_en',
16522 
      },
16523 
      'entity' => {
16524 
        'attributes' => {
16525 
          'entityAlreadyNetlisted' => 1,
16526 
          'generics' => [
16527 
          ],
16528 
          'is_floating_block' => 1,
16529 
          'mask' => {
16530 
            'Block_Handle' => 2132.00048828125,
16531 
            'Block_handle' => 2132.00048828125,
16532 
            'MDL_Handle' => 2083.00048828125,
16533 
            'MDL_handle' => 2083.00048828125,
16534 
            'arith_type' => 1,
16535 
            'bin_pt' => 14,
16536 
            'block_config' => 'sysgen_blockset:toreg_config',
16537 
            'block_handle' => 2132.00048828125,
16538 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22',
16539 
            'block_type' => 'toreg',
16540 
            'dbl_ovrd' => 0,
16541 
            'explicit_data_type' => 0,
16542 
            'gui_display_data_type' => 1,
16543 
            'init' => 0,
16544 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
16545 
            'mdl_handle' => 2083.00048828125,
16546 
            'model_handle' => 2083.00048828125,
16547 
            'n_bits' => 16,
16548 
            'ownership' => 1,
16549 
            'preci_type' => 1,
16550 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16551 
            'shared_memory_name' => 'register09td',
16552 
          },
16553 
          'needs_vhdl_wrapper' => 0,
16554 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22',
16555 
        },
16556 
        'entityName' => 'x_x13',
16557 
        'ports' => {
16558 
          'ce' => {
16559 
            'attributes' => {
16560 
              'domain' => '',
16561 
              'group' => 1,
16562 
              'isCe' => 1,
16563 
              'is_floating_block' => 1,
16564 
              'period' => 1,
16565 
              'type' => 'logic',
16566 
            },
16567 
            'direction' => 'in',
16568 
            'hdlType' => 'std_logic',
16569 
            'width' => 1,
16570 
          },
16571 
          'clk' => {
16572 
            'attributes' => {
16573 
              'domain' => '',
16574 
              'group' => 1,
16575 
              'isClk' => 1,
16576 
              'is_floating_block' => 1,
16577 
              'period' => 1,
16578 
              'type' => 'logic',
16579 
            },
16580 
            'direction' => 'in',
16581 
            'hdlType' => 'std_logic',
16582 
            'width' => 1,
16583 
          },
16584 
          'clr' => {
16585 
            'attributes' => {
16586 
              'domain' => '',
16587 
              'group' => 1,
16588 
              'isClr' => 1,
16589 
              'is_floating_block' => 1,
16590 
              'period' => 1,
16591 
              'type' => 'logic',
16592 
              'valid_bit_used' => 0,
16593 
            },
16594 
            'direction' => 'in',
16595 
            'hdlType' => 'std_logic',
16596 
            'width' => 1,
16597 
          },
16598 
          'data_in' => {
16599 
            'attributes' => {
16600 
              'bin_pt' => 0,
16601 
              'is_floating_block' => 1,
16602 
              'must_be_hdl_vector' => 1,
16603 
              'period' => 1,
16604 
              'port_id' => 0,
16605 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/data_in',
16606 
              'type' => 'UFix_32_0',
16607 
            },
16608 
            'direction' => 'in',
16609 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16610 
            'width' => 32,
16611 
          },
16612 
          'dout' => {
16613 
            'attributes' => {
16614 
              'bin_pt' => 0,
16615 
              'is_floating_block' => 1,
16616 
              'must_be_hdl_vector' => 1,
16617 
              'period' => 1,
16618 
              'port_id' => 0,
16619 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/dout',
16620 
              'type' => 'UFix_32_0',
16621 
            },
16622 
            'direction' => 'out',
16623 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16624 
            'width' => 32,
16625 
          },
16626 
          'en' => {
16627 
            'attributes' => {
16628 
              'bin_pt' => 0,
16629 
              'is_floating_block' => 1,
16630 
              'must_be_hdl_vector' => 1,
16631 
              'period' => 1,
16632 
              'port_id' => 1,
16633 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/en',
16634 
              'type' => 'Bool',
16635 
            },
16636 
            'direction' => 'in',
16637 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16638 
            'width' => 1,
16639 
          },
16640 
        },
16641 
      },
16642 
      'entityName' => 'x_x13',
16643 
    },
16644 
    'to_register23' => {
16645 
      'connections' => {
16646 
        'ce' => 'sysgen_dut.to_register23_ce',
16647 
        'clk' => 'sysgen_dut.to_register23_clk',
16648 
        'clr' => 'sysgen_dut.to_register23_clr',
16649 
        'data_in' => 'sysgen_dut.to_register23_data_in',
16650 
        'dout' => 'to_register23.dout',
16651 
        'en' => 'sysgen_dut.to_register23_en',
16652 
      },
16653 
      'entity' => {
16654 
        'attributes' => {
16655 
          'entityAlreadyNetlisted' => 1,
16656 
          'generics' => [
16657 
          ],
16658 
          'is_floating_block' => 1,
16659 
          'mask' => {
16660 
            'Block_Handle' => 2133.00048828125,
16661 
            'Block_handle' => 2133.00048828125,
16662 
            'MDL_Handle' => 2083.00048828125,
16663 
            'MDL_handle' => 2083.00048828125,
16664 
            'arith_type' => 1,
16665 
            'bin_pt' => 14,
16666 
            'block_config' => 'sysgen_blockset:toreg_config',
16667 
            'block_handle' => 2133.00048828125,
16668 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23',
16669 
            'block_type' => 'toreg',
16670 
            'dbl_ovrd' => 0,
16671 
            'explicit_data_type' => 0,
16672 
            'gui_display_data_type' => 1,
16673 
            'init' => 0,
16674 
            'init_bit_vector' => '\'b0',
16675 
            'mdl_handle' => 2083.00048828125,
16676 
            'model_handle' => 2083.00048828125,
16677 
            'n_bits' => 16,
16678 
            'ownership' => 1,
16679 
            'preci_type' => 1,
16680 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16681 
            'shared_memory_name' => 'register10tv',
16682 
          },
16683 
          'needs_vhdl_wrapper' => 0,
16684 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23',
16685 
        },
16686 
        'entityName' => 'x_x14',
16687 
        'ports' => {
16688 
          'ce' => {
16689 
            'attributes' => {
16690 
              'domain' => '',
16691 
              'group' => 1,
16692 
              'isCe' => 1,
16693 
              'is_floating_block' => 1,
16694 
              'period' => 1,
16695 
              'type' => 'logic',
16696 
            },
16697 
            'direction' => 'in',
16698 
            'hdlType' => 'std_logic',
16699 
            'width' => 1,
16700 
          },
16701 
          'clk' => {
16702 
            'attributes' => {
16703 
              'domain' => '',
16704 
              'group' => 1,
16705 
              'isClk' => 1,
16706 
              'is_floating_block' => 1,
16707 
              'period' => 1,
16708 
              'type' => 'logic',
16709 
            },
16710 
            'direction' => 'in',
16711 
            'hdlType' => 'std_logic',
16712 
            'width' => 1,
16713 
          },
16714 
          'clr' => {
16715 
            'attributes' => {
16716 
              'domain' => '',
16717 
              'group' => 1,
16718 
              'isClr' => 1,
16719 
              'is_floating_block' => 1,
16720 
              'period' => 1,
16721 
              'type' => 'logic',
16722 
              'valid_bit_used' => 0,
16723 
            },
16724 
            'direction' => 'in',
16725 
            'hdlType' => 'std_logic',
16726 
            'width' => 1,
16727 
          },
16728 
          'data_in' => {
16729 
            'attributes' => {
16730 
              'bin_pt' => 0,
16731 
              'is_floating_block' => 1,
16732 
              'must_be_hdl_vector' => 1,
16733 
              'period' => 1,
16734 
              'port_id' => 0,
16735 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/data_in',
16736 
              'type' => 'Bool',
16737 
            },
16738 
            'direction' => 'in',
16739 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16740 
            'width' => 1,
16741 
          },
16742 
          'dout' => {
16743 
            'attributes' => {
16744 
              'bin_pt' => 0,
16745 
              'is_floating_block' => 1,
16746 
              'must_be_hdl_vector' => 1,
16747 
              'period' => 1,
16748 
              'port_id' => 0,
16749 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/dout',
16750 
              'type' => 'Bool',
16751 
            },
16752 
            'direction' => 'out',
16753 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16754 
            'width' => 1,
16755 
          },
16756 
          'en' => {
16757 
            'attributes' => {
16758 
              'bin_pt' => 0,
16759 
              'is_floating_block' => 1,
16760 
              'must_be_hdl_vector' => 1,
16761 
              'period' => 1,
16762 
              'port_id' => 1,
16763 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/en',
16764 
              'type' => 'Bool',
16765 
            },
16766 
            'direction' => 'in',
16767 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16768 
            'width' => 1,
16769 
          },
16770 
        },
16771 
      },
16772 
      'entityName' => 'x_x14',
16773 
    },
16774 
    'to_register24' => {
16775 
      'connections' => {
16776 
        'ce' => 'sysgen_dut.to_register24_ce',
16777 
        'clk' => 'sysgen_dut.to_register24_clk',
16778 
        'clr' => 'sysgen_dut.to_register24_clr',
16779 
        'data_in' => 'sysgen_dut.to_register24_data_in',
16780 
        'dout' => 'to_register24.dout',
16781 
        'en' => 'sysgen_dut.to_register24_en',
16782 
      },
16783 
      'entity' => {
16784 
        'attributes' => {
16785 
          'entityAlreadyNetlisted' => 1,
16786 
          'generics' => [
16787 
          ],
16788 
          'is_floating_block' => 1,
16789 
          'mask' => {
16790 
            'Block_Handle' => 2134.00048828125,
16791 
            'Block_handle' => 2134.00048828125,
16792 
            'MDL_Handle' => 2083.00048828125,
16793 
            'MDL_handle' => 2083.00048828125,
16794 
            'arith_type' => 1,
16795 
            'bin_pt' => 14,
16796 
            'block_config' => 'sysgen_blockset:toreg_config',
16797 
            'block_handle' => 2134.00048828125,
16798 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24',
16799 
            'block_type' => 'toreg',
16800 
            'dbl_ovrd' => 0,
16801 
            'explicit_data_type' => 0,
16802 
            'gui_display_data_type' => 1,
16803 
            'init' => 0,
16804 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
16805 
            'mdl_handle' => 2083.00048828125,
16806 
            'model_handle' => 2083.00048828125,
16807 
            'n_bits' => 16,
16808 
            'ownership' => 1,
16809 
            'preci_type' => 1,
16810 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16811 
            'shared_memory_name' => 'register10td',
16812 
          },
16813 
          'needs_vhdl_wrapper' => 0,
16814 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24',
16815 
        },
16816 
        'entityName' => 'x_x15',
16817 
        'ports' => {
16818 
          'ce' => {
16819 
            'attributes' => {
16820 
              'domain' => '',
16821 
              'group' => 1,
16822 
              'isCe' => 1,
16823 
              'is_floating_block' => 1,
16824 
              'period' => 1,
16825 
              'type' => 'logic',
16826 
            },
16827 
            'direction' => 'in',
16828 
            'hdlType' => 'std_logic',
16829 
            'width' => 1,
16830 
          },
16831 
          'clk' => {
16832 
            'attributes' => {
16833 
              'domain' => '',
16834 
              'group' => 1,
16835 
              'isClk' => 1,
16836 
              'is_floating_block' => 1,
16837 
              'period' => 1,
16838 
              'type' => 'logic',
16839 
            },
16840 
            'direction' => 'in',
16841 
            'hdlType' => 'std_logic',
16842 
            'width' => 1,
16843 
          },
16844 
          'clr' => {
16845 
            'attributes' => {
16846 
              'domain' => '',
16847 
              'group' => 1,
16848 
              'isClr' => 1,
16849 
              'is_floating_block' => 1,
16850 
              'period' => 1,
16851 
              'type' => 'logic',
16852 
              'valid_bit_used' => 0,
16853 
            },
16854 
            'direction' => 'in',
16855 
            'hdlType' => 'std_logic',
16856 
            'width' => 1,
16857 
          },
16858 
          'data_in' => {
16859 
            'attributes' => {
16860 
              'bin_pt' => 0,
16861 
              'is_floating_block' => 1,
16862 
              'must_be_hdl_vector' => 1,
16863 
              'period' => 1,
16864 
              'port_id' => 0,
16865 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/data_in',
16866 
              'type' => 'UFix_32_0',
16867 
            },
16868 
            'direction' => 'in',
16869 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16870 
            'width' => 32,
16871 
          },
16872 
          'dout' => {
16873 
            'attributes' => {
16874 
              'bin_pt' => 0,
16875 
              'is_floating_block' => 1,
16876 
              'must_be_hdl_vector' => 1,
16877 
              'period' => 1,
16878 
              'port_id' => 0,
16879 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/dout',
16880 
              'type' => 'UFix_32_0',
16881 
            },
16882 
            'direction' => 'out',
16883 
            'hdlType' => 'std_logic_vector(31 downto 0)',
16884 
            'width' => 32,
16885 
          },
16886 
          'en' => {
16887 
            'attributes' => {
16888 
              'bin_pt' => 0,
16889 
              'is_floating_block' => 1,
16890 
              'must_be_hdl_vector' => 1,
16891 
              'period' => 1,
16892 
              'port_id' => 1,
16893 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/en',
16894 
              'type' => 'Bool',
16895 
            },
16896 
            'direction' => 'in',
16897 
            'hdlType' => 'std_logic_vector(0 downto 0)',
16898 
            'width' => 1,
16899 
          },
16900 
        },
16901 
      },
16902 
      'entityName' => 'x_x15',
16903 
    },
16904 
    'to_register25' => {
16905 
      'connections' => {
16906 
        'ce' => 'sysgen_dut.to_register25_ce',
16907 
        'clk' => 'sysgen_dut.to_register25_clk',
16908 
        'clr' => 'sysgen_dut.to_register25_clr',
16909 
        'data_in' => 'sysgen_dut.to_register25_data_in',
16910 
        'dout' => 'to_register25.dout',
16911 
        'en' => 'sysgen_dut.to_register25_en',
16912 
      },
16913 
      'entity' => {
16914 
        'attributes' => {
16915 
          'entityAlreadyNetlisted' => 1,
16916 
          'generics' => [
16917 
          ],
16918 
          'is_floating_block' => 1,
16919 
          'mask' => {
16920 
            'Block_Handle' => 2135.00048828125,
16921 
            'Block_handle' => 2135.00048828125,
16922 
            'MDL_Handle' => 2083.00048828125,
16923 
            'MDL_handle' => 2083.00048828125,
16924 
            'arith_type' => 1,
16925 
            'bin_pt' => 14,
16926 
            'block_config' => 'sysgen_blockset:toreg_config',
16927 
            'block_handle' => 2135.00048828125,
16928 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25',
16929 
            'block_type' => 'toreg',
16930 
            'dbl_ovrd' => 0,
16931 
            'explicit_data_type' => 0,
16932 
            'gui_display_data_type' => 1,
16933 
            'init' => 0,
16934 
            'init_bit_vector' => '\'b0',
16935 
            'mdl_handle' => 2083.00048828125,
16936 
            'model_handle' => 2083.00048828125,
16937 
            'n_bits' => 16,
16938 
            'ownership' => 1,
16939 
            'preci_type' => 1,
16940 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
16941 
            'shared_memory_name' => 'register08tv',
16942 
          },
16943 
          'needs_vhdl_wrapper' => 0,
16944 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25',
16945 
        },
16946 
        'entityName' => 'x_x16',
16947 
        'ports' => {
16948 
          'ce' => {
16949 
            'attributes' => {
16950 
              'domain' => '',
16951 
              'group' => 1,
16952 
              'isCe' => 1,
16953 
              'is_floating_block' => 1,
16954 
              'period' => 1,
16955 
              'type' => 'logic',
16956 
            },
16957 
            'direction' => 'in',
16958 
            'hdlType' => 'std_logic',
16959 
            'width' => 1,
16960 
          },
16961 
          'clk' => {
16962 
            'attributes' => {
16963 
              'domain' => '',
16964 
              'group' => 1,
16965 
              'isClk' => 1,
16966 
              'is_floating_block' => 1,
16967 
              'period' => 1,
16968 
              'type' => 'logic',
16969 
            },
16970 
            'direction' => 'in',
16971 
            'hdlType' => 'std_logic',
16972 
            'width' => 1,
16973 
          },
16974 
          'clr' => {
16975 
            'attributes' => {
16976 
              'domain' => '',
16977 
              'group' => 1,
16978 
              'isClr' => 1,
16979 
              'is_floating_block' => 1,
16980 
              'period' => 1,
16981 
              'type' => 'logic',
16982 
              'valid_bit_used' => 0,
16983 
            },
16984 
            'direction' => 'in',
16985 
            'hdlType' => 'std_logic',
16986 
            'width' => 1,
16987 
          },
16988 
          'data_in' => {
16989 
            'attributes' => {
16990 
              'bin_pt' => 0,
16991 
              'is_floating_block' => 1,
16992 
              'must_be_hdl_vector' => 1,
16993 
              'period' => 1,
16994 
              'port_id' => 0,
16995 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/data_in',
16996 
              'type' => 'Bool',
16997 
            },
16998 
            'direction' => 'in',
16999 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17000 
            'width' => 1,
17001 
          },
17002 
          'dout' => {
17003 
            'attributes' => {
17004 
              'bin_pt' => 0,
17005 
              'is_floating_block' => 1,
17006 
              'must_be_hdl_vector' => 1,
17007 
              'period' => 1,
17008 
              'port_id' => 0,
17009 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/dout',
17010 
              'type' => 'Bool',
17011 
            },
17012 
            'direction' => 'out',
17013 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17014 
            'width' => 1,
17015 
          },
17016 
          'en' => {
17017 
            'attributes' => {
17018 
              'bin_pt' => 0,
17019 
              'is_floating_block' => 1,
17020 
              'must_be_hdl_vector' => 1,
17021 
              'period' => 1,
17022 
              'port_id' => 1,
17023 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register25/en',
17024 
              'type' => 'Bool',
17025 
            },
17026 
            'direction' => 'in',
17027 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17028 
            'width' => 1,
17029 
          },
17030 
        },
17031 
      },
17032 
      'entityName' => 'x_x16',
17033 
    },
17034 
    'to_register26' => {
17035 
      'connections' => {
17036 
        'ce' => 'sysgen_dut.to_register26_ce',
17037 
        'clk' => 'sysgen_dut.to_register26_clk',
17038 
        'clr' => 'sysgen_dut.to_register26_clr',
17039 
        'data_in' => 'sysgen_dut.to_register26_data_in',
17040 
        'dout' => 'to_register26.dout',
17041 
        'en' => 'sysgen_dut.to_register26_en',
17042 
      },
17043 
      'entity' => {
17044 
        'attributes' => {
17045 
          'entityAlreadyNetlisted' => 1,
17046 
          'generics' => [
17047 
          ],
17048 
          'is_floating_block' => 1,
17049 
          'mask' => {
17050 
            'Block_Handle' => 2136.00048828125,
17051 
            'Block_handle' => 2136.00048828125,
17052 
            'MDL_Handle' => 2083.00048828125,
17053 
            'MDL_handle' => 2083.00048828125,
17054 
            'arith_type' => 1,
17055 
            'bin_pt' => 14,
17056 
            'block_config' => 'sysgen_blockset:toreg_config',
17057 
            'block_handle' => 2136.00048828125,
17058 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26',
17059 
            'block_type' => 'toreg',
17060 
            'dbl_ovrd' => 0,
17061 
            'explicit_data_type' => 0,
17062 
            'gui_display_data_type' => 1,
17063 
            'init' => 0,
17064 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
17065 
            'mdl_handle' => 2083.00048828125,
17066 
            'model_handle' => 2083.00048828125,
17067 
            'n_bits' => 16,
17068 
            'ownership' => 1,
17069 
            'preci_type' => 1,
17070 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17071 
            'shared_memory_name' => 'register08td',
17072 
          },
17073 
          'needs_vhdl_wrapper' => 0,
17074 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26',
17075 
        },
17076 
        'entityName' => 'x_x17',
17077 
        'ports' => {
17078 
          'ce' => {
17079 
            'attributes' => {
17080 
              'domain' => '',
17081 
              'group' => 1,
17082 
              'isCe' => 1,
17083 
              'is_floating_block' => 1,
17084 
              'period' => 1,
17085 
              'type' => 'logic',
17086 
            },
17087 
            'direction' => 'in',
17088 
            'hdlType' => 'std_logic',
17089 
            'width' => 1,
17090 
          },
17091 
          'clk' => {
17092 
            'attributes' => {
17093 
              'domain' => '',
17094 
              'group' => 1,
17095 
              'isClk' => 1,
17096 
              'is_floating_block' => 1,
17097 
              'period' => 1,
17098 
              'type' => 'logic',
17099 
            },
17100 
            'direction' => 'in',
17101 
            'hdlType' => 'std_logic',
17102 
            'width' => 1,
17103 
          },
17104 
          'clr' => {
17105 
            'attributes' => {
17106 
              'domain' => '',
17107 
              'group' => 1,
17108 
              'isClr' => 1,
17109 
              'is_floating_block' => 1,
17110 
              'period' => 1,
17111 
              'type' => 'logic',
17112 
              'valid_bit_used' => 0,
17113 
            },
17114 
            'direction' => 'in',
17115 
            'hdlType' => 'std_logic',
17116 
            'width' => 1,
17117 
          },
17118 
          'data_in' => {
17119 
            'attributes' => {
17120 
              'bin_pt' => 0,
17121 
              'is_floating_block' => 1,
17122 
              'must_be_hdl_vector' => 1,
17123 
              'period' => 1,
17124 
              'port_id' => 0,
17125 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/data_in',
17126 
              'type' => 'UFix_32_0',
17127 
            },
17128 
            'direction' => 'in',
17129 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17130 
            'width' => 32,
17131 
          },
17132 
          'dout' => {
17133 
            'attributes' => {
17134 
              'bin_pt' => 0,
17135 
              'is_floating_block' => 1,
17136 
              'must_be_hdl_vector' => 1,
17137 
              'period' => 1,
17138 
              'port_id' => 0,
17139 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/dout',
17140 
              'type' => 'UFix_32_0',
17141 
            },
17142 
            'direction' => 'out',
17143 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17144 
            'width' => 32,
17145 
          },
17146 
          'en' => {
17147 
            'attributes' => {
17148 
              'bin_pt' => 0,
17149 
              'is_floating_block' => 1,
17150 
              'must_be_hdl_vector' => 1,
17151 
              'period' => 1,
17152 
              'port_id' => 1,
17153 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/en',
17154 
              'type' => 'Bool',
17155 
            },
17156 
            'direction' => 'in',
17157 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17158 
            'width' => 1,
17159 
          },
17160 
        },
17161 
      },
17162 
      'entityName' => 'x_x17',
17163 
    },
17164 
    'to_register27' => {
17165 
      'connections' => {
17166 
        'ce' => 'sysgen_dut.to_register27_ce',
17167 
        'clk' => 'sysgen_dut.to_register27_clk',
17168 
        'clr' => 'sysgen_dut.to_register27_clr',
17169 
        'data_in' => 'sysgen_dut.to_register27_data_in',
17170 
        'dout' => 'to_register27.dout',
17171 
        'en' => 'sysgen_dut.to_register27_en',
17172 
      },
17173 
      'entity' => {
17174 
        'attributes' => {
17175 
          'entityAlreadyNetlisted' => 1,
17176 
          'generics' => [
17177 
          ],
17178 
          'is_floating_block' => 1,
17179 
          'mask' => {
17180 
            'Block_Handle' => 2137.00048828125,
17181 
            'Block_handle' => 2137.00048828125,
17182 
            'MDL_Handle' => 2083.00048828125,
17183 
            'MDL_handle' => 2083.00048828125,
17184 
            'arith_type' => 1,
17185 
            'bin_pt' => 14,
17186 
            'block_config' => 'sysgen_blockset:toreg_config',
17187 
            'block_handle' => 2137.00048828125,
17188 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27',
17189 
            'block_type' => 'toreg',
17190 
            'dbl_ovrd' => 0,
17191 
            'explicit_data_type' => 0,
17192 
            'gui_display_data_type' => 1,
17193 
            'init' => 0,
17194 
            'init_bit_vector' => '\'b0',
17195 
            'mdl_handle' => 2083.00048828125,
17196 
            'model_handle' => 2083.00048828125,
17197 
            'n_bits' => 16,
17198 
            'ownership' => 1,
17199 
            'preci_type' => 1,
17200 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17201 
            'shared_memory_name' => 'register11tv',
17202 
          },
17203 
          'needs_vhdl_wrapper' => 0,
17204 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27',
17205 
        },
17206 
        'entityName' => 'x_x18',
17207 
        'ports' => {
17208 
          'ce' => {
17209 
            'attributes' => {
17210 
              'domain' => '',
17211 
              'group' => 1,
17212 
              'isCe' => 1,
17213 
              'is_floating_block' => 1,
17214 
              'period' => 1,
17215 
              'type' => 'logic',
17216 
            },
17217 
            'direction' => 'in',
17218 
            'hdlType' => 'std_logic',
17219 
            'width' => 1,
17220 
          },
17221 
          'clk' => {
17222 
            'attributes' => {
17223 
              'domain' => '',
17224 
              'group' => 1,
17225 
              'isClk' => 1,
17226 
              'is_floating_block' => 1,
17227 
              'period' => 1,
17228 
              'type' => 'logic',
17229 
            },
17230 
            'direction' => 'in',
17231 
            'hdlType' => 'std_logic',
17232 
            'width' => 1,
17233 
          },
17234 
          'clr' => {
17235 
            'attributes' => {
17236 
              'domain' => '',
17237 
              'group' => 1,
17238 
              'isClr' => 1,
17239 
              'is_floating_block' => 1,
17240 
              'period' => 1,
17241 
              'type' => 'logic',
17242 
              'valid_bit_used' => 0,
17243 
            },
17244 
            'direction' => 'in',
17245 
            'hdlType' => 'std_logic',
17246 
            'width' => 1,
17247 
          },
17248 
          'data_in' => {
17249 
            'attributes' => {
17250 
              'bin_pt' => 0,
17251 
              'is_floating_block' => 1,
17252 
              'must_be_hdl_vector' => 1,
17253 
              'period' => 1,
17254 
              'port_id' => 0,
17255 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/data_in',
17256 
              'type' => 'Bool',
17257 
            },
17258 
            'direction' => 'in',
17259 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17260 
            'width' => 1,
17261 
          },
17262 
          'dout' => {
17263 
            'attributes' => {
17264 
              'bin_pt' => 0,
17265 
              'is_floating_block' => 1,
17266 
              'must_be_hdl_vector' => 1,
17267 
              'period' => 1,
17268 
              'port_id' => 0,
17269 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
17270 
              'type' => 'Bool',
17271 
            },
17272 
            'direction' => 'out',
17273 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17274 
            'width' => 1,
17275 
          },
17276 
          'en' => {
17277 
            'attributes' => {
17278 
              'bin_pt' => 0,
17279 
              'is_floating_block' => 1,
17280 
              'must_be_hdl_vector' => 1,
17281 
              'period' => 1,
17282 
              'port_id' => 1,
17283 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/en',
17284 
              'type' => 'Bool',
17285 
            },
17286 
            'direction' => 'in',
17287 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17288 
            'width' => 1,
17289 
          },
17290 
        },
17291 
      },
17292 
      'entityName' => 'x_x18',
17293 
    },
17294 
    'to_register28' => {
17295 
      'connections' => {
17296 
        'ce' => 'sysgen_dut.to_register28_ce',
17297 
        'clk' => 'sysgen_dut.to_register28_clk',
17298 
        'clr' => 'sysgen_dut.to_register28_clr',
17299 
        'data_in' => 'sysgen_dut.to_register28_data_in',
17300 
        'dout' => 'to_register28.dout',
17301 
        'en' => 'sysgen_dut.to_register28_en',
17302 
      },
17303 
      'entity' => {
17304 
        'attributes' => {
17305 
          'entityAlreadyNetlisted' => 1,
17306 
          'generics' => [
17307 
          ],
17308 
          'is_floating_block' => 1,
17309 
          'mask' => {
17310 
            'Block_Handle' => 2138.00048828125,
17311 
            'Block_handle' => 2138.00048828125,
17312 
            'MDL_Handle' => 2083.00048828125,
17313 
            'MDL_handle' => 2083.00048828125,
17314 
            'arith_type' => 1,
17315 
            'bin_pt' => 14,
17316 
            'block_config' => 'sysgen_blockset:toreg_config',
17317 
            'block_handle' => 2138.00048828125,
17318 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28',
17319 
            'block_type' => 'toreg',
17320 
            'dbl_ovrd' => 0,
17321 
            'explicit_data_type' => 0,
17322 
            'gui_display_data_type' => 1,
17323 
            'init' => 0,
17324 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
17325 
            'mdl_handle' => 2083.00048828125,
17326 
            'model_handle' => 2083.00048828125,
17327 
            'n_bits' => 16,
17328 
            'ownership' => 1,
17329 
            'preci_type' => 1,
17330 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17331 
            'shared_memory_name' => 'register11td',
17332 
          },
17333 
          'needs_vhdl_wrapper' => 0,
17334 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28',
17335 
        },
17336 
        'entityName' => 'x_x19',
17337 
        'ports' => {
17338 
          'ce' => {
17339 
            'attributes' => {
17340 
              'domain' => '',
17341 
              'group' => 1,
17342 
              'isCe' => 1,
17343 
              'is_floating_block' => 1,
17344 
              'period' => 1,
17345 
              'type' => 'logic',
17346 
            },
17347 
            'direction' => 'in',
17348 
            'hdlType' => 'std_logic',
17349 
            'width' => 1,
17350 
          },
17351 
          'clk' => {
17352 
            'attributes' => {
17353 
              'domain' => '',
17354 
              'group' => 1,
17355 
              'isClk' => 1,
17356 
              'is_floating_block' => 1,
17357 
              'period' => 1,
17358 
              'type' => 'logic',
17359 
            },
17360 
            'direction' => 'in',
17361 
            'hdlType' => 'std_logic',
17362 
            'width' => 1,
17363 
          },
17364 
          'clr' => {
17365 
            'attributes' => {
17366 
              'domain' => '',
17367 
              'group' => 1,
17368 
              'isClr' => 1,
17369 
              'is_floating_block' => 1,
17370 
              'period' => 1,
17371 
              'type' => 'logic',
17372 
              'valid_bit_used' => 0,
17373 
            },
17374 
            'direction' => 'in',
17375 
            'hdlType' => 'std_logic',
17376 
            'width' => 1,
17377 
          },
17378 
          'data_in' => {
17379 
            'attributes' => {
17380 
              'bin_pt' => 0,
17381 
              'is_floating_block' => 1,
17382 
              'must_be_hdl_vector' => 1,
17383 
              'period' => 1,
17384 
              'port_id' => 0,
17385 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/data_in',
17386 
              'type' => 'UFix_32_0',
17387 
            },
17388 
            'direction' => 'in',
17389 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17390 
            'width' => 32,
17391 
          },
17392 
          'dout' => {
17393 
            'attributes' => {
17394 
              'bin_pt' => 0,
17395 
              'is_floating_block' => 1,
17396 
              'must_be_hdl_vector' => 1,
17397 
              'period' => 1,
17398 
              'port_id' => 0,
17399 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/dout',
17400 
              'type' => 'UFix_32_0',
17401 
            },
17402 
            'direction' => 'out',
17403 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17404 
            'width' => 32,
17405 
          },
17406 
          'en' => {
17407 
            'attributes' => {
17408 
              'bin_pt' => 0,
17409 
              'is_floating_block' => 1,
17410 
              'must_be_hdl_vector' => 1,
17411 
              'period' => 1,
17412 
              'port_id' => 1,
17413 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register28/en',
17414 
              'type' => 'Bool',
17415 
            },
17416 
            'direction' => 'in',
17417 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17418 
            'width' => 1,
17419 
          },
17420 
        },
17421 
      },
17422 
      'entityName' => 'x_x19',
17423 
    },
17424 
    'to_register29' => {
17425 
      'connections' => {
17426 
        'ce' => 'sysgen_dut.to_register29_ce',
17427 
        'clk' => 'sysgen_dut.to_register29_clk',
17428 
        'clr' => 'sysgen_dut.to_register29_clr',
17429 
        'data_in' => 'sysgen_dut.to_register29_data_in',
17430 
        'dout' => 'to_register29.dout',
17431 
        'en' => 'sysgen_dut.to_register29_en',
17432 
      },
17433 
      'entity' => {
17434 
        'attributes' => {
17435 
          'entityAlreadyNetlisted' => 1,
17436 
          'generics' => [
17437 
          ],
17438 
          'is_floating_block' => 1,
17439 
          'mask' => {
17440 
            'Block_Handle' => 2139.00048828125,
17441 
            'Block_handle' => 2139.00048828125,
17442 
            'MDL_Handle' => 2083.00048828125,
17443 
            'MDL_handle' => 2083.00048828125,
17444 
            'arith_type' => 1,
17445 
            'bin_pt' => 14,
17446 
            'block_config' => 'sysgen_blockset:toreg_config',
17447 
            'block_handle' => 2139.00048828125,
17448 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29',
17449 
            'block_type' => 'toreg',
17450 
            'dbl_ovrd' => 0,
17451 
            'explicit_data_type' => 0,
17452 
            'gui_display_data_type' => 1,
17453 
            'init' => 0,
17454 
            'init_bit_vector' => '\'b0',
17455 
            'mdl_handle' => 2083.00048828125,
17456 
            'model_handle' => 2083.00048828125,
17457 
            'n_bits' => 16,
17458 
            'ownership' => 1,
17459 
            'preci_type' => 1,
17460 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17461 
            'shared_memory_name' => 'register12tv',
17462 
          },
17463 
          'needs_vhdl_wrapper' => 0,
17464 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29',
17465 
        },
17466 
        'entityName' => 'x_x20',
17467 
        'ports' => {
17468 
          'ce' => {
17469 
            'attributes' => {
17470 
              'domain' => '',
17471 
              'group' => 1,
17472 
              'isCe' => 1,
17473 
              'is_floating_block' => 1,
17474 
              'period' => 1,
17475 
              'type' => 'logic',
17476 
            },
17477 
            'direction' => 'in',
17478 
            'hdlType' => 'std_logic',
17479 
            'width' => 1,
17480 
          },
17481 
          'clk' => {
17482 
            'attributes' => {
17483 
              'domain' => '',
17484 
              'group' => 1,
17485 
              'isClk' => 1,
17486 
              'is_floating_block' => 1,
17487 
              'period' => 1,
17488 
              'type' => 'logic',
17489 
            },
17490 
            'direction' => 'in',
17491 
            'hdlType' => 'std_logic',
17492 
            'width' => 1,
17493 
          },
17494 
          'clr' => {
17495 
            'attributes' => {
17496 
              'domain' => '',
17497 
              'group' => 1,
17498 
              'isClr' => 1,
17499 
              'is_floating_block' => 1,
17500 
              'period' => 1,
17501 
              'type' => 'logic',
17502 
              'valid_bit_used' => 0,
17503 
            },
17504 
            'direction' => 'in',
17505 
            'hdlType' => 'std_logic',
17506 
            'width' => 1,
17507 
          },
17508 
          'data_in' => {
17509 
            'attributes' => {
17510 
              'bin_pt' => 0,
17511 
              'is_floating_block' => 1,
17512 
              'must_be_hdl_vector' => 1,
17513 
              'period' => 1,
17514 
              'port_id' => 0,
17515 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/data_in',
17516 
              'type' => 'Bool',
17517 
            },
17518 
            'direction' => 'in',
17519 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17520 
            'width' => 1,
17521 
          },
17522 
          'dout' => {
17523 
            'attributes' => {
17524 
              'bin_pt' => 0,
17525 
              'is_floating_block' => 1,
17526 
              'must_be_hdl_vector' => 1,
17527 
              'period' => 1,
17528 
              'port_id' => 0,
17529 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/dout',
17530 
              'type' => 'Bool',
17531 
            },
17532 
            'direction' => 'out',
17533 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17534 
            'width' => 1,
17535 
          },
17536 
          'en' => {
17537 
            'attributes' => {
17538 
              'bin_pt' => 0,
17539 
              'is_floating_block' => 1,
17540 
              'must_be_hdl_vector' => 1,
17541 
              'period' => 1,
17542 
              'port_id' => 1,
17543 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register29/en',
17544 
              'type' => 'Bool',
17545 
            },
17546 
            'direction' => 'in',
17547 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17548 
            'width' => 1,
17549 
          },
17550 
        },
17551 
      },
17552 
      'entityName' => 'x_x20',
17553 
    },
17554 
    'to_register3' => {
17555 
      'connections' => {
17556 
        'ce' => 'sysgen_dut.to_register3_ce',
17557 
        'clk' => 'sysgen_dut.to_register3_clk',
17558 
        'clr' => 'sysgen_dut.to_register3_clr',
17559 
        'data_in' => 'sysgen_dut.to_register3_data_in',
17560 
        'dout' => 'to_register3.dout',
17561 
        'en' => 'sysgen_dut.to_register3_en',
17562 
      },
17563 
      'entity' => {
17564 
        'attributes' => {
17565 
          'entityAlreadyNetlisted' => 1,
17566 
          'generics' => [
17567 
          ],
17568 
          'is_floating_block' => 1,
17569 
          'mask' => {
17570 
            'Block_Handle' => 2140.00048828125,
17571 
            'Block_handle' => 2140.00048828125,
17572 
            'MDL_Handle' => 2083.00048828125,
17573 
            'MDL_handle' => 2083.00048828125,
17574 
            'arith_type' => 1,
17575 
            'bin_pt' => 14,
17576 
            'block_config' => 'sysgen_blockset:toreg_config',
17577 
            'block_handle' => 2140.00048828125,
17578 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3',
17579 
            'block_type' => 'toreg',
17580 
            'dbl_ovrd' => 0,
17581 
            'explicit_data_type' => 0,
17582 
            'gui_display_data_type' => 1,
17583 
            'init' => 0,
17584 
            'init_bit_vector' => '\'b0',
17585 
            'mdl_handle' => 2083.00048828125,
17586 
            'model_handle' => 2083.00048828125,
17587 
            'n_bits' => 16,
17588 
            'ownership' => 1,
17589 
            'preci_type' => 1,
17590 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17591 
            'shared_memory_name' => 'register01tv',
17592 
          },
17593 
          'needs_vhdl_wrapper' => 0,
17594 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3',
17595 
        },
17596 
        'entityName' => 'x_x21',
17597 
        'ports' => {
17598 
          'ce' => {
17599 
            'attributes' => {
17600 
              'domain' => '',
17601 
              'group' => 1,
17602 
              'isCe' => 1,
17603 
              'is_floating_block' => 1,
17604 
              'period' => 1,
17605 
              'type' => 'logic',
17606 
            },
17607 
            'direction' => 'in',
17608 
            'hdlType' => 'std_logic',
17609 
            'width' => 1,
17610 
          },
17611 
          'clk' => {
17612 
            'attributes' => {
17613 
              'domain' => '',
17614 
              'group' => 1,
17615 
              'isClk' => 1,
17616 
              'is_floating_block' => 1,
17617 
              'period' => 1,
17618 
              'type' => 'logic',
17619 
            },
17620 
            'direction' => 'in',
17621 
            'hdlType' => 'std_logic',
17622 
            'width' => 1,
17623 
          },
17624 
          'clr' => {
17625 
            'attributes' => {
17626 
              'domain' => '',
17627 
              'group' => 1,
17628 
              'isClr' => 1,
17629 
              'is_floating_block' => 1,
17630 
              'period' => 1,
17631 
              'type' => 'logic',
17632 
              'valid_bit_used' => 0,
17633 
            },
17634 
            'direction' => 'in',
17635 
            'hdlType' => 'std_logic',
17636 
            'width' => 1,
17637 
          },
17638 
          'data_in' => {
17639 
            'attributes' => {
17640 
              'bin_pt' => 0,
17641 
              'is_floating_block' => 1,
17642 
              'must_be_hdl_vector' => 1,
17643 
              'period' => 1,
17644 
              'port_id' => 0,
17645 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/data_in',
17646 
              'type' => 'Bool',
17647 
            },
17648 
            'direction' => 'in',
17649 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17650 
            'width' => 1,
17651 
          },
17652 
          'dout' => {
17653 
            'attributes' => {
17654 
              'bin_pt' => 0,
17655 
              'is_floating_block' => 1,
17656 
              'must_be_hdl_vector' => 1,
17657 
              'period' => 1,
17658 
              'port_id' => 0,
17659 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
17660 
              'type' => 'Bool',
17661 
            },
17662 
            'direction' => 'out',
17663 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17664 
            'width' => 1,
17665 
          },
17666 
          'en' => {
17667 
            'attributes' => {
17668 
              'bin_pt' => 0,
17669 
              'is_floating_block' => 1,
17670 
              'must_be_hdl_vector' => 1,
17671 
              'period' => 1,
17672 
              'port_id' => 1,
17673 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/en',
17674 
              'type' => 'Bool',
17675 
            },
17676 
            'direction' => 'in',
17677 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17678 
            'width' => 1,
17679 
          },
17680 
        },
17681 
      },
17682 
      'entityName' => 'x_x21',
17683 
    },
17684 
    'to_register30' => {
17685 
      'connections' => {
17686 
        'ce' => 'sysgen_dut.to_register30_ce',
17687 
        'clk' => 'sysgen_dut.to_register30_clk',
17688 
        'clr' => 'sysgen_dut.to_register30_clr',
17689 
        'data_in' => 'sysgen_dut.to_register30_data_in',
17690 
        'dout' => 'to_register30.dout',
17691 
        'en' => 'sysgen_dut.to_register30_en',
17692 
      },
17693 
      'entity' => {
17694 
        'attributes' => {
17695 
          'entityAlreadyNetlisted' => 1,
17696 
          'generics' => [
17697 
          ],
17698 
          'is_floating_block' => 1,
17699 
          'mask' => {
17700 
            'Block_Handle' => 2141.00048828125,
17701 
            'Block_handle' => 2141.00048828125,
17702 
            'MDL_Handle' => 2083.00048828125,
17703 
            'MDL_handle' => 2083.00048828125,
17704 
            'arith_type' => 1,
17705 
            'bin_pt' => 14,
17706 
            'block_config' => 'sysgen_blockset:toreg_config',
17707 
            'block_handle' => 2141.00048828125,
17708 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30',
17709 
            'block_type' => 'toreg',
17710 
            'dbl_ovrd' => 0,
17711 
            'explicit_data_type' => 0,
17712 
            'gui_display_data_type' => 1,
17713 
            'init' => 0,
17714 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
17715 
            'mdl_handle' => 2083.00048828125,
17716 
            'model_handle' => 2083.00048828125,
17717 
            'n_bits' => 16,
17718 
            'ownership' => 1,
17719 
            'preci_type' => 1,
17720 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17721 
            'shared_memory_name' => 'register12td',
17722 
          },
17723 
          'needs_vhdl_wrapper' => 0,
17724 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30',
17725 
        },
17726 
        'entityName' => 'x_x22',
17727 
        'ports' => {
17728 
          'ce' => {
17729 
            'attributes' => {
17730 
              'domain' => '',
17731 
              'group' => 1,
17732 
              'isCe' => 1,
17733 
              'is_floating_block' => 1,
17734 
              'period' => 1,
17735 
              'type' => 'logic',
17736 
            },
17737 
            'direction' => 'in',
17738 
            'hdlType' => 'std_logic',
17739 
            'width' => 1,
17740 
          },
17741 
          'clk' => {
17742 
            'attributes' => {
17743 
              'domain' => '',
17744 
              'group' => 1,
17745 
              'isClk' => 1,
17746 
              'is_floating_block' => 1,
17747 
              'period' => 1,
17748 
              'type' => 'logic',
17749 
            },
17750 
            'direction' => 'in',
17751 
            'hdlType' => 'std_logic',
17752 
            'width' => 1,
17753 
          },
17754 
          'clr' => {
17755 
            'attributes' => {
17756 
              'domain' => '',
17757 
              'group' => 1,
17758 
              'isClr' => 1,
17759 
              'is_floating_block' => 1,
17760 
              'period' => 1,
17761 
              'type' => 'logic',
17762 
              'valid_bit_used' => 0,
17763 
            },
17764 
            'direction' => 'in',
17765 
            'hdlType' => 'std_logic',
17766 
            'width' => 1,
17767 
          },
17768 
          'data_in' => {
17769 
            'attributes' => {
17770 
              'bin_pt' => 0,
17771 
              'is_floating_block' => 1,
17772 
              'must_be_hdl_vector' => 1,
17773 
              'period' => 1,
17774 
              'port_id' => 0,
17775 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/data_in',
17776 
              'type' => 'UFix_32_0',
17777 
            },
17778 
            'direction' => 'in',
17779 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17780 
            'width' => 32,
17781 
          },
17782 
          'dout' => {
17783 
            'attributes' => {
17784 
              'bin_pt' => 0,
17785 
              'is_floating_block' => 1,
17786 
              'must_be_hdl_vector' => 1,
17787 
              'period' => 1,
17788 
              'port_id' => 0,
17789 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/dout',
17790 
              'type' => 'UFix_32_0',
17791 
            },
17792 
            'direction' => 'out',
17793 
            'hdlType' => 'std_logic_vector(31 downto 0)',
17794 
            'width' => 32,
17795 
          },
17796 
          'en' => {
17797 
            'attributes' => {
17798 
              'bin_pt' => 0,
17799 
              'is_floating_block' => 1,
17800 
              'must_be_hdl_vector' => 1,
17801 
              'period' => 1,
17802 
              'port_id' => 1,
17803 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register30/en',
17804 
              'type' => 'Bool',
17805 
            },
17806 
            'direction' => 'in',
17807 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17808 
            'width' => 1,
17809 
          },
17810 
        },
17811 
      },
17812 
      'entityName' => 'x_x22',
17813 
    },
17814 
    'to_register31' => {
17815 
      'connections' => {
17816 
        'ce' => 'sysgen_dut.to_register31_ce',
17817 
        'clk' => 'sysgen_dut.to_register31_clk',
17818 
        'clr' => 'sysgen_dut.to_register31_clr',
17819 
        'data_in' => 'sysgen_dut.to_register31_data_in',
17820 
        'dout' => 'to_register31.dout',
17821 
        'en' => 'sysgen_dut.to_register31_en',
17822 
      },
17823 
      'entity' => {
17824 
        'attributes' => {
17825 
          'entityAlreadyNetlisted' => 1,
17826 
          'generics' => [
17827 
          ],
17828 
          'is_floating_block' => 1,
17829 
          'mask' => {
17830 
            'Block_Handle' => 2142.00048828125,
17831 
            'Block_handle' => 2142.00048828125,
17832 
            'MDL_Handle' => 2083.00048828125,
17833 
            'MDL_handle' => 2083.00048828125,
17834 
            'arith_type' => 1,
17835 
            'bin_pt' => 14,
17836 
            'block_config' => 'sysgen_blockset:toreg_config',
17837 
            'block_handle' => 2142.00048828125,
17838 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31',
17839 
            'block_type' => 'toreg',
17840 
            'dbl_ovrd' => 0,
17841 
            'explicit_data_type' => 0,
17842 
            'gui_display_data_type' => 1,
17843 
            'init' => 0,
17844 
            'init_bit_vector' => '\'b0',
17845 
            'mdl_handle' => 2083.00048828125,
17846 
            'model_handle' => 2083.00048828125,
17847 
            'n_bits' => 16,
17848 
            'ownership' => 1,
17849 
            'preci_type' => 1,
17850 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17851 
            'shared_memory_name' => 'register13tv',
17852 
          },
17853 
          'needs_vhdl_wrapper' => 0,
17854 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31',
17855 
        },
17856 
        'entityName' => 'x_x23',
17857 
        'ports' => {
17858 
          'ce' => {
17859 
            'attributes' => {
17860 
              'domain' => '',
17861 
              'group' => 1,
17862 
              'isCe' => 1,
17863 
              'is_floating_block' => 1,
17864 
              'period' => 1,
17865 
              'type' => 'logic',
17866 
            },
17867 
            'direction' => 'in',
17868 
            'hdlType' => 'std_logic',
17869 
            'width' => 1,
17870 
          },
17871 
          'clk' => {
17872 
            'attributes' => {
17873 
              'domain' => '',
17874 
              'group' => 1,
17875 
              'isClk' => 1,
17876 
              'is_floating_block' => 1,
17877 
              'period' => 1,
17878 
              'type' => 'logic',
17879 
            },
17880 
            'direction' => 'in',
17881 
            'hdlType' => 'std_logic',
17882 
            'width' => 1,
17883 
          },
17884 
          'clr' => {
17885 
            'attributes' => {
17886 
              'domain' => '',
17887 
              'group' => 1,
17888 
              'isClr' => 1,
17889 
              'is_floating_block' => 1,
17890 
              'period' => 1,
17891 
              'type' => 'logic',
17892 
              'valid_bit_used' => 0,
17893 
            },
17894 
            'direction' => 'in',
17895 
            'hdlType' => 'std_logic',
17896 
            'width' => 1,
17897 
          },
17898 
          'data_in' => {
17899 
            'attributes' => {
17900 
              'bin_pt' => 0,
17901 
              'is_floating_block' => 1,
17902 
              'must_be_hdl_vector' => 1,
17903 
              'period' => 1,
17904 
              'port_id' => 0,
17905 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/data_in',
17906 
              'type' => 'Bool',
17907 
            },
17908 
            'direction' => 'in',
17909 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17910 
            'width' => 1,
17911 
          },
17912 
          'dout' => {
17913 
            'attributes' => {
17914 
              'bin_pt' => 0,
17915 
              'is_floating_block' => 1,
17916 
              'must_be_hdl_vector' => 1,
17917 
              'period' => 1,
17918 
              'port_id' => 0,
17919 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/dout',
17920 
              'type' => 'Bool',
17921 
            },
17922 
            'direction' => 'out',
17923 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17924 
            'width' => 1,
17925 
          },
17926 
          'en' => {
17927 
            'attributes' => {
17928 
              'bin_pt' => 0,
17929 
              'is_floating_block' => 1,
17930 
              'must_be_hdl_vector' => 1,
17931 
              'period' => 1,
17932 
              'port_id' => 1,
17933 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register31/en',
17934 
              'type' => 'Bool',
17935 
            },
17936 
            'direction' => 'in',
17937 
            'hdlType' => 'std_logic_vector(0 downto 0)',
17938 
            'width' => 1,
17939 
          },
17940 
        },
17941 
      },
17942 
      'entityName' => 'x_x23',
17943 
    },
17944 
    'to_register32' => {
17945 
      'connections' => {
17946 
        'ce' => 'sysgen_dut.to_register32_ce',
17947 
        'clk' => 'sysgen_dut.to_register32_clk',
17948 
        'clr' => 'sysgen_dut.to_register32_clr',
17949 
        'data_in' => 'sysgen_dut.to_register32_data_in',
17950 
        'dout' => 'to_register32.dout',
17951 
        'en' => 'sysgen_dut.to_register32_en',
17952 
      },
17953 
      'entity' => {
17954 
        'attributes' => {
17955 
          'entityAlreadyNetlisted' => 1,
17956 
          'generics' => [
17957 
          ],
17958 
          'is_floating_block' => 1,
17959 
          'mask' => {
17960 
            'Block_Handle' => 2143.00048828125,
17961 
            'Block_handle' => 2143.00048828125,
17962 
            'MDL_Handle' => 2083.00048828125,
17963 
            'MDL_handle' => 2083.00048828125,
17964 
            'arith_type' => 1,
17965 
            'bin_pt' => 14,
17966 
            'block_config' => 'sysgen_blockset:toreg_config',
17967 
            'block_handle' => 2143.00048828125,
17968 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32',
17969 
            'block_type' => 'toreg',
17970 
            'dbl_ovrd' => 0,
17971 
            'explicit_data_type' => 0,
17972 
            'gui_display_data_type' => 1,
17973 
            'init' => 0,
17974 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
17975 
            'mdl_handle' => 2083.00048828125,
17976 
            'model_handle' => 2083.00048828125,
17977 
            'n_bits' => 16,
17978 
            'ownership' => 1,
17979 
            'preci_type' => 1,
17980 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
17981 
            'shared_memory_name' => 'register13td',
17982 
          },
17983 
          'needs_vhdl_wrapper' => 0,
17984 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32',
17985 
        },
17986 
        'entityName' => 'x_x24',
17987 
        'ports' => {
17988 
          'ce' => {
17989 
            'attributes' => {
17990 
              'domain' => '',
17991 
              'group' => 1,
17992 
              'isCe' => 1,
17993 
              'is_floating_block' => 1,
17994 
              'period' => 1,
17995 
              'type' => 'logic',
17996 
            },
17997 
            'direction' => 'in',
17998 
            'hdlType' => 'std_logic',
17999 
            'width' => 1,
18000 
          },
18001 
          'clk' => {
18002 
            'attributes' => {
18003 
              'domain' => '',
18004 
              'group' => 1,
18005 
              'isClk' => 1,
18006 
              'is_floating_block' => 1,
18007 
              'period' => 1,
18008 
              'type' => 'logic',
18009 
            },
18010 
            'direction' => 'in',
18011 
            'hdlType' => 'std_logic',
18012 
            'width' => 1,
18013 
          },
18014 
          'clr' => {
18015 
            'attributes' => {
18016 
              'domain' => '',
18017 
              'group' => 1,
18018 
              'isClr' => 1,
18019 
              'is_floating_block' => 1,
18020 
              'period' => 1,
18021 
              'type' => 'logic',
18022 
              'valid_bit_used' => 0,
18023 
            },
18024 
            'direction' => 'in',
18025 
            'hdlType' => 'std_logic',
18026 
            'width' => 1,
18027 
          },
18028 
          'data_in' => {
18029 
            'attributes' => {
18030 
              'bin_pt' => 0,
18031 
              'is_floating_block' => 1,
18032 
              'must_be_hdl_vector' => 1,
18033 
              'period' => 1,
18034 
              'port_id' => 0,
18035 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/data_in',
18036 
              'type' => 'UFix_32_0',
18037 
            },
18038 
            'direction' => 'in',
18039 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18040 
            'width' => 32,
18041 
          },
18042 
          'dout' => {
18043 
            'attributes' => {
18044 
              'bin_pt' => 0,
18045 
              'is_floating_block' => 1,
18046 
              'must_be_hdl_vector' => 1,
18047 
              'period' => 1,
18048 
              'port_id' => 0,
18049 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/dout',
18050 
              'type' => 'UFix_32_0',
18051 
            },
18052 
            'direction' => 'out',
18053 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18054 
            'width' => 32,
18055 
          },
18056 
          'en' => {
18057 
            'attributes' => {
18058 
              'bin_pt' => 0,
18059 
              'is_floating_block' => 1,
18060 
              'must_be_hdl_vector' => 1,
18061 
              'period' => 1,
18062 
              'port_id' => 1,
18063 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register32/en',
18064 
              'type' => 'Bool',
18065 
            },
18066 
            'direction' => 'in',
18067 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18068 
            'width' => 1,
18069 
          },
18070 
        },
18071 
      },
18072 
      'entityName' => 'x_x24',
18073 
    },
18074 
    'to_register33' => {
18075 
      'connections' => {
18076 
        'ce' => 'sysgen_dut.to_register33_ce',
18077 
        'clk' => 'sysgen_dut.to_register33_clk',
18078 
        'clr' => 'sysgen_dut.to_register33_clr',
18079 
        'data_in' => 'sysgen_dut.to_register33_data_in',
18080 
        'dout' => 'to_register33.dout',
18081 
        'en' => 'sysgen_dut.to_register33_en',
18082 
      },
18083 
      'entity' => {
18084 
        'attributes' => {
18085 
          'entityAlreadyNetlisted' => 1,
18086 
          'generics' => [
18087 
          ],
18088 
          'is_floating_block' => 1,
18089 
          'mask' => {
18090 
            'Block_Handle' => 2144.00048828125,
18091 
            'Block_handle' => 2144.00048828125,
18092 
            'MDL_Handle' => 2083.00048828125,
18093 
            'MDL_handle' => 2083.00048828125,
18094 
            'arith_type' => 1,
18095 
            'bin_pt' => 14,
18096 
            'block_config' => 'sysgen_blockset:toreg_config',
18097 
            'block_handle' => 2144.00048828125,
18098 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33',
18099 
            'block_type' => 'toreg',
18100 
            'dbl_ovrd' => 0,
18101 
            'explicit_data_type' => 0,
18102 
            'gui_display_data_type' => 1,
18103 
            'init' => 0,
18104 
            'init_bit_vector' => '\'b0',
18105 
            'mdl_handle' => 2083.00048828125,
18106 
            'model_handle' => 2083.00048828125,
18107 
            'n_bits' => 16,
18108 
            'ownership' => 1,
18109 
            'preci_type' => 1,
18110 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18111 
            'shared_memory_name' => 'register14tv',
18112 
          },
18113 
          'needs_vhdl_wrapper' => 0,
18114 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33',
18115 
        },
18116 
        'entityName' => 'x_x25',
18117 
        'ports' => {
18118 
          'ce' => {
18119 
            'attributes' => {
18120 
              'domain' => '',
18121 
              'group' => 1,
18122 
              'isCe' => 1,
18123 
              'is_floating_block' => 1,
18124 
              'period' => 1,
18125 
              'type' => 'logic',
18126 
            },
18127 
            'direction' => 'in',
18128 
            'hdlType' => 'std_logic',
18129 
            'width' => 1,
18130 
          },
18131 
          'clk' => {
18132 
            'attributes' => {
18133 
              'domain' => '',
18134 
              'group' => 1,
18135 
              'isClk' => 1,
18136 
              'is_floating_block' => 1,
18137 
              'period' => 1,
18138 
              'type' => 'logic',
18139 
            },
18140 
            'direction' => 'in',
18141 
            'hdlType' => 'std_logic',
18142 
            'width' => 1,
18143 
          },
18144 
          'clr' => {
18145 
            'attributes' => {
18146 
              'domain' => '',
18147 
              'group' => 1,
18148 
              'isClr' => 1,
18149 
              'is_floating_block' => 1,
18150 
              'period' => 1,
18151 
              'type' => 'logic',
18152 
              'valid_bit_used' => 0,
18153 
            },
18154 
            'direction' => 'in',
18155 
            'hdlType' => 'std_logic',
18156 
            'width' => 1,
18157 
          },
18158 
          'data_in' => {
18159 
            'attributes' => {
18160 
              'bin_pt' => 0,
18161 
              'is_floating_block' => 1,
18162 
              'must_be_hdl_vector' => 1,
18163 
              'period' => 1,
18164 
              'port_id' => 0,
18165 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/data_in',
18166 
              'type' => 'Bool',
18167 
            },
18168 
            'direction' => 'in',
18169 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18170 
            'width' => 1,
18171 
          },
18172 
          'dout' => {
18173 
            'attributes' => {
18174 
              'bin_pt' => 0,
18175 
              'is_floating_block' => 1,
18176 
              'must_be_hdl_vector' => 1,
18177 
              'period' => 1,
18178 
              'port_id' => 0,
18179 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/dout',
18180 
              'type' => 'Bool',
18181 
            },
18182 
            'direction' => 'out',
18183 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18184 
            'width' => 1,
18185 
          },
18186 
          'en' => {
18187 
            'attributes' => {
18188 
              'bin_pt' => 0,
18189 
              'is_floating_block' => 1,
18190 
              'must_be_hdl_vector' => 1,
18191 
              'period' => 1,
18192 
              'port_id' => 1,
18193 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register33/en',
18194 
              'type' => 'Bool',
18195 
            },
18196 
            'direction' => 'in',
18197 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18198 
            'width' => 1,
18199 
          },
18200 
        },
18201 
      },
18202 
      'entityName' => 'x_x25',
18203 
    },
18204 
    'to_register34' => {
18205 
      'connections' => {
18206 
        'ce' => 'sysgen_dut.to_register34_ce',
18207 
        'clk' => 'sysgen_dut.to_register34_clk',
18208 
        'clr' => 'sysgen_dut.to_register34_clr',
18209 
        'data_in' => 'sysgen_dut.to_register34_data_in',
18210 
        'dout' => 'to_register34.dout',
18211 
        'en' => 'sysgen_dut.to_register34_en',
18212 
      },
18213 
      'entity' => {
18214 
        'attributes' => {
18215 
          'entityAlreadyNetlisted' => 1,
18216 
          'generics' => [
18217 
          ],
18218 
          'is_floating_block' => 1,
18219 
          'mask' => {
18220 
            'Block_Handle' => 2145.00048828125,
18221 
            'Block_handle' => 2145.00048828125,
18222 
            'MDL_Handle' => 2083.00048828125,
18223 
            'MDL_handle' => 2083.00048828125,
18224 
            'arith_type' => 1,
18225 
            'bin_pt' => 14,
18226 
            'block_config' => 'sysgen_blockset:toreg_config',
18227 
            'block_handle' => 2145.00048828125,
18228 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34',
18229 
            'block_type' => 'toreg',
18230 
            'dbl_ovrd' => 0,
18231 
            'explicit_data_type' => 0,
18232 
            'gui_display_data_type' => 1,
18233 
            'init' => 0,
18234 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
18235 
            'mdl_handle' => 2083.00048828125,
18236 
            'model_handle' => 2083.00048828125,
18237 
            'n_bits' => 16,
18238 
            'ownership' => 1,
18239 
            'preci_type' => 1,
18240 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18241 
            'shared_memory_name' => 'register14td',
18242 
          },
18243 
          'needs_vhdl_wrapper' => 0,
18244 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34',
18245 
        },
18246 
        'entityName' => 'x_x26',
18247 
        'ports' => {
18248 
          'ce' => {
18249 
            'attributes' => {
18250 
              'domain' => '',
18251 
              'group' => 1,
18252 
              'isCe' => 1,
18253 
              'is_floating_block' => 1,
18254 
              'period' => 1,
18255 
              'type' => 'logic',
18256 
            },
18257 
            'direction' => 'in',
18258 
            'hdlType' => 'std_logic',
18259 
            'width' => 1,
18260 
          },
18261 
          'clk' => {
18262 
            'attributes' => {
18263 
              'domain' => '',
18264 
              'group' => 1,
18265 
              'isClk' => 1,
18266 
              'is_floating_block' => 1,
18267 
              'period' => 1,
18268 
              'type' => 'logic',
18269 
            },
18270 
            'direction' => 'in',
18271 
            'hdlType' => 'std_logic',
18272 
            'width' => 1,
18273 
          },
18274 
          'clr' => {
18275 
            'attributes' => {
18276 
              'domain' => '',
18277 
              'group' => 1,
18278 
              'isClr' => 1,
18279 
              'is_floating_block' => 1,
18280 
              'period' => 1,
18281 
              'type' => 'logic',
18282 
              'valid_bit_used' => 0,
18283 
            },
18284 
            'direction' => 'in',
18285 
            'hdlType' => 'std_logic',
18286 
            'width' => 1,
18287 
          },
18288 
          'data_in' => {
18289 
            'attributes' => {
18290 
              'bin_pt' => 0,
18291 
              'is_floating_block' => 1,
18292 
              'must_be_hdl_vector' => 1,
18293 
              'period' => 1,
18294 
              'port_id' => 0,
18295 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/data_in',
18296 
              'type' => 'UFix_32_0',
18297 
            },
18298 
            'direction' => 'in',
18299 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18300 
            'width' => 32,
18301 
          },
18302 
          'dout' => {
18303 
            'attributes' => {
18304 
              'bin_pt' => 0,
18305 
              'is_floating_block' => 1,
18306 
              'must_be_hdl_vector' => 1,
18307 
              'period' => 1,
18308 
              'port_id' => 0,
18309 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/dout',
18310 
              'type' => 'UFix_32_0',
18311 
            },
18312 
            'direction' => 'out',
18313 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18314 
            'width' => 32,
18315 
          },
18316 
          'en' => {
18317 
            'attributes' => {
18318 
              'bin_pt' => 0,
18319 
              'is_floating_block' => 1,
18320 
              'must_be_hdl_vector' => 1,
18321 
              'period' => 1,
18322 
              'port_id' => 1,
18323 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register34/en',
18324 
              'type' => 'Bool',
18325 
            },
18326 
            'direction' => 'in',
18327 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18328 
            'width' => 1,
18329 
          },
18330 
        },
18331 
      },
18332 
      'entityName' => 'x_x26',
18333 
    },
18334 
    'to_register4' => {
18335 
      'connections' => {
18336 
        'ce' => 'sysgen_dut.to_register4_ce',
18337 
        'clk' => 'sysgen_dut.to_register4_clk',
18338 
        'clr' => 'sysgen_dut.to_register4_clr',
18339 
        'data_in' => 'sysgen_dut.to_register4_data_in',
18340 
        'dout' => 'to_register4.dout',
18341 
        'en' => 'sysgen_dut.to_register4_en',
18342 
      },
18343 
      'entity' => {
18344 
        'attributes' => {
18345 
          'entityAlreadyNetlisted' => 1,
18346 
          'generics' => [
18347 
          ],
18348 
          'is_floating_block' => 1,
18349 
          'mask' => {
18350 
            'Block_Handle' => 2146.00048828125,
18351 
            'Block_handle' => 2146.00048828125,
18352 
            'MDL_Handle' => 2083.00048828125,
18353 
            'MDL_handle' => 2083.00048828125,
18354 
            'arith_type' => 1,
18355 
            'bin_pt' => 14,
18356 
            'block_config' => 'sysgen_blockset:toreg_config',
18357 
            'block_handle' => 2146.00048828125,
18358 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4',
18359 
            'block_type' => 'toreg',
18360 
            'dbl_ovrd' => 0,
18361 
            'explicit_data_type' => 0,
18362 
            'gui_display_data_type' => 1,
18363 
            'init' => 0,
18364 
            'init_bit_vector' => '\'b0',
18365 
            'mdl_handle' => 2083.00048828125,
18366 
            'model_handle' => 2083.00048828125,
18367 
            'n_bits' => 16,
18368 
            'ownership' => 1,
18369 
            'preci_type' => 1,
18370 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18371 
            'shared_memory_name' => 'register02tv',
18372 
          },
18373 
          'needs_vhdl_wrapper' => 0,
18374 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4',
18375 
        },
18376 
        'entityName' => 'x_x27',
18377 
        'ports' => {
18378 
          'ce' => {
18379 
            'attributes' => {
18380 
              'domain' => '',
18381 
              'group' => 1,
18382 
              'isCe' => 1,
18383 
              'is_floating_block' => 1,
18384 
              'period' => 1,
18385 
              'type' => 'logic',
18386 
            },
18387 
            'direction' => 'in',
18388 
            'hdlType' => 'std_logic',
18389 
            'width' => 1,
18390 
          },
18391 
          'clk' => {
18392 
            'attributes' => {
18393 
              'domain' => '',
18394 
              'group' => 1,
18395 
              'isClk' => 1,
18396 
              'is_floating_block' => 1,
18397 
              'period' => 1,
18398 
              'type' => 'logic',
18399 
            },
18400 
            'direction' => 'in',
18401 
            'hdlType' => 'std_logic',
18402 
            'width' => 1,
18403 
          },
18404 
          'clr' => {
18405 
            'attributes' => {
18406 
              'domain' => '',
18407 
              'group' => 1,
18408 
              'isClr' => 1,
18409 
              'is_floating_block' => 1,
18410 
              'period' => 1,
18411 
              'type' => 'logic',
18412 
              'valid_bit_used' => 0,
18413 
            },
18414 
            'direction' => 'in',
18415 
            'hdlType' => 'std_logic',
18416 
            'width' => 1,
18417 
          },
18418 
          'data_in' => {
18419 
            'attributes' => {
18420 
              'bin_pt' => 0,
18421 
              'is_floating_block' => 1,
18422 
              'must_be_hdl_vector' => 1,
18423 
              'period' => 1,
18424 
              'port_id' => 0,
18425 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/data_in',
18426 
              'type' => 'Bool',
18427 
            },
18428 
            'direction' => 'in',
18429 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18430 
            'width' => 1,
18431 
          },
18432 
          'dout' => {
18433 
            'attributes' => {
18434 
              'bin_pt' => 0,
18435 
              'is_floating_block' => 1,
18436 
              'must_be_hdl_vector' => 1,
18437 
              'period' => 1,
18438 
              'port_id' => 0,
18439 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/dout',
18440 
              'type' => 'Bool',
18441 
            },
18442 
            'direction' => 'out',
18443 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18444 
            'width' => 1,
18445 
          },
18446 
          'en' => {
18447 
            'attributes' => {
18448 
              'bin_pt' => 0,
18449 
              'is_floating_block' => 1,
18450 
              'must_be_hdl_vector' => 1,
18451 
              'period' => 1,
18452 
              'port_id' => 1,
18453 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register4/en',
18454 
              'type' => 'Bool',
18455 
            },
18456 
            'direction' => 'in',
18457 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18458 
            'width' => 1,
18459 
          },
18460 
        },
18461 
      },
18462 
      'entityName' => 'x_x27',
18463 
    },
18464 
    'to_register5' => {
18465 
      'connections' => {
18466 
        'ce' => 'sysgen_dut.to_register5_ce',
18467 
        'clk' => 'sysgen_dut.to_register5_clk',
18468 
        'clr' => 'sysgen_dut.to_register5_clr',
18469 
        'data_in' => 'sysgen_dut.to_register5_data_in',
18470 
        'dout' => 'to_register5.dout',
18471 
        'en' => 'sysgen_dut.to_register5_en',
18472 
      },
18473 
      'entity' => {
18474 
        'attributes' => {
18475 
          'entityAlreadyNetlisted' => 1,
18476 
          'generics' => [
18477 
          ],
18478 
          'is_floating_block' => 1,
18479 
          'mask' => {
18480 
            'Block_Handle' => 2147.00048828125,
18481 
            'Block_handle' => 2147.00048828125,
18482 
            'MDL_Handle' => 2083.00048828125,
18483 
            'MDL_handle' => 2083.00048828125,
18484 
            'arith_type' => 1,
18485 
            'bin_pt' => 14,
18486 
            'block_config' => 'sysgen_blockset:toreg_config',
18487 
            'block_handle' => 2147.00048828125,
18488 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5',
18489 
            'block_type' => 'toreg',
18490 
            'dbl_ovrd' => 0,
18491 
            'explicit_data_type' => 0,
18492 
            'gui_display_data_type' => 1,
18493 
            'init' => 0,
18494 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
18495 
            'mdl_handle' => 2083.00048828125,
18496 
            'model_handle' => 2083.00048828125,
18497 
            'n_bits' => 16,
18498 
            'ownership' => 1,
18499 
            'preci_type' => 1,
18500 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18501 
            'shared_memory_name' => 'register02td',
18502 
          },
18503 
          'needs_vhdl_wrapper' => 0,
18504 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5',
18505 
        },
18506 
        'entityName' => 'x_x28',
18507 
        'ports' => {
18508 
          'ce' => {
18509 
            'attributes' => {
18510 
              'domain' => '',
18511 
              'group' => 1,
18512 
              'isCe' => 1,
18513 
              'is_floating_block' => 1,
18514 
              'period' => 1,
18515 
              'type' => 'logic',
18516 
            },
18517 
            'direction' => 'in',
18518 
            'hdlType' => 'std_logic',
18519 
            'width' => 1,
18520 
          },
18521 
          'clk' => {
18522 
            'attributes' => {
18523 
              'domain' => '',
18524 
              'group' => 1,
18525 
              'isClk' => 1,
18526 
              'is_floating_block' => 1,
18527 
              'period' => 1,
18528 
              'type' => 'logic',
18529 
            },
18530 
            'direction' => 'in',
18531 
            'hdlType' => 'std_logic',
18532 
            'width' => 1,
18533 
          },
18534 
          'clr' => {
18535 
            'attributes' => {
18536 
              'domain' => '',
18537 
              'group' => 1,
18538 
              'isClr' => 1,
18539 
              'is_floating_block' => 1,
18540 
              'period' => 1,
18541 
              'type' => 'logic',
18542 
              'valid_bit_used' => 0,
18543 
            },
18544 
            'direction' => 'in',
18545 
            'hdlType' => 'std_logic',
18546 
            'width' => 1,
18547 
          },
18548 
          'data_in' => {
18549 
            'attributes' => {
18550 
              'bin_pt' => 0,
18551 
              'is_floating_block' => 1,
18552 
              'must_be_hdl_vector' => 1,
18553 
              'period' => 1,
18554 
              'port_id' => 0,
18555 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/data_in',
18556 
              'type' => 'UFix_32_0',
18557 
            },
18558 
            'direction' => 'in',
18559 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18560 
            'width' => 32,
18561 
          },
18562 
          'dout' => {
18563 
            'attributes' => {
18564 
              'bin_pt' => 0,
18565 
              'is_floating_block' => 1,
18566 
              'must_be_hdl_vector' => 1,
18567 
              'period' => 1,
18568 
              'port_id' => 0,
18569 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/dout',
18570 
              'type' => 'UFix_32_0',
18571 
            },
18572 
            'direction' => 'out',
18573 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18574 
            'width' => 32,
18575 
          },
18576 
          'en' => {
18577 
            'attributes' => {
18578 
              'bin_pt' => 0,
18579 
              'is_floating_block' => 1,
18580 
              'must_be_hdl_vector' => 1,
18581 
              'period' => 1,
18582 
              'port_id' => 1,
18583 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register5/en',
18584 
              'type' => 'Bool',
18585 
            },
18586 
            'direction' => 'in',
18587 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18588 
            'width' => 1,
18589 
          },
18590 
        },
18591 
      },
18592 
      'entityName' => 'x_x28',
18593 
    },
18594 
    'to_register6' => {
18595 
      'connections' => {
18596 
        'ce' => 'sysgen_dut.to_register6_ce',
18597 
        'clk' => 'sysgen_dut.to_register6_clk',
18598 
        'clr' => 'sysgen_dut.to_register6_clr',
18599 
        'data_in' => 'sysgen_dut.to_register6_data_in',
18600 
        'dout' => 'to_register6.dout',
18601 
        'en' => 'sysgen_dut.to_register6_en',
18602 
      },
18603 
      'entity' => {
18604 
        'attributes' => {
18605 
          'entityAlreadyNetlisted' => 1,
18606 
          'generics' => [
18607 
          ],
18608 
          'is_floating_block' => 1,
18609 
          'mask' => {
18610 
            'Block_Handle' => 2148.00048828125,
18611 
            'Block_handle' => 2148.00048828125,
18612 
            'MDL_Handle' => 2083.00048828125,
18613 
            'MDL_handle' => 2083.00048828125,
18614 
            'arith_type' => 1,
18615 
            'bin_pt' => 14,
18616 
            'block_config' => 'sysgen_blockset:toreg_config',
18617 
            'block_handle' => 2148.00048828125,
18618 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6',
18619 
            'block_type' => 'toreg',
18620 
            'dbl_ovrd' => 0,
18621 
            'explicit_data_type' => 0,
18622 
            'gui_display_data_type' => 1,
18623 
            'init' => 0,
18624 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
18625 
            'mdl_handle' => 2083.00048828125,
18626 
            'model_handle' => 2083.00048828125,
18627 
            'n_bits' => 16,
18628 
            'ownership' => 1,
18629 
            'preci_type' => 1,
18630 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18631 
            'shared_memory_name' => 'debug1i',
18632 
          },
18633 
          'needs_vhdl_wrapper' => 0,
18634 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6',
18635 
        },
18636 
        'entityName' => 'x_x29',
18637 
        'ports' => {
18638 
          'ce' => {
18639 
            'attributes' => {
18640 
              'domain' => '',
18641 
              'group' => 1,
18642 
              'isCe' => 1,
18643 
              'is_floating_block' => 1,
18644 
              'period' => 1,
18645 
              'type' => 'logic',
18646 
            },
18647 
            'direction' => 'in',
18648 
            'hdlType' => 'std_logic',
18649 
            'width' => 1,
18650 
          },
18651 
          'clk' => {
18652 
            'attributes' => {
18653 
              'domain' => '',
18654 
              'group' => 1,
18655 
              'isClk' => 1,
18656 
              'is_floating_block' => 1,
18657 
              'period' => 1,
18658 
              'type' => 'logic',
18659 
            },
18660 
            'direction' => 'in',
18661 
            'hdlType' => 'std_logic',
18662 
            'width' => 1,
18663 
          },
18664 
          'clr' => {
18665 
            'attributes' => {
18666 
              'domain' => '',
18667 
              'group' => 1,
18668 
              'isClr' => 1,
18669 
              'is_floating_block' => 1,
18670 
              'period' => 1,
18671 
              'type' => 'logic',
18672 
              'valid_bit_used' => 0,
18673 
            },
18674 
            'direction' => 'in',
18675 
            'hdlType' => 'std_logic',
18676 
            'width' => 1,
18677 
          },
18678 
          'data_in' => {
18679 
            'attributes' => {
18680 
              'bin_pt' => 0,
18681 
              'is_floating_block' => 1,
18682 
              'must_be_hdl_vector' => 1,
18683 
              'period' => 1,
18684 
              'port_id' => 0,
18685 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/data_in',
18686 
              'type' => 'UFix_32_0',
18687 
            },
18688 
            'direction' => 'in',
18689 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18690 
            'width' => 32,
18691 
          },
18692 
          'dout' => {
18693 
            'attributes' => {
18694 
              'bin_pt' => 0,
18695 
              'is_floating_block' => 1,
18696 
              'must_be_hdl_vector' => 1,
18697 
              'period' => 1,
18698 
              'port_id' => 0,
18699 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/dout',
18700 
              'type' => 'UFix_32_0',
18701 
            },
18702 
            'direction' => 'out',
18703 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18704 
            'width' => 32,
18705 
          },
18706 
          'en' => {
18707 
            'attributes' => {
18708 
              'bin_pt' => 0,
18709 
              'is_floating_block' => 1,
18710 
              'must_be_hdl_vector' => 1,
18711 
              'period' => 1,
18712 
              'port_id' => 1,
18713 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register6/en',
18714 
              'type' => 'Bool',
18715 
            },
18716 
            'direction' => 'in',
18717 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18718 
            'width' => 1,
18719 
          },
18720 
        },
18721 
      },
18722 
      'entityName' => 'x_x29',
18723 
    },
18724 
    'to_register7' => {
18725 
      'connections' => {
18726 
        'ce' => 'sysgen_dut.to_register7_ce',
18727 
        'clk' => 'sysgen_dut.to_register7_clk',
18728 
        'clr' => 'sysgen_dut.to_register7_clr',
18729 
        'data_in' => 'sysgen_dut.to_register7_data_in',
18730 
        'dout' => 'to_register7.dout',
18731 
        'en' => 'sysgen_dut.to_register7_en',
18732 
      },
18733 
      'entity' => {
18734 
        'attributes' => {
18735 
          'entityAlreadyNetlisted' => 1,
18736 
          'generics' => [
18737 
          ],
18738 
          'is_floating_block' => 1,
18739 
          'mask' => {
18740 
            'Block_Handle' => 2149.00048828125,
18741 
            'Block_handle' => 2149.00048828125,
18742 
            'MDL_Handle' => 2083.00048828125,
18743 
            'MDL_handle' => 2083.00048828125,
18744 
            'arith_type' => 1,
18745 
            'bin_pt' => 14,
18746 
            'block_config' => 'sysgen_blockset:toreg_config',
18747 
            'block_handle' => 2149.00048828125,
18748 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7',
18749 
            'block_type' => 'toreg',
18750 
            'dbl_ovrd' => 0,
18751 
            'explicit_data_type' => 0,
18752 
            'gui_display_data_type' => 1,
18753 
            'init' => 0,
18754 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
18755 
            'mdl_handle' => 2083.00048828125,
18756 
            'model_handle' => 2083.00048828125,
18757 
            'n_bits' => 16,
18758 
            'ownership' => 1,
18759 
            'preci_type' => 1,
18760 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18761 
            'shared_memory_name' => 'register01td',
18762 
          },
18763 
          'needs_vhdl_wrapper' => 0,
18764 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7',
18765 
        },
18766 
        'entityName' => 'x_x30',
18767 
        'ports' => {
18768 
          'ce' => {
18769 
            'attributes' => {
18770 
              'domain' => '',
18771 
              'group' => 1,
18772 
              'isCe' => 1,
18773 
              'is_floating_block' => 1,
18774 
              'period' => 1,
18775 
              'type' => 'logic',
18776 
            },
18777 
            'direction' => 'in',
18778 
            'hdlType' => 'std_logic',
18779 
            'width' => 1,
18780 
          },
18781 
          'clk' => {
18782 
            'attributes' => {
18783 
              'domain' => '',
18784 
              'group' => 1,
18785 
              'isClk' => 1,
18786 
              'is_floating_block' => 1,
18787 
              'period' => 1,
18788 
              'type' => 'logic',
18789 
            },
18790 
            'direction' => 'in',
18791 
            'hdlType' => 'std_logic',
18792 
            'width' => 1,
18793 
          },
18794 
          'clr' => {
18795 
            'attributes' => {
18796 
              'domain' => '',
18797 
              'group' => 1,
18798 
              'isClr' => 1,
18799 
              'is_floating_block' => 1,
18800 
              'period' => 1,
18801 
              'type' => 'logic',
18802 
              'valid_bit_used' => 0,
18803 
            },
18804 
            'direction' => 'in',
18805 
            'hdlType' => 'std_logic',
18806 
            'width' => 1,
18807 
          },
18808 
          'data_in' => {
18809 
            'attributes' => {
18810 
              'bin_pt' => 0,
18811 
              'is_floating_block' => 1,
18812 
              'must_be_hdl_vector' => 1,
18813 
              'period' => 1,
18814 
              'port_id' => 0,
18815 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/data_in',
18816 
              'type' => 'UFix_32_0',
18817 
            },
18818 
            'direction' => 'in',
18819 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18820 
            'width' => 32,
18821 
          },
18822 
          'dout' => {
18823 
            'attributes' => {
18824 
              'bin_pt' => 0,
18825 
              'is_floating_block' => 1,
18826 
              'must_be_hdl_vector' => 1,
18827 
              'period' => 1,
18828 
              'port_id' => 0,
18829 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/dout',
18830 
              'type' => 'UFix_32_0',
18831 
            },
18832 
            'direction' => 'out',
18833 
            'hdlType' => 'std_logic_vector(31 downto 0)',
18834 
            'width' => 32,
18835 
          },
18836 
          'en' => {
18837 
            'attributes' => {
18838 
              'bin_pt' => 0,
18839 
              'is_floating_block' => 1,
18840 
              'must_be_hdl_vector' => 1,
18841 
              'period' => 1,
18842 
              'port_id' => 1,
18843 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
18844 
              'type' => 'Bool',
18845 
            },
18846 
            'direction' => 'in',
18847 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18848 
            'width' => 1,
18849 
          },
18850 
        },
18851 
      },
18852 
      'entityName' => 'x_x30',
18853 
    },
18854 
    'to_register8' => {
18855 
      'connections' => {
18856 
        'ce' => 'sysgen_dut.to_register8_ce',
18857 
        'clk' => 'sysgen_dut.to_register8_clk',
18858 
        'clr' => 'sysgen_dut.to_register8_clr',
18859 
        'data_in' => 'sysgen_dut.to_register8_data_in',
18860 
        'dout' => 'to_register8.dout',
18861 
        'en' => 'sysgen_dut.to_register8_en',
18862 
      },
18863 
      'entity' => {
18864 
        'attributes' => {
18865 
          'entityAlreadyNetlisted' => 1,
18866 
          'generics' => [
18867 
          ],
18868 
          'is_floating_block' => 1,
18869 
          'mask' => {
18870 
            'Block_Handle' => 2150.00048828125,
18871 
            'Block_handle' => 2150.00048828125,
18872 
            'MDL_Handle' => 2083.00048828125,
18873 
            'MDL_handle' => 2083.00048828125,
18874 
            'arith_type' => 1,
18875 
            'bin_pt' => 14,
18876 
            'block_config' => 'sysgen_blockset:toreg_config',
18877 
            'block_handle' => 2150.00048828125,
18878 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8',
18879 
            'block_type' => 'toreg',
18880 
            'dbl_ovrd' => 0,
18881 
            'explicit_data_type' => 0,
18882 
            'gui_display_data_type' => 1,
18883 
            'init' => 0,
18884 
            'init_bit_vector' => '\'b0',
18885 
            'mdl_handle' => 2083.00048828125,
18886 
            'model_handle' => 2083.00048828125,
18887 
            'n_bits' => 16,
18888 
            'ownership' => 1,
18889 
            'preci_type' => 1,
18890 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
18891 
            'shared_memory_name' => 'register03tv',
18892 
          },
18893 
          'needs_vhdl_wrapper' => 0,
18894 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8',
18895 
        },
18896 
        'entityName' => 'x_x31',
18897 
        'ports' => {
18898 
          'ce' => {
18899 
            'attributes' => {
18900 
              'domain' => '',
18901 
              'group' => 1,
18902 
              'isCe' => 1,
18903 
              'is_floating_block' => 1,
18904 
              'period' => 1,
18905 
              'type' => 'logic',
18906 
            },
18907 
            'direction' => 'in',
18908 
            'hdlType' => 'std_logic',
18909 
            'width' => 1,
18910 
          },
18911 
          'clk' => {
18912 
            'attributes' => {
18913 
              'domain' => '',
18914 
              'group' => 1,
18915 
              'isClk' => 1,
18916 
              'is_floating_block' => 1,
18917 
              'period' => 1,
18918 
              'type' => 'logic',
18919 
            },
18920 
            'direction' => 'in',
18921 
            'hdlType' => 'std_logic',
18922 
            'width' => 1,
18923 
          },
18924 
          'clr' => {
18925 
            'attributes' => {
18926 
              'domain' => '',
18927 
              'group' => 1,
18928 
              'isClr' => 1,
18929 
              'is_floating_block' => 1,
18930 
              'period' => 1,
18931 
              'type' => 'logic',
18932 
              'valid_bit_used' => 0,
18933 
            },
18934 
            'direction' => 'in',
18935 
            'hdlType' => 'std_logic',
18936 
            'width' => 1,
18937 
          },
18938 
          'data_in' => {
18939 
            'attributes' => {
18940 
              'bin_pt' => 0,
18941 
              'is_floating_block' => 1,
18942 
              'must_be_hdl_vector' => 1,
18943 
              'period' => 1,
18944 
              'port_id' => 0,
18945 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
18946 
              'type' => 'Bool',
18947 
            },
18948 
            'direction' => 'in',
18949 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18950 
            'width' => 1,
18951 
          },
18952 
          'dout' => {
18953 
            'attributes' => {
18954 
              'bin_pt' => 0,
18955 
              'is_floating_block' => 1,
18956 
              'must_be_hdl_vector' => 1,
18957 
              'period' => 1,
18958 
              'port_id' => 0,
18959 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
18960 
              'type' => 'Bool',
18961 
            },
18962 
            'direction' => 'out',
18963 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18964 
            'width' => 1,
18965 
          },
18966 
          'en' => {
18967 
            'attributes' => {
18968 
              'bin_pt' => 0,
18969 
              'is_floating_block' => 1,
18970 
              'must_be_hdl_vector' => 1,
18971 
              'period' => 1,
18972 
              'port_id' => 1,
18973 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
18974 
              'type' => 'Bool',
18975 
            },
18976 
            'direction' => 'in',
18977 
            'hdlType' => 'std_logic_vector(0 downto 0)',
18978 
            'width' => 1,
18979 
          },
18980 
        },
18981 
      },
18982 
      'entityName' => 'x_x31',
18983 
    },
18984 
    'to_register9' => {
18985 
      'connections' => {
18986 
        'ce' => 'sysgen_dut.to_register9_ce',
18987 
        'clk' => 'sysgen_dut.to_register9_clk',
18988 
        'clr' => 'sysgen_dut.to_register9_clr',
18989 
        'data_in' => 'sysgen_dut.to_register9_data_in',
18990 
        'dout' => 'to_register9.dout',
18991 
        'en' => 'sysgen_dut.to_register9_en',
18992 
      },
18993 
      'entity' => {
18994 
        'attributes' => {
18995 
          'entityAlreadyNetlisted' => 1,
18996 
          'generics' => [
18997 
          ],
18998 
          'is_floating_block' => 1,
18999 
          'mask' => {
19000 
            'Block_Handle' => 2151.00048828125,
19001 
            'Block_handle' => 2151.00048828125,
19002 
            'MDL_Handle' => 2083.00048828125,
19003 
            'MDL_handle' => 2083.00048828125,
19004 
            'arith_type' => 1,
19005 
            'bin_pt' => 14,
19006 
            'block_config' => 'sysgen_blockset:toreg_config',
19007 
            'block_handle' => 2151.00048828125,
19008 
            'block_name' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
19009 
            'block_type' => 'toreg',
19010 
            'dbl_ovrd' => 0,
19011 
            'explicit_data_type' => 0,
19012 
            'gui_display_data_type' => 1,
19013 
            'init' => 0,
19014 
            'init_bit_vector' => '\'b00000000000000000000000000000000',
19015 
            'mdl_handle' => 2083.00048828125,
19016 
            'model_handle' => 2083.00048828125,
19017 
            'n_bits' => 16,
19018 
            'ownership' => 1,
19019 
            'preci_type' => 1,
19020 
            'sg_icon_stat' => '60,33,2,1,white,blue,0,10ab453e,right,,[ ],[ ]',
19021 
            'shared_memory_name' => 'register03td',
19022 
          },
19023 
          'needs_vhdl_wrapper' => 0,
19024 
          'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9',
19025 
        },
19026 
        'entityName' => 'x_x32',
19027 
        'ports' => {
19028 
          'ce' => {
19029 
            'attributes' => {
19030 
              'domain' => '',
19031 
              'group' => 1,
19032 
              'isCe' => 1,
19033 
              'is_floating_block' => 1,
19034 
              'period' => 1,
19035 
              'type' => 'logic',
19036 
            },
19037 
            'direction' => 'in',
19038 
            'hdlType' => 'std_logic',
19039 
            'width' => 1,
19040 
          },
19041 
          'clk' => {
19042 
            'attributes' => {
19043 
              'domain' => '',
19044 
              'group' => 1,
19045 
              'isClk' => 1,
19046 
              'is_floating_block' => 1,
19047 
              'period' => 1,
19048 
              'type' => 'logic',
19049 
            },
19050 
            'direction' => 'in',
19051 
            'hdlType' => 'std_logic',
19052 
            'width' => 1,
19053 
          },
19054 
          'clr' => {
19055 
            'attributes' => {
19056 
              'domain' => '',
19057 
              'group' => 1,
19058 
              'isClr' => 1,
19059 
              'is_floating_block' => 1,
19060 
              'period' => 1,
19061 
              'type' => 'logic',
19062 
              'valid_bit_used' => 0,
19063 
            },
19064 
            'direction' => 'in',
19065 
            'hdlType' => 'std_logic',
19066 
            'width' => 1,
19067 
          },
19068 
          'data_in' => {
19069 
            'attributes' => {
19070 
              'bin_pt' => 0,
19071 
              'is_floating_block' => 1,
19072 
              'must_be_hdl_vector' => 1,
19073 
              'period' => 1,
19074 
              'port_id' => 0,
19075 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
19076 
              'type' => 'UFix_32_0',
19077 
            },
19078 
            'direction' => 'in',
19079 
            'hdlType' => 'std_logic_vector(31 downto 0)',
19080 
            'width' => 32,
19081 
          },
19082 
          'dout' => {
19083 
            'attributes' => {
19084 
              'bin_pt' => 0,
19085 
              'is_floating_block' => 1,
19086 
              'must_be_hdl_vector' => 1,
19087 
              'period' => 1,
19088 
              'port_id' => 0,
19089 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
19090 
              'type' => 'UFix_32_0',
19091 
            },
19092 
            'direction' => 'out',
19093 
            'hdlType' => 'std_logic_vector(31 downto 0)',
19094 
            'width' => 32,
19095 
          },
19096 
          'en' => {
19097 
            'attributes' => {
19098 
              'bin_pt' => 0,
19099 
              'is_floating_block' => 1,
19100 
              'must_be_hdl_vector' => 1,
19101 
              'period' => 1,
19102 
              'port_id' => 1,
19103 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
19104 
              'type' => 'Bool',
19105 
            },
19106 
            'direction' => 'in',
19107 
            'hdlType' => 'std_logic_vector(0 downto 0)',
19108 
            'width' => 1,
19109 
          },
19110 
        },
19111 
      },
19112 
      'entityName' => 'x_x32',
19113 
    },
19114 
  },
19115 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.