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barabba |
Release 13.3 - xst O.76xd (nt)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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-->
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Reading constraint file inout_logic_cw.xcf.
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XCF parsing done.
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Parsing
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3) HDL Elaboration
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4) HDL Synthesis
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4.1) HDL Synthesis Report
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5) Advanced HDL Synthesis
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5.1) Advanced HDL Synthesis Report
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6) Low Level Synthesis
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7) Partition Report
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8) Design Summary
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8.1) Primitive and Black Box Usage
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8.2) Device utilization summary
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8.3) Partition Resource Summary
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8.4) Timing Report
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8.4.1) Clock Information
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8.4.2) Asynchronous Control Signals Information
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8.4.3) Timing Summary
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8.4.4) Timing Details
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8.4.5) Cross Clock Domains Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "xst_inout_logic.prj"
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Input Format : mixed
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Synthesis Constraint File : inout_logic_cw.xcf
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---- Target Parameters
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Output File Name : "inout_logic_cw.ngc"
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Output Format : NGC
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Target Device : xc6vlx240t-1ff1156
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---- Source Options
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Entity Name : inout_logic_cw
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Top Module Name : inout_logic_cw
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Automatic Register Balancing : no
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---- Target Options
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Add IO Buffers : NO
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Pack IO Registers into IOBs : Auto
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---- General Options
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Keep Hierarchy : NO
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Bus Delimiter : ()
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Hierarchy Separator : /
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Write Timing Constraints : yes
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---- Other Options
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report_timing_constraint_problems : warning
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=========================================================================
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WARNING:Xst:29 - Optimization Effort not specified
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The following parameters have been added:
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Optimization Goal : SPEED
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=========================================================================
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=========================================================================
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* HDL Parsing *
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=========================================================================
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Parsing VHDL file "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic.vhd" into library work
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Parsing package .
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Parsing package body .
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Parsing entity .
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Parsing architecture of entity .
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Parsing entity .
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Parsing architecture of entity .
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Parsing entity .
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Parsing architecture of entity .
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Parsing entity .
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Parsing architecture of entity .
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Parsing entity .
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Parsing architecture of entity .
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Parsing entity .
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Parsing architecture of entity .
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Parsing entity .
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Parsing architecture of entity .
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Parsing VHDL file "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" into library work
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Parsing entity .
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Parsing architecture of entity .
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Parsing entity .
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Parsing architecture of entity .
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Parsing entity .
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Parsing architecture of entity .
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=========================================================================
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* HDL Elaboration *
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=========================================================================
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Elaborating entity (architecture ) from library .
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 986: Assignment to to_register10_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 987: Assignment to to_register11_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 988: Assignment to to_register12_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 989: Assignment to to_register13_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 990: Assignment to to_register14_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 991: Assignment to to_register15_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 992: Assignment to to_register16_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 993: Assignment to to_register17_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 994: Assignment to to_register18_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 995: Assignment to to_register19_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 996: Assignment to to_register1_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 997: Assignment to to_register20_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 998: Assignment to to_register21_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 999: Assignment to to_register22_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1000: Assignment to to_register23_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1001: Assignment to to_register24_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1002: Assignment to to_register25_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1003: Assignment to to_register26_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1004: Assignment to to_register27_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1005: Assignment to to_register28_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1006: Assignment to to_register29_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1007: Assignment to to_register2_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1008: Assignment to to_register30_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1009: Assignment to to_register31_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1010: Assignment to to_register32_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1011: Assignment to to_register33_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1012: Assignment to to_register34_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1013: Assignment to to_register3_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1014: Assignment to to_register4_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1015: Assignment to to_register5_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1016: Assignment to to_register6_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1017: Assignment to to_register7_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1018: Assignment to to_register8_dout_net ignored, since the identifier is never used
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WARNING:HDLCompiler:1127 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic_cw.vhd" Line 1019: Assignment to to_register9_dout_net ignored, since the identifier is never used
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Elaborating entity (architecture ) from library .
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Elaborating entity (architecture ) with generics from library .
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Elaborating entity (architecture ) with generics from library .
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Elaborating entity (architecture ) with generics from library .
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WARNING:HDLCompiler:89 - "C:\Temp\Xilinx PCI Express\ML605_ISE13.3\MyUserLogic\UserLogic_00\top_level_0_PCIe_UserLogic_00_INOUT_LOGIC\synth_model\inout_logic.vhd" Line 1727: remains a black-box since it has no binding entity.
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Elaborating entity (architecture ) from library .
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Elaborating entity (architecture ) from library .
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit .
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Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd".
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Set property "syn_black_box = true" for instance .
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Set property "syn_noprune = true" for instance .
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Set property "optimize_primitives = false" for instance .
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Set property "dont_touch = true" for instance .
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Set property "MAX_FANOUT = REDUCE" for signal .
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Set property "syn_keep = true" for signal .
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Set property "KEEP = TRUE" for signal .
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WARNING:Xst:37 - Detected unknown constraint/property "preserve_signal". This constraint/property is not supported by the current software release and will be ignored.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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|
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
185 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
186 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
187 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
188 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
189 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
190 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
191 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
192 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
193 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
194 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
195 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
196 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
197 |
|
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
198 |
|
|
Summary:
|
199 |
|
|
no macro.
|
200 |
|
|
Unit synthesized.
|
201 |
|
|
|
202 |
|
|
Synthesizing Unit .
|
203 |
|
|
Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd".
|
204 |
|
|
Set property "syn_noprune = true".
|
205 |
|
|
Set property "optimize_primitives = false".
|
206 |
|
|
Set property "dont_touch = true".
|
207 |
|
|
INFO:Xst:3210 - "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd" line 378: Output port of the instance is unconnected or connected to loadless signal.
|
208 |
|
|
INFO:Xst:3210 - "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd" line 378: Output port of the instance is unconnected or connected to loadless signal.
|
209 |
|
|
Summary:
|
210 |
|
|
no macro.
|
211 |
|
|
Unit synthesized.
|
212 |
|
|
|
213 |
|
|
Synthesizing Unit .
|
214 |
|
|
Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd".
|
215 |
|
|
period = 1
|
216 |
|
|
log_2_period = 1
|
217 |
|
|
pipeline_regs = 5
|
218 |
|
|
use_bufg = 0
|
219 |
|
|
Set property "MAX_FANOUT = REDUCE" for signal .
|
220 |
|
|
Set property "MAX_FANOUT = REDUCE" for signal .
|
221 |
|
|
INFO:Xst:3210 - "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic_cw.vhd" line 254: Output port of the instance is unconnected or connected to loadless signal.
|
222 |
|
|
Summary:
|
223 |
|
|
no macro.
|
224 |
|
|
Unit synthesized.
|
225 |
|
|
|
226 |
|
|
Synthesizing Unit .
|
227 |
|
|
Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic.vhd".
|
228 |
|
|
width = 1
|
229 |
|
|
init_index = 0
|
230 |
|
|
init_value = "0000"
|
231 |
|
|
latency = 1
|
232 |
|
|
Summary:
|
233 |
|
|
no macro.
|
234 |
|
|
Unit synthesized.
|
235 |
|
|
|
236 |
|
|
Synthesizing Unit .
|
237 |
|
|
Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic.vhd".
|
238 |
|
|
width = 1
|
239 |
|
|
init_index = 0
|
240 |
|
|
init_value = "0000"
|
241 |
|
|
Set property "syn_black_box = true" for instance .
|
242 |
|
|
WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored.
|
243 |
|
|
Summary:
|
244 |
|
|
no macro.
|
245 |
|
|
Unit synthesized.
|
246 |
|
|
|
247 |
|
|
Synthesizing Unit .
|
248 |
|
|
Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic.vhd".
|
249 |
|
|
Summary:
|
250 |
|
|
no macro.
|
251 |
|
|
Unit synthesized.
|
252 |
|
|
|
253 |
|
|
Synthesizing Unit .
|
254 |
|
|
Related source file is "c:/temp/xilinx pci express/ml605_ise13.3/myuserlogic/userlogic_00/top_level_0_pcie_userlogic_00_inout_logic/synth_model/inout_logic.vhd".
|
255 |
|
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
256 |
|
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
257 |
|
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
258 |
|
|
Summary:
|
259 |
|
|
no macro.
|
260 |
|
|
Unit synthesized.
|
261 |
|
|
|
262 |
|
|
=========================================================================
|
263 |
|
|
HDL Synthesis Report
|
264 |
|
|
|
265 |
|
|
Found no macro
|
266 |
|
|
=========================================================================
|
267 |
|
|
|
268 |
|
|
=========================================================================
|
269 |
|
|
* Advanced HDL Synthesis *
|
270 |
|
|
=========================================================================
|
271 |
|
|
|
272 |
|
|
Reading core .
|
273 |
|
|
Loading core for timing and area information for instance .
|
274 |
|
|
|
275 |
|
|
=========================================================================
|
276 |
|
|
Advanced HDL Synthesis Report
|
277 |
|
|
|
278 |
|
|
Macro Statistics
|
279 |
|
|
# Registers : 1
|
280 |
|
|
Flip-Flops : 1
|
281 |
|
|
|
282 |
|
|
=========================================================================
|
283 |
|
|
|
284 |
|
|
=========================================================================
|
285 |
|
|
* Low Level Synthesis *
|
286 |
|
|
=========================================================================
|
287 |
|
|
WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed
|
288 |
|
|
|
289 |
|
|
Optimizing unit ...
|
290 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
291 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
292 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
293 |
|
|
|
294 |
|
|
Mapping all equations...
|
295 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
296 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
297 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
298 |
|
|
Annotating constraints using XCF file 'inout_logic_cw.xcf'
|
299 |
|
|
XCF parsing done.
|
300 |
|
|
Building and optimizing final netlist ...
|
301 |
|
|
Found area constraint ratio of 100 (+ 0) on block inout_logic_cw, actual ratio is 0.
|
302 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
303 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
304 |
|
|
|
305 |
|
|
Final Macro Processing ...
|
306 |
|
|
|
307 |
|
|
=========================================================================
|
308 |
|
|
Final Register Report
|
309 |
|
|
|
310 |
|
|
Macro Statistics
|
311 |
|
|
# Registers : 1
|
312 |
|
|
Flip-Flops : 1
|
313 |
|
|
|
314 |
|
|
=========================================================================
|
315 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
316 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
|
317 |
|
|
|
318 |
|
|
=========================================================================
|
319 |
|
|
* Partition Report *
|
320 |
|
|
=========================================================================
|
321 |
|
|
|
322 |
|
|
Partition Implementation Status
|
323 |
|
|
-------------------------------
|
324 |
|
|
|
325 |
|
|
No Partitions were found in this design.
|
326 |
|
|
|
327 |
|
|
-------------------------------
|
328 |
|
|
|
329 |
|
|
=========================================================================
|
330 |
|
|
* Design Summary *
|
331 |
|
|
=========================================================================
|
332 |
|
|
|
333 |
|
|
Top Level Output File Name : inout_logic_cw.ngc
|
334 |
|
|
|
335 |
|
|
Primitive and Black Box Usage:
|
336 |
|
|
------------------------------
|
337 |
|
|
# BELS : 2
|
338 |
|
|
# GND : 1
|
339 |
|
|
# VCC : 1
|
340 |
|
|
# FlipFlops/Latches : 2
|
341 |
|
|
# FD : 1
|
342 |
|
|
# FDRE : 1
|
343 |
|
|
# Others : 1
|
344 |
|
|
# TIMESPEC : 1
|
345 |
|
|
|
346 |
|
|
Device utilization summary:
|
347 |
|
|
---------------------------
|
348 |
|
|
|
349 |
|
|
Selected Device : 6vlx240tff1156-1
|
350 |
|
|
|
351 |
|
|
|
352 |
|
|
Slice Logic Utilization:
|
353 |
|
|
Number of Slice Registers: 2 out of 301440 0%
|
354 |
|
|
|
355 |
|
|
Slice Logic Distribution:
|
356 |
|
|
Number of LUT Flip Flop pairs used: 2
|
357 |
|
|
Number with an unused Flip Flop: 0 out of 2 0%
|
358 |
|
|
Number with an unused LUT: 2 out of 2 100%
|
359 |
|
|
Number of fully used LUT-FF pairs: 0 out of 2 0%
|
360 |
|
|
Number of unique control sets: 2
|
361 |
|
|
|
362 |
|
|
IO Utilization:
|
363 |
|
|
Number of IOs: 2838
|
364 |
|
|
Number of bonded IOBs: 0 out of 600 0%
|
365 |
|
|
|
366 |
|
|
Specific Feature Utilization:
|
367 |
|
|
|
368 |
|
|
---------------------------
|
369 |
|
|
Partition Resource Summary:
|
370 |
|
|
---------------------------
|
371 |
|
|
|
372 |
|
|
No Partitions were found in this design.
|
373 |
|
|
|
374 |
|
|
---------------------------
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
=========================================================================
|
378 |
|
|
Timing Report
|
379 |
|
|
|
380 |
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
381 |
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
382 |
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
383 |
|
|
|
384 |
|
|
Clock Information:
|
385 |
|
|
------------------
|
386 |
|
|
-----------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
|
387 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
388 |
|
|
-----------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
|
389 |
|
|
to_register9_clk | NONE(default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp)| 2 |
|
390 |
|
|
-----------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------+
|
391 |
|
|
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
392 |
|
|
|
393 |
|
|
Asynchronous Control Signals Information:
|
394 |
|
|
----------------------------------------
|
395 |
|
|
No asynchronous control signals found in this design
|
396 |
|
|
|
397 |
|
|
Timing Summary:
|
398 |
|
|
---------------
|
399 |
|
|
Speed Grade: -1
|
400 |
|
|
|
401 |
|
|
Minimum period: 0.785ns (Maximum Frequency: 1273.885MHz)
|
402 |
|
|
Minimum input arrival time before clock: No path found
|
403 |
|
|
Maximum output required time after clock: No path found
|
404 |
|
|
Maximum combinational path delay: 0.000ns
|
405 |
|
|
|
406 |
|
|
=========================================================================
|
407 |
|
|
Timing constraint: TS_clk_54e96cfd = PERIOD TIMEGRP "clk_54e96cfd" 5 nS HIGH 2.500 nS
|
408 |
|
|
Clock period: 0.785ns (frequency: 1273.885MHz)
|
409 |
|
|
Total number of paths / destination ports: 1 / 1
|
410 |
|
|
Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
|
411 |
|
|
-------------------------------------------------------------------------
|
412 |
|
|
Slack: 4.215ns
|
413 |
|
|
Source: persistentdff_inst/q (FF)
|
414 |
|
|
Destination: persistentdff_inst/q (FF)
|
415 |
|
|
Data Path Delay: 0.785ns (Levels of Logic = 1)
|
416 |
|
|
Source Clock: to_register9_clk rising at 0.000ns
|
417 |
|
|
Destination Clock: to_register9_clk rising at 5.000ns
|
418 |
|
|
|
419 |
|
|
Data Path: persistentdff_inst/q (FF) to persistentdff_inst/q (FF)
|
420 |
|
|
Gate Net
|
421 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
422 |
|
|
---------------------------------------- ------------
|
423 |
|
|
FD:C->Q 1 0.375 0.399 q (q)
|
424 |
|
|
end scope: 'persistentdff_inst:q'
|
425 |
|
|
begin scope: 'persistentdff_inst:d'
|
426 |
|
|
FD:D 0.011 q
|
427 |
|
|
----------------------------------------
|
428 |
|
|
Total 0.785ns (0.386ns logic, 0.399ns route)
|
429 |
|
|
(49.2% logic, 50.8% route)
|
430 |
|
|
|
431 |
|
|
=========================================================================
|
432 |
|
|
|
433 |
|
|
Cross Clock Domains Report:
|
434 |
|
|
--------------------------
|
435 |
|
|
|
436 |
|
|
Clock to Setup on destination clock to_register9_clk
|
437 |
|
|
----------------+---------+---------+---------+---------+
|
438 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
439 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
440 |
|
|
----------------+---------+---------+---------+---------+
|
441 |
|
|
to_register9_clk| 0.785| | | |
|
442 |
|
|
----------------+---------+---------+---------+---------+
|
443 |
|
|
|
444 |
|
|
=========================================================================
|
445 |
|
|
|
446 |
|
|
|
447 |
|
|
Total REAL time to Xst completion: 12.00 secs
|
448 |
|
|
Total CPU time to Xst completion: 11.78 secs
|
449 |
|
|
|
450 |
|
|
-->
|
451 |
|
|
|
452 |
|
|
Total memory usage is 160616 kilobytes
|
453 |
|
|
|
454 |
|
|
Number of errors : 0 ( 0 filtered)
|
455 |
|
|
Number of warnings : 87 ( 0 filtered)
|
456 |
|
|
Number of infos : 4 ( 0 filtered)
|
457 |
|
|
|