OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [synopsis.2] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
{
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  'attributes' => {
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patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
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patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
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fprintf(\'\',\'COMMENT: end icon graphics\');
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fprintf(\'\',\'COMMENT: begin icon text\');
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fprintf(\'\',\'COMMENT: end icon text\');',
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fprintf(\'\',\'COMMENT: end icon graphics\');
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fprintf(\'\',\'COMMENT: begin icon text\');
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    'constant5_op_net_x4' => {
481 
      'hdlType' => 'std_logic',
482 
      'width' => 1,
483 
    },
484 
    'constant5_op_net_x5' => {
485 
      'hdlType' => 'std_logic',
486 
      'width' => 1,
487 
    },
488 
    'constant5_op_net_x6' => {
489 
      'hdlType' => 'std_logic',
490 
      'width' => 1,
491 
    },
492 
    'constant5_op_net_x7' => {
493 
      'hdlType' => 'std_logic',
494 
      'width' => 1,
495 
    },
496 
    'constant5_op_net_x8' => {
497 
      'hdlType' => 'std_logic',
498 
      'width' => 1,
499 
    },
500 
    'constant5_op_net_x9' => {
501 
      'hdlType' => 'std_logic',
502 
      'width' => 1,
503 
    },
504 
    'debug_in_1i_net' => {
505 
      'hdlType' => 'std_logic_vector(31 downto 0)',
506 
      'width' => 32,
507 
    },
508 
    'debug_in_1i_net_x0' => {
509 
      'hdlType' => 'std_logic_vector(31 downto 0)',
510 
      'width' => 32,
511 
    },
512 
    'debug_in_2i_net' => {
513 
      'hdlType' => 'std_logic_vector(31 downto 0)',
514 
      'width' => 32,
515 
    },
516 
    'debug_in_2i_net_x0' => {
517 
      'hdlType' => 'std_logic_vector(31 downto 0)',
518 
      'width' => 32,
519 
    },
520 
    'debug_in_3i_net' => {
521 
      'hdlType' => 'std_logic_vector(31 downto 0)',
522 
      'width' => 32,
523 
    },
524 
    'debug_in_3i_net_x0' => {
525 
      'hdlType' => 'std_logic_vector(31 downto 0)',
526 
      'width' => 32,
527 
    },
528 
    'debug_in_4i_net' => {
529 
      'hdlType' => 'std_logic_vector(31 downto 0)',
530 
      'width' => 32,
531 
    },
532 
    'debug_in_4i_net_x0' => {
533 
      'hdlType' => 'std_logic_vector(31 downto 0)',
534 
      'width' => 32,
535 
    },
536 
    'dma_host2board_busy_net' => {
537 
      'hdlType' => 'std_logic',
538 
      'width' => 1,
539 
    },
540 
    'dma_host2board_busy_net_x0' => {
541 
      'hdlType' => 'std_logic',
542 
      'width' => 1,
543 
    },
544 
    'dma_host2board_done_net' => {
545 
      'hdlType' => 'std_logic',
546 
      'width' => 1,
547 
    },
548 
    'dma_host2board_done_net_x0' => {
549 
      'hdlType' => 'std_logic',
550 
      'width' => 1,
551 
    },
552 
    'from_register10_data_out_net' => {
553 
      'hdlType' => 'std_logic_vector(31 downto 0)',
554 
      'width' => 32,
555 
    },
556 
    'from_register10_data_out_net_x0' => {
557 
      'hdlType' => 'std_logic_vector(31 downto 0)',
558 
      'width' => 32,
559 
    },
560 
    'from_register11_data_out_net' => {
561 
      'hdlType' => 'std_logic_vector(31 downto 0)',
562 
      'width' => 32,
563 
    },
564 
    'from_register11_data_out_net_x0' => {
565 
      'hdlType' => 'std_logic_vector(31 downto 0)',
566 
      'width' => 32,
567 
    },
568 
    'from_register12_data_out_net' => {
569 
      'hdlType' => 'std_logic',
570 
      'width' => 1,
571 
    },
572 
    'from_register12_data_out_net_x0' => {
573 
      'hdlType' => 'std_logic',
574 
      'width' => 1,
575 
    },
576 
    'from_register13_data_out_net' => {
577 
      'hdlType' => 'std_logic_vector(31 downto 0)',
578 
      'width' => 32,
579 
    },
580 
    'from_register13_data_out_net_x0' => {
581 
      'hdlType' => 'std_logic_vector(31 downto 0)',
582 
      'width' => 32,
583 
    },
584 
    'from_register14_data_out_net' => {
585 
      'hdlType' => 'std_logic',
586 
      'width' => 1,
587 
    },
588 
    'from_register14_data_out_net_x0' => {
589 
      'hdlType' => 'std_logic',
590 
      'width' => 1,
591 
    },
592 
    'from_register15_data_out_net' => {
593 
      'hdlType' => 'std_logic_vector(31 downto 0)',
594 
      'width' => 32,
595 
    },
596 
    'from_register15_data_out_net_x0' => {
597 
      'hdlType' => 'std_logic_vector(31 downto 0)',
598 
      'width' => 32,
599 
    },
600 
    'from_register16_data_out_net' => {
601 
      'hdlType' => 'std_logic',
602 
      'width' => 1,
603 
    },
604 
    'from_register16_data_out_net_x0' => {
605 
      'hdlType' => 'std_logic',
606 
      'width' => 1,
607 
    },
608 
    'from_register17_data_out_net' => {
609 
      'hdlType' => 'std_logic_vector(31 downto 0)',
610 
      'width' => 32,
611 
    },
612 
    'from_register17_data_out_net_x0' => {
613 
      'hdlType' => 'std_logic_vector(31 downto 0)',
614 
      'width' => 32,
615 
    },
616 
    'from_register18_data_out_net' => {
617 
      'hdlType' => 'std_logic',
618 
      'width' => 1,
619 
    },
620 
    'from_register18_data_out_net_x0' => {
621 
      'hdlType' => 'std_logic',
622 
      'width' => 1,
623 
    },
624 
    'from_register19_data_out_net' => {
625 
      'hdlType' => 'std_logic_vector(31 downto 0)',
626 
      'width' => 32,
627 
    },
628 
    'from_register19_data_out_net_x0' => {
629 
      'hdlType' => 'std_logic_vector(31 downto 0)',
630 
      'width' => 32,
631 
    },
632 
    'from_register1_data_out_net' => {
633 
      'hdlType' => 'std_logic',
634 
      'width' => 1,
635 
    },
636 
    'from_register1_data_out_net_x0' => {
637 
      'hdlType' => 'std_logic',
638 
      'width' => 1,
639 
    },
640 
    'from_register20_data_out_net' => {
641 
      'hdlType' => 'std_logic',
642 
      'width' => 1,
643 
    },
644 
    'from_register20_data_out_net_x0' => {
645 
      'hdlType' => 'std_logic',
646 
      'width' => 1,
647 
    },
648 
    'from_register21_data_out_net' => {
649 
      'hdlType' => 'std_logic_vector(31 downto 0)',
650 
      'width' => 32,
651 
    },
652 
    'from_register21_data_out_net_x0' => {
653 
      'hdlType' => 'std_logic_vector(31 downto 0)',
654 
      'width' => 32,
655 
    },
656 
    'from_register22_data_out_net' => {
657 
      'hdlType' => 'std_logic',
658 
      'width' => 1,
659 
    },
660 
    'from_register22_data_out_net_x0' => {
661 
      'hdlType' => 'std_logic',
662 
      'width' => 1,
663 
    },
664 
    'from_register23_data_out_net' => {
665 
      'hdlType' => 'std_logic_vector(31 downto 0)',
666 
      'width' => 32,
667 
    },
668 
    'from_register23_data_out_net_x0' => {
669 
      'hdlType' => 'std_logic_vector(31 downto 0)',
670 
      'width' => 32,
671 
    },
672 
    'from_register24_data_out_net' => {
673 
      'hdlType' => 'std_logic',
674 
      'width' => 1,
675 
    },
676 
    'from_register24_data_out_net_x0' => {
677 
      'hdlType' => 'std_logic',
678 
      'width' => 1,
679 
    },
680 
    'from_register25_data_out_net' => {
681 
      'hdlType' => 'std_logic_vector(31 downto 0)',
682 
      'width' => 32,
683 
    },
684 
    'from_register25_data_out_net_x0' => {
685 
      'hdlType' => 'std_logic_vector(31 downto 0)',
686 
      'width' => 32,
687 
    },
688 
    'from_register26_data_out_net' => {
689 
      'hdlType' => 'std_logic',
690 
      'width' => 1,
691 
    },
692 
    'from_register26_data_out_net_x0' => {
693 
      'hdlType' => 'std_logic',
694 
      'width' => 1,
695 
    },
696 
    'from_register27_data_out_net' => {
697 
      'hdlType' => 'std_logic_vector(31 downto 0)',
698 
      'width' => 32,
699 
    },
700 
    'from_register27_data_out_net_x0' => {
701 
      'hdlType' => 'std_logic_vector(31 downto 0)',
702 
      'width' => 32,
703 
    },
704 
    'from_register28_data_out_net' => {
705 
      'hdlType' => 'std_logic',
706 
      'width' => 1,
707 
    },
708 
    'from_register28_data_out_net_x0' => {
709 
      'hdlType' => 'std_logic',
710 
      'width' => 1,
711 
    },
712 
    'from_register2_data_out_net' => {
713 
      'hdlType' => 'std_logic',
714 
      'width' => 1,
715 
    },
716 
    'from_register2_data_out_net_x0' => {
717 
      'hdlType' => 'std_logic',
718 
      'width' => 1,
719 
    },
720 
    'from_register3_data_out_net' => {
721 
      'hdlType' => 'std_logic_vector(31 downto 0)',
722 
      'width' => 32,
723 
    },
724 
    'from_register3_data_out_net_x0' => {
725 
      'hdlType' => 'std_logic_vector(31 downto 0)',
726 
      'width' => 32,
727 
    },
728 
    'from_register4_data_out_net' => {
729 
      'hdlType' => 'std_logic',
730 
      'width' => 1,
731 
    },
732 
    'from_register4_data_out_net_x0' => {
733 
      'hdlType' => 'std_logic',
734 
      'width' => 1,
735 
    },
736 
    'from_register5_data_out_net' => {
737 
      'hdlType' => 'std_logic_vector(31 downto 0)',
738 
      'width' => 32,
739 
    },
740 
    'from_register5_data_out_net_x0' => {
741 
      'hdlType' => 'std_logic_vector(31 downto 0)',
742 
      'width' => 32,
743 
    },
744 
    'from_register6_data_out_net' => {
745 
      'hdlType' => 'std_logic',
746 
      'width' => 1,
747 
    },
748 
    'from_register6_data_out_net_x0' => {
749 
      'hdlType' => 'std_logic',
750 
      'width' => 1,
751 
    },
752 
    'from_register7_data_out_net' => {
753 
      'hdlType' => 'std_logic_vector(31 downto 0)',
754 
      'width' => 32,
755 
    },
756 
    'from_register7_data_out_net_x0' => {
757 
      'hdlType' => 'std_logic_vector(31 downto 0)',
758 
      'width' => 32,
759 
    },
760 
    'from_register8_data_out_net' => {
761 
      'hdlType' => 'std_logic_vector(31 downto 0)',
762 
      'width' => 32,
763 
    },
764 
    'from_register8_data_out_net_x0' => {
765 
      'hdlType' => 'std_logic_vector(31 downto 0)',
766 
      'width' => 32,
767 
    },
768 
    'from_register9_data_out_net' => {
769 
      'hdlType' => 'std_logic',
770 
      'width' => 1,
771 
    },
772 
    'from_register9_data_out_net_x0' => {
773 
      'hdlType' => 'std_logic',
774 
      'width' => 1,
775 
    },
776 
    'reg01_td_net' => {
777 
      'hdlType' => 'std_logic_vector(31 downto 0)',
778 
      'width' => 32,
779 
    },
780 
    'reg01_td_net_x0' => {
781 
      'hdlType' => 'std_logic_vector(31 downto 0)',
782 
      'width' => 32,
783 
    },
784 
    'reg01_tv_net' => {
785 
      'hdlType' => 'std_logic',
786 
      'width' => 1,
787 
    },
788 
    'reg01_tv_net_x0' => {
789 
      'hdlType' => 'std_logic',
790 
      'width' => 1,
791 
    },
792 
    'reg02_td_net' => {
793 
      'hdlType' => 'std_logic_vector(31 downto 0)',
794 
      'width' => 32,
795 
    },
796 
    'reg02_td_net_x0' => {
797 
      'hdlType' => 'std_logic_vector(31 downto 0)',
798 
      'width' => 32,
799 
    },
800 
    'reg02_tv_net' => {
801 
      'hdlType' => 'std_logic',
802 
      'width' => 1,
803 
    },
804 
    'reg02_tv_net_x0' => {
805 
      'hdlType' => 'std_logic',
806 
      'width' => 1,
807 
    },
808 
    'reg03_td_net' => {
809 
      'hdlType' => 'std_logic_vector(31 downto 0)',
810 
      'width' => 32,
811 
    },
812 
    'reg03_td_net_x0' => {
813 
      'hdlType' => 'std_logic_vector(31 downto 0)',
814 
      'width' => 32,
815 
    },
816 
    'reg03_tv_net' => {
817 
      'hdlType' => 'std_logic',
818 
      'width' => 1,
819 
    },
820 
    'reg03_tv_net_x0' => {
821 
      'hdlType' => 'std_logic',
822 
      'width' => 1,
823 
    },
824 
    'reg04_td_net' => {
825 
      'hdlType' => 'std_logic_vector(31 downto 0)',
826 
      'width' => 32,
827 
    },
828 
    'reg04_td_net_x0' => {
829 
      'hdlType' => 'std_logic_vector(31 downto 0)',
830 
      'width' => 32,
831 
    },
832 
    'reg04_tv_net' => {
833 
      'hdlType' => 'std_logic',
834 
      'width' => 1,
835 
    },
836 
    'reg04_tv_net_x0' => {
837 
      'hdlType' => 'std_logic',
838 
      'width' => 1,
839 
    },
840 
    'reg05_td_net' => {
841 
      'hdlType' => 'std_logic_vector(31 downto 0)',
842 
      'width' => 32,
843 
    },
844 
    'reg05_td_net_x0' => {
845 
      'hdlType' => 'std_logic_vector(31 downto 0)',
846 
      'width' => 32,
847 
    },
848 
    'reg05_tv_net' => {
849 
      'hdlType' => 'std_logic',
850 
      'width' => 1,
851 
    },
852 
    'reg05_tv_net_x0' => {
853 
      'hdlType' => 'std_logic',
854 
      'width' => 1,
855 
    },
856 
    'reg06_td_net' => {
857 
      'hdlType' => 'std_logic_vector(31 downto 0)',
858 
      'width' => 32,
859 
    },
860 
    'reg06_td_net_x0' => {
861 
      'hdlType' => 'std_logic_vector(31 downto 0)',
862 
      'width' => 32,
863 
    },
864 
    'reg06_tv_net' => {
865 
      'hdlType' => 'std_logic',
866 
      'width' => 1,
867 
    },
868 
    'reg06_tv_net_x0' => {
869 
      'hdlType' => 'std_logic',
870 
      'width' => 1,
871 
    },
872 
    'reg07_td_net' => {
873 
      'hdlType' => 'std_logic_vector(31 downto 0)',
874 
      'width' => 32,
875 
    },
876 
    'reg07_td_net_x0' => {
877 
      'hdlType' => 'std_logic_vector(31 downto 0)',
878 
      'width' => 32,
879 
    },
880 
    'reg07_tv_net' => {
881 
      'hdlType' => 'std_logic',
882 
      'width' => 1,
883 
    },
884 
    'reg07_tv_net_x0' => {
885 
      'hdlType' => 'std_logic',
886 
      'width' => 1,
887 
    },
888 
    'reg08_td_net' => {
889 
      'hdlType' => 'std_logic_vector(31 downto 0)',
890 
      'width' => 32,
891 
    },
892 
    'reg08_td_net_x0' => {
893 
      'hdlType' => 'std_logic_vector(31 downto 0)',
894 
      'width' => 32,
895 
    },
896 
    'reg08_tv_net' => {
897 
      'hdlType' => 'std_logic',
898 
      'width' => 1,
899 
    },
900 
    'reg08_tv_net_x0' => {
901 
      'hdlType' => 'std_logic',
902 
      'width' => 1,
903 
    },
904 
    'reg09_td_net' => {
905 
      'hdlType' => 'std_logic_vector(31 downto 0)',
906 
      'width' => 32,
907 
    },
908 
    'reg09_td_net_x0' => {
909 
      'hdlType' => 'std_logic_vector(31 downto 0)',
910 
      'width' => 32,
911 
    },
912 
    'reg09_tv_net' => {
913 
      'hdlType' => 'std_logic',
914 
      'width' => 1,
915 
    },
916 
    'reg09_tv_net_x0' => {
917 
      'hdlType' => 'std_logic',
918 
      'width' => 1,
919 
    },
920 
    'reg10_td_net' => {
921 
      'hdlType' => 'std_logic_vector(31 downto 0)',
922 
      'width' => 32,
923 
    },
924 
    'reg10_td_net_x0' => {
925 
      'hdlType' => 'std_logic_vector(31 downto 0)',
926 
      'width' => 32,
927 
    },
928 
    'reg10_tv_net' => {
929 
      'hdlType' => 'std_logic',
930 
      'width' => 1,
931 
    },
932 
    'reg10_tv_net_x0' => {
933 
      'hdlType' => 'std_logic',
934 
      'width' => 1,
935 
    },
936 
    'reg11_td_net' => {
937 
      'hdlType' => 'std_logic_vector(31 downto 0)',
938 
      'width' => 32,
939 
    },
940 
    'reg11_td_net_x0' => {
941 
      'hdlType' => 'std_logic_vector(31 downto 0)',
942 
      'width' => 32,
943 
    },
944 
    'reg11_tv_net' => {
945 
      'hdlType' => 'std_logic',
946 
      'width' => 1,
947 
    },
948 
    'reg11_tv_net_x0' => {
949 
      'hdlType' => 'std_logic',
950 
      'width' => 1,
951 
    },
952 
    'reg12_td_net' => {
953 
      'hdlType' => 'std_logic_vector(31 downto 0)',
954 
      'width' => 32,
955 
    },
956 
    'reg12_td_net_x0' => {
957 
      'hdlType' => 'std_logic_vector(31 downto 0)',
958 
      'width' => 32,
959 
    },
960 
    'reg12_tv_net' => {
961 
      'hdlType' => 'std_logic',
962 
      'width' => 1,
963 
    },
964 
    'reg12_tv_net_x0' => {
965 
      'hdlType' => 'std_logic',
966 
      'width' => 1,
967 
    },
968 
    'reg13_td_net' => {
969 
      'hdlType' => 'std_logic_vector(31 downto 0)',
970 
      'width' => 32,
971 
    },
972 
    'reg13_td_net_x0' => {
973 
      'hdlType' => 'std_logic_vector(31 downto 0)',
974 
      'width' => 32,
975 
    },
976 
    'reg13_tv_net' => {
977 
      'hdlType' => 'std_logic',
978 
      'width' => 1,
979 
    },
980 
    'reg13_tv_net_x0' => {
981 
      'hdlType' => 'std_logic',
982 
      'width' => 1,
983 
    },
984 
    'reg14_td_net' => {
985 
      'hdlType' => 'std_logic_vector(31 downto 0)',
986 
      'width' => 32,
987 
    },
988 
    'reg14_td_net_x0' => {
989 
      'hdlType' => 'std_logic_vector(31 downto 0)',
990 
      'width' => 32,
991 
    },
992 
    'reg14_tv_net' => {
993 
      'hdlType' => 'std_logic',
994 
      'width' => 1,
995 
    },
996 
    'reg14_tv_net_x0' => {
997 
      'hdlType' => 'std_logic',
998 
      'width' => 1,
999 
    },
1000 
    'to_register10_dout_net' => {
1001 
      'hdlType' => 'std_logic',
1002 
      'width' => 1,
1003 
    },
1004 
    'to_register11_dout_net' => {
1005 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1006 
      'width' => 32,
1007 
    },
1008 
    'to_register12_dout_net' => {
1009 
      'hdlType' => 'std_logic',
1010 
      'width' => 1,
1011 
    },
1012 
    'to_register13_dout_net' => {
1013 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1014 
      'width' => 32,
1015 
    },
1016 
    'to_register14_dout_net' => {
1017 
      'hdlType' => 'std_logic',
1018 
      'width' => 1,
1019 
    },
1020 
    'to_register15_dout_net' => {
1021 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1022 
      'width' => 32,
1023 
    },
1024 
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1025 
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2959 
        'data_in_x2' => 'reg05_tv_net_x0',
2960 
        'data_in_x20' => 'reg12_tv_net_x0',
2961 
        'data_in_x21' => 'reg01_tv_net_x0',
2962 
        'data_in_x22' => 'reg12_td_net_x0',
2963 
        'data_in_x23' => 'reg13_tv_net_x0',
2964 
        'data_in_x24' => 'reg13_td_net_x0',
2965 
        'data_in_x25' => 'reg14_tv_net_x0',
2966 
        'data_in_x26' => 'reg14_td_net_x0',
2967 
        'data_in_x27' => 'reg02_tv_net_x0',
2968 
        'data_in_x28' => 'reg02_td_net_x0',
2969 
        'data_in_x29' => 'debug_in_1i_net_x0',
2970 
        'data_in_x3' => 'reg05_td_net_x0',
2971 
        'data_in_x30' => 'reg01_td_net_x0',
2972 
        'data_in_x31' => 'reg03_tv_net_x0',
2973 
        'data_in_x32' => 'reg03_td_net_x0',
2974 
        'data_in_x4' => 'reg06_tv_net_x0',
2975 
        'data_in_x5' => 'reg06_td_net_x0',
2976 
        'data_in_x6' => 'reg07_tv_net_x0',
2977 
        'data_in_x7' => 'reg07_td_net_x0',
2978 
        'data_in_x8' => 'dma_host2board_busy_net_x0',
2979 
        'data_in_x9' => 'dma_host2board_done_net_x0',
2980 
        'data_out' => 'from_register1_data_out_net',
2981 
        'data_out_x0' => 'from_register10_data_out_net',
2982 
        'data_out_x1' => 'from_register11_data_out_net',
2983 
        'data_out_x10' => 'from_register2_data_out_net',
2984 
        'data_out_x11' => 'from_register20_data_out_net',
2985 
        'data_out_x12' => 'from_register21_data_out_net',
2986 
        'data_out_x13' => 'from_register22_data_out_net',
2987 
        'data_out_x14' => 'from_register23_data_out_net',
2988 
        'data_out_x15' => 'from_register24_data_out_net',
2989 
        'data_out_x16' => 'from_register25_data_out_net',
2990 
        'data_out_x17' => 'from_register26_data_out_net',
2991 
        'data_out_x18' => 'from_register27_data_out_net',
2992 
        'data_out_x19' => 'from_register28_data_out_net',
2993 
        'data_out_x2' => 'from_register12_data_out_net',
2994 
        'data_out_x20' => 'from_register3_data_out_net',
2995 
        'data_out_x21' => 'from_register4_data_out_net',
2996 
        'data_out_x22' => 'from_register5_data_out_net',
2997 
        'data_out_x23' => 'from_register6_data_out_net',
2998 
        'data_out_x24' => 'from_register7_data_out_net',
2999 
        'data_out_x25' => 'from_register8_data_out_net',
3000 
        'data_out_x26' => 'from_register9_data_out_net',
3001 
        'data_out_x3' => 'from_register13_data_out_net',
3002 
        'data_out_x4' => 'from_register14_data_out_net',
3003 
        'data_out_x5' => 'from_register15_data_out_net',
3004 
        'data_out_x6' => 'from_register16_data_out_net',
3005 
        'data_out_x7' => 'from_register17_data_out_net',
3006 
        'data_out_x8' => 'from_register18_data_out_net',
3007 
        'data_out_x9' => 'from_register19_data_out_net',
3008 
        'debug_in_1i' => 'debug_in_1i_net',
3009 
        'debug_in_2i' => 'debug_in_2i_net',
3010 
        'debug_in_3i' => 'debug_in_3i_net',
3011 
        'debug_in_4i' => 'debug_in_4i_net',
3012 
        'dma_host2board_busy' => 'dma_host2board_busy_net',
3013 
        'dma_host2board_done' => 'dma_host2board_done_net',
3014 
        'en' => 'constant5_op_net_x0',
3015 
        'en_x0' => 'constant5_op_net_x1',
3016 
        'en_x1' => 'constant5_op_net_x2',
3017 
        'en_x10' => 'constant5_op_net_x11',
3018 
        'en_x11' => 'constant5_op_net_x12',
3019 
        'en_x12' => 'constant1_op_net_x0',
3020 
        'en_x13' => 'constant1_op_net_x1',
3021 
        'en_x14' => 'constant1_op_net_x2',
3022 
        'en_x15' => 'constant1_op_net_x3',
3023 
        'en_x16' => 'constant1_op_net_x4',
3024 
        'en_x17' => 'constant1_op_net_x5',
3025 
        'en_x18' => 'constant1_op_net_x6',
3026 
        'en_x19' => 'constant1_op_net_x7',
3027 
        'en_x2' => 'constant5_op_net_x3',
3028 
        'en_x20' => 'constant1_op_net_x8',
3029 
        'en_x21' => 'constant5_op_net_x13',
3030 
        'en_x22' => 'constant1_op_net_x9',
3031 
        'en_x23' => 'constant1_op_net_x10',
3032 
        'en_x24' => 'constant1_op_net_x11',
3033 
        'en_x25' => 'constant1_op_net_x12',
3034 
        'en_x26' => 'constant1_op_net_x13',
3035 
        'en_x27' => 'constant5_op_net_x14',
3036 
        'en_x28' => 'constant5_op_net_x15',
3037 
        'en_x29' => 'constant5_op_net_x16',
3038 
        'en_x3' => 'constant5_op_net_x4',
3039 
        'en_x30' => 'constant5_op_net_x17',
3040 
        'en_x31' => 'constant5_op_net_x18',
3041 
        'en_x32' => 'constant5_op_net_x19',
3042 
        'en_x4' => 'constant5_op_net_x5',
3043 
        'en_x5' => 'constant5_op_net_x6',
3044 
        'en_x6' => 'constant5_op_net_x7',
3045 
        'en_x7' => 'constant5_op_net_x8',
3046 
        'en_x8' => 'constant5_op_net_x9',
3047 
        'en_x9' => 'constant5_op_net_x10',
3048 
        'reg01_rd' => 'from_register3_data_out_net_x0',
3049 
        'reg01_rv' => 'from_register1_data_out_net_x0',
3050 
        'reg01_td' => 'reg01_td_net',
3051 
        'reg01_tv' => 'reg01_tv_net',
3052 
        'reg02_rd' => 'from_register5_data_out_net_x0',
3053 
        'reg02_rv' => 'from_register2_data_out_net_x0',
3054 
        'reg02_td' => 'reg02_td_net',
3055 
        'reg02_tv' => 'reg02_tv_net',
3056 
        'reg03_rd' => 'from_register7_data_out_net_x0',
3057 
        'reg03_rv' => 'from_register6_data_out_net_x0',
3058 
        'reg03_td' => 'reg03_td_net',
3059 
        'reg03_tv' => 'reg03_tv_net',
3060 
        'reg04_rd' => 'from_register8_data_out_net_x0',
3061 
        'reg04_rv' => 'from_register4_data_out_net_x0',
3062 
        'reg04_td' => 'reg04_td_net',
3063 
        'reg04_tv' => 'reg04_tv_net',
3064 
        'reg05_rd' => 'from_register10_data_out_net_x0',
3065 
        'reg05_rv' => 'from_register9_data_out_net_x0',
3066 
        'reg05_td' => 'reg05_td_net',
3067 
        'reg05_tv' => 'reg05_tv_net',
3068 
        'reg06_rd' => 'from_register11_data_out_net_x0',
3069 
        'reg06_rv' => 'from_register12_data_out_net_x0',
3070 
        'reg06_td' => 'reg06_td_net',
3071 
        'reg06_tv' => 'reg06_tv_net',
3072 
        'reg07_rd' => 'from_register13_data_out_net_x0',
3073 
        'reg07_rv' => 'from_register14_data_out_net_x0',
3074 
        'reg07_td' => 'reg07_td_net',
3075 
        'reg07_tv' => 'reg07_tv_net',
3076 
        'reg08_rd' => 'from_register15_data_out_net_x0',
3077 
        'reg08_rv' => 'from_register16_data_out_net_x0',
3078 
        'reg08_td' => 'reg08_td_net',
3079 
        'reg08_tv' => 'reg08_tv_net',
3080 
        'reg09_rd' => 'from_register17_data_out_net_x0',
3081 
        'reg09_rv' => 'from_register18_data_out_net_x0',
3082 
        'reg09_td' => 'reg09_td_net',
3083 
        'reg09_tv' => 'reg09_tv_net',
3084 
        'reg10_rd' => 'from_register19_data_out_net_x0',
3085 
        'reg10_rv' => 'from_register20_data_out_net_x0',
3086 
        'reg10_td' => 'reg10_td_net',
3087 
        'reg10_tv' => 'reg10_tv_net',
3088 
        'reg11_rd' => 'from_register21_data_out_net_x0',
3089 
        'reg11_rv' => 'from_register22_data_out_net_x0',
3090 
        'reg11_td' => 'reg11_td_net',
3091 
        'reg11_tv' => 'reg11_tv_net',
3092 
        'reg12_rd' => 'from_register23_data_out_net_x0',
3093 
        'reg12_rv' => 'from_register24_data_out_net_x0',
3094 
        'reg12_td' => 'reg12_td_net',
3095 
        'reg12_tv' => 'reg12_tv_net',
3096 
        'reg13_rd' => 'from_register25_data_out_net_x0',
3097 
        'reg13_rv' => 'from_register26_data_out_net_x0',
3098 
        'reg13_td' => 'reg13_td_net',
3099 
        'reg13_tv' => 'reg13_tv_net',
3100 
        'reg14_rd' => 'from_register27_data_out_net_x0',
3101 
        'reg14_rv' => 'from_register28_data_out_net_x0',
3102 
        'reg14_td' => 'reg14_td_net',
3103 
        'reg14_tv' => 'reg14_tv_net',
3104 
      },
3105 
      'entity' => {
3106 
        'attributes' => {
3107 
          'entityAlreadyNetlisted' => 1,
3108 
          'hdlKind' => 'vhdl',
3109 
          'isDesign' => 1,
3110 
          'simulinkName' => 'INOUT_LOGIC',
3111 
        },
3112 
        'entityName' => 'inout_logic',
3113 
        'ports' => {
3114 
          'data_in' => {
3115 
            'attributes' => {
3116 
              'bin_pt' => 0,
3117 
              'is_floating_block' => 1,
3118 
              'must_be_hdl_vector' => 1,
3119 
              'period' => 1,
3120 
              'port_id' => 0,
3121 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3122 
              'type' => 'UFix_32_0',
3123 
            },
3124 
            'direction' => 'out',
3125 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3126 
            'width' => 32,
3127 
          },
3128 
          'data_in_x0' => {
3129 
            'attributes' => {
3130 
              'bin_pt' => 0,
3131 
              'is_floating_block' => 1,
3132 
              'must_be_hdl_vector' => 1,
3133 
              'period' => 1,
3134 
              'port_id' => 0,
3135 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3136 
              'type' => 'Bool',
3137 
            },
3138 
            'direction' => 'out',
3139 
            'hdlType' => 'std_logic',
3140 
            'width' => 1,
3141 
          },
3142 
          'data_in_x1' => {
3143 
            'attributes' => {
3144 
              'bin_pt' => 0,
3145 
              'is_floating_block' => 1,
3146 
              'must_be_hdl_vector' => 1,
3147 
              'period' => 1,
3148 
              'port_id' => 0,
3149 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3150 
              'type' => 'UFix_32_0',
3151 
            },
3152 
            'direction' => 'out',
3153 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3154 
            'width' => 32,
3155 
          },
3156 
          'data_in_x10' => {
3157 
            'attributes' => {
3158 
              'bin_pt' => 0,
3159 
              'is_floating_block' => 1,
3160 
              'must_be_hdl_vector' => 1,
3161 
              'period' => 1,
3162 
              'port_id' => 0,
3163 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3164 
              'type' => 'UFix_32_0',
3165 
            },
3166 
            'direction' => 'out',
3167 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3168 
            'width' => 32,
3169 
          },
3170 
          'data_in_x11' => {
3171 
            'attributes' => {
3172 
              'bin_pt' => 0,
3173 
              'is_floating_block' => 1,
3174 
              'must_be_hdl_vector' => 1,
3175 
              'period' => 1,
3176 
              'port_id' => 0,
3177 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3178 
              'type' => 'UFix_32_0',
3179 
            },
3180 
            'direction' => 'out',
3181 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3182 
            'width' => 32,
3183 
          },
3184 
          'data_in_x12' => {
3185 
            'attributes' => {
3186 
              'bin_pt' => 0,
3187 
              'is_floating_block' => 1,
3188 
              'must_be_hdl_vector' => 1,
3189 
              'period' => 1,
3190 
              'port_id' => 0,
3191 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3192 
              'type' => 'Bool',
3193 
            },
3194 
            'direction' => 'out',
3195 
            'hdlType' => 'std_logic',
3196 
            'width' => 1,
3197 
          },
3198 
          'data_in_x13' => {
3199 
            'attributes' => {
3200 
              'bin_pt' => 0,
3201 
              'is_floating_block' => 1,
3202 
              'must_be_hdl_vector' => 1,
3203 
              'period' => 1,
3204 
              'port_id' => 0,
3205 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3206 
              'type' => 'UFix_32_0',
3207 
            },
3208 
            'direction' => 'out',
3209 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3210 
            'width' => 32,
3211 
          },
3212 
          'data_in_x14' => {
3213 
            'attributes' => {
3214 
              'bin_pt' => 0,
3215 
              'is_floating_block' => 1,
3216 
              'must_be_hdl_vector' => 1,
3217 
              'period' => 1,
3218 
              'port_id' => 0,
3219 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3220 
              'type' => 'Bool',
3221 
            },
3222 
            'direction' => 'out',
3223 
            'hdlType' => 'std_logic',
3224 
            'width' => 1,
3225 
          },
3226 
          'data_in_x15' => {
3227 
            'attributes' => {
3228 
              'bin_pt' => 0,
3229 
              'is_floating_block' => 1,
3230 
              'must_be_hdl_vector' => 1,
3231 
              'period' => 1,
3232 
              'port_id' => 0,
3233 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3234 
              'type' => 'UFix_32_0',
3235 
            },
3236 
            'direction' => 'out',
3237 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3238 
            'width' => 32,
3239 
          },
3240 
          'data_in_x16' => {
3241 
            'attributes' => {
3242 
              'bin_pt' => 0,
3243 
              'is_floating_block' => 1,
3244 
              'must_be_hdl_vector' => 1,
3245 
              'period' => 1,
3246 
              'port_id' => 0,
3247 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3248 
              'type' => 'Bool',
3249 
            },
3250 
            'direction' => 'out',
3251 
            'hdlType' => 'std_logic',
3252 
            'width' => 1,
3253 
          },
3254 
          'data_in_x17' => {
3255 
            'attributes' => {
3256 
              'bin_pt' => 0,
3257 
              'is_floating_block' => 1,
3258 
              'must_be_hdl_vector' => 1,
3259 
              'period' => 1,
3260 
              'port_id' => 0,
3261 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3262 
              'type' => 'UFix_32_0',
3263 
            },
3264 
            'direction' => 'out',
3265 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3266 
            'width' => 32,
3267 
          },
3268 
          'data_in_x18' => {
3269 
            'attributes' => {
3270 
              'bin_pt' => 0,
3271 
              'is_floating_block' => 1,
3272 
              'must_be_hdl_vector' => 1,
3273 
              'period' => 1,
3274 
              'port_id' => 0,
3275 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3276 
              'type' => 'Bool',
3277 
            },
3278 
            'direction' => 'out',
3279 
            'hdlType' => 'std_logic',
3280 
            'width' => 1,
3281 
          },
3282 
          'data_in_x19' => {
3283 
            'attributes' => {
3284 
              'bin_pt' => 0,
3285 
              'is_floating_block' => 1,
3286 
              'must_be_hdl_vector' => 1,
3287 
              'period' => 1,
3288 
              'port_id' => 0,
3289 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3290 
              'type' => 'UFix_32_0',
3291 
            },
3292 
            'direction' => 'out',
3293 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3294 
            'width' => 32,
3295 
          },
3296 
          'data_in_x2' => {
3297 
            'attributes' => {
3298 
              'bin_pt' => 0,
3299 
              'is_floating_block' => 1,
3300 
              'must_be_hdl_vector' => 1,
3301 
              'period' => 1,
3302 
              'port_id' => 0,
3303 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3304 
              'type' => 'Bool',
3305 
            },
3306 
            'direction' => 'out',
3307 
            'hdlType' => 'std_logic',
3308 
            'width' => 1,
3309 
          },
3310 
          'data_in_x20' => {
3311 
            'attributes' => {
3312 
              'bin_pt' => 0,
3313 
              'is_floating_block' => 1,
3314 
              'must_be_hdl_vector' => 1,
3315 
              'period' => 1,
3316 
              'port_id' => 0,
3317 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3318 
              'type' => 'Bool',
3319 
            },
3320 
            'direction' => 'out',
3321 
            'hdlType' => 'std_logic',
3322 
            'width' => 1,
3323 
          },
3324 
          'data_in_x21' => {
3325 
            'attributes' => {
3326 
              'bin_pt' => 0,
3327 
              'is_floating_block' => 1,
3328 
              'must_be_hdl_vector' => 1,
3329 
              'period' => 1,
3330 
              'port_id' => 0,
3331 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3332 
              'type' => 'Bool',
3333 
            },
3334 
            'direction' => 'out',
3335 
            'hdlType' => 'std_logic',
3336 
            'width' => 1,
3337 
          },
3338 
          'data_in_x22' => {
3339 
            'attributes' => {
3340 
              'bin_pt' => 0,
3341 
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3342 
              'must_be_hdl_vector' => 1,
3343 
              'period' => 1,
3344 
              'port_id' => 0,
3345 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3346 
              'type' => 'UFix_32_0',
3347 
            },
3348 
            'direction' => 'out',
3349 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3350 
            'width' => 32,
3351 
          },
3352 
          'data_in_x23' => {
3353 
            'attributes' => {
3354 
              'bin_pt' => 0,
3355 
              'is_floating_block' => 1,
3356 
              'must_be_hdl_vector' => 1,
3357 
              'period' => 1,
3358 
              'port_id' => 0,
3359 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3360 
              'type' => 'Bool',
3361 
            },
3362 
            'direction' => 'out',
3363 
            'hdlType' => 'std_logic',
3364 
            'width' => 1,
3365 
          },
3366 
          'data_in_x24' => {
3367 
            'attributes' => {
3368 
              'bin_pt' => 0,
3369 
              'is_floating_block' => 1,
3370 
              'must_be_hdl_vector' => 1,
3371 
              'period' => 1,
3372 
              'port_id' => 0,
3373 
              'simulinkName' => 'INOUT_LOGIC/data_in',
3374 
              'type' => 'UFix_32_0',
3375 
            },
3376 
            'direction' => 'out',
3377 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3378 
            'width' => 32,
3379 
          },
3380 
          'data_in_x25' => {
3381 
            'attributes' => {
3382 
              'bin_pt' => 0,
3383 
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3384 
              'must_be_hdl_vector' => 1,
3385 
              'period' => 1,
3386 
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11656 
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11657 
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11658 
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11659 
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11660 
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11661 
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11662 
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11663 
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11664 
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11665 
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11666 
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11667 
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11668 
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11669 
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11670 
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11671 
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11672 
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11673 
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11674 
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11675 
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11676 
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11677 
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11678 
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11679 
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11680 
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11681 
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11682 
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11683 
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11684 
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11685 
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11686 
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11687 
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11688 
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11689 
            'shared_memory_name' => 'register03tv',
11690 
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11691 
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11692 
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11693 
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11694 
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11695 
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11696 
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11697 
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11698 
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11699 
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11700 
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11701 
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11702 
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11703 
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11704 
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11705 
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11706 
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11707 
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11708 
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11709 
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11710 
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11711 
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11712 
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11713 
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11714 
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11715 
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11716 
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11717 
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11718 
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11719 
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11720 
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11721 
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11722 
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11723 
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11724 
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11725 
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11726 
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11727 
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11728 
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11729 
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11730 
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11731 
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11732 
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11733 
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11734 
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11735 
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11736 
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11737 
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11738 
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11739 
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11740 
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11741 
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11742 
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11743 
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11744 
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11745 
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11746 
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11747 
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11748 
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11749 
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11750 
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11751 
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11752 
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11753 
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11754 
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11755 
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11756 
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11757 
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11758 
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11759 
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11760 
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11761 
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11762 
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11763 
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11764 
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11765 
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11766 
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11767 
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11768 
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11769 
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11770 
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11771 
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11772 
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11773 
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11774 
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11775 
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11776 
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11777 
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11778 
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11779 
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11780 
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11781 
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11782 
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11783 
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11784 
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11785 
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11786 
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11787 
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11788 
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11789 
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11790 
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11791 
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11792 
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11793 
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11794 
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11795 
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11796 
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11797 
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11798 
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11799 
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11800 
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11801 
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11803 
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11804 
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11805 
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11806 
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11807 
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11808 
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11809 
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11810 
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11811 
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11812 
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11813 
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11814 
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11815 
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11816 
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11817 
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11818 
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11819 
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11820 
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11821 
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11822 
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11823 
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11824 
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11825 
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11826 
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11827 
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11828 
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11829 
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11830 
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11831 
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11832 
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11833 
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11834 
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11835 
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11836 
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11837 
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11838 
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11839 
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11840 
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11841 
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11842 
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11843 
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11844 
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11845 
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11846 
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11847 
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11848 
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11849 
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11850 
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11851 
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11852 
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11853 
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11854 
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11855 
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11856 
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11857 
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11859 
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11860 
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11861 
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11864 
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11865 
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11866 
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11867 
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11868 
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11869 
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11870 
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11871 
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11875 
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11876 
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11877 
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11878 
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11879 
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11880 
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11881 
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11882 
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11883 
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11884 
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11885 
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11887 
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11888 
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11889 
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11890 
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11892 
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11893 
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11894 
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11895 
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11898 
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11899 
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11900 
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11901 
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11903 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11904 
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11905 
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11906 
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11907 
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11908 
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11909 
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11910 
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11911 
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11912 
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11913 
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11914 
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11915 
}

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