OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_0_PCIe_UserLogic_00_INOUT_LOGIC/] [sysgen/] [synopsis_com.xilinx.sysgen.netlister.CfWriter] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
{
2 
  'attributes' => {
3 
    'HDLCodeGenStatus' => 0,
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    'HDL_PATH' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
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    'Impl_file' => 'ISE Defaults',
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    'Impl_file_sgadvanced' => '',
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    'Synth_file' => 'XST Defaults',
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    'Synth_file_sgadvanced' => '',
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    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
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    'TMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
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    'Temp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
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    'Tmp' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
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    'base_system_period_hardware' => 5,
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    'base_system_period_simulink' => '8e-009',
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    'block_icon_display' => 'Default',
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    'block_type' => 'sysgen',
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    'block_version' => '',
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    'ce_clr' => 0,
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    'clkWrapper' => 'inout_logic_cw',
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    'clkWrapperFile' => 'inout_logic_cw.vhd',
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    'clock_loc' => '',
22 
    'clock_wrapper' => 'Clock Enables',
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    'clock_wrapper_sgadvanced' => '',
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    'compilation' => 'NGC Netlist',
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    'compilation_lut' => {
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      'keys' => [
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        'HDL Netlist',
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        'Bitstream',
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      ],
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      'values' => [
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        'target1',
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        'target2',
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        'target3',
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      ],
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    },
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    'compilation_target' => 'NGC Netlist',
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    'core_generation' => 1,
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    'core_generation_sgadvanced' => '',
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    'core_is_deployed' => 0,
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    'coregen_core_generation_tmpdir' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root/cg_wk/c46e83d2645affbd5',
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    'coregen_part_family' => 'virtex6',
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    'createTestbench' => 0,
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    'create_interface_document' => 'off',
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    'dbl_ovrd' => -1,
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    'dbl_ovrd_sgadvanced' => '',
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    'dcm_info' => {},
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    'dcm_input_clock_period' => 5,
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    'deprecated_control' => 'off',
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    'deprecated_control_sgadvanced' => '',
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    'design' => 'inout_logic',
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    'designFile' => 'inout_logic.vhd',
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    'design_full_path' => 'C:\\Temp\\Xilinx PCI Express\\ML605_ISE13.3\\MySysGen\\PCIe_UserLogic_00.mdl',
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    'device_speed' => -1,
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    'directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
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    'dsp_cache_root_path' => 'C:/DOCUME~1/root/IMPOST~1/Temp/sysgentmp-root',
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    'entityNamingInstrs' => {
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      'namesAlreadyUsed' => {
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        'default_clock_driver' => 1,
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        'inout_logic_cw' => 1,
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      },
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    },
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      'nonleaf_results.vhd' => { 'producer' => 'nonleafNetlister', },
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    },
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      'xlpersistentdff.ngc',
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      'synopsis',
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      'inout_logic.vhd',
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      'xlpersistentdff.ngc',
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      'inout_logic_cw.vhd',
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      'inout_logic_cw.ucf',
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      'inout_logic_cw.xcf',
77 
      'inout_logic_cw.sdc',
78 
    ],
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    'fxdptinstalled' => 1,
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    'generateUsing71FrontEnd' => 1,
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    'generating_subsystem_handle' => 2084.00048828125,
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    'generation_directory' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MyUserLogic/UserLogic_00/top_level_0_PCIe_UserLogic_00_INOUT_LOGIC',
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    'has_advanced_control' => 0,
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    'hdlDir' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE/sysgen/hdl',
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    'hdlKind' => 'vhdl',
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    'hdl_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen',
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    'impl_file' => 'ISE Defaults*',
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    'infoedit' => ' System Generator',
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    'isCombinatorial' => 1,
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    'isdeployed' => 0,
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    'ise_version' => '13.3i',
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    'master_sysgen_token_handle' => 2085.00048828125,
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    'matlab' => 'C:/Programmi/MATLAB/R2010b',
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    'matlab_fixedpoint' => 1,
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    'mdlHandle' => 2083.00048828125,
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    'mdlPath' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
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    'modelDiagnostics' => [
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        'isMask' => 0,
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        'type' => 'PCIe_UserLogic_00 Total blocks',
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        'count' => 44,
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        'isMask' => 1,
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        'count' => 39,
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        'isMask' => 1,
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        'type' => 'Xilinx Inverter Block',
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        'type' => 'Xilinx Shared Memory Based From Register Block',
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        'count' => 62,
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        'isMask' => 1,
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        'type' => 'Xilinx Shared Memory Based To Register Block',
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      {
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        'count' => 1,
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        'isMask' => 1,
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        'type' => 'Xilinx Subsystem Generator Block',
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      },
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      {
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        'count' => 2,
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        'isMask' => 1,
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        'type' => 'Xilinx System Generator Block',
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      },
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        'count' => 14,
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        'isMask' => 1,
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        'type' => 'Xilinx Type Converter Block',
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    ],
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    'model_globals_initialized' => 1,
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    'model_path' => 'C:/Temp/Xilinx PCI Express/ML605_ISE13.3/MySysGen/PCIe_UserLogic_00.mdl',
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    'myxilinx' => 'C:/Programmi/Xilinx/13.3/ISE_DS/ISE',
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    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
196 
    'ngc_config' => {
197 
      'include_cf' => 1,
198 
      'include_clockwrapper' => 1,
199 
    },
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    'ngc_files' => [ 'xlpersistentdff.ngc', ],
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    'num_sim_cycles' => 1250000000,
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    'package' => 'ff1156',
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    'part' => 'xc6vlx240t',
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    'partFamily' => 'virtex6',
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    'port_data_types_enabled' => 1,
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    'preserve_hierarchy' => 0,
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    'proj_type' => 'Project Navigator',
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    'run_coregen' => 'off',
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    'run_coregen_sgadvanced' => '',
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    'sample_time_colors_enabled' => 1,
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    'sampletimecolors' => 1,
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    'sdcFile' => 'inout_logic_cw.sdc',
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    'sg_icon_stat' => '50,50,-1,-1,token,white,0,07734,right,,[ ],[ ]',
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    'sg_list_contents' => '',
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    'sg_mask_display' => 'fprintf(\'\',\'COMMENT: begin icon graphics\');
220 
patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
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patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
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patch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 36.655 26.155 ],[0.698039 0.0313725 0.219608 ]);
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patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
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patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
225 
fprintf(\'\',\'COMMENT: end icon graphics\');
226 
fprintf(\'\',\'COMMENT: begin icon text\');
227 
fprintf(\'\',\'COMMENT: end icon text\');',
228 
    'sg_version' => '',
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    'simulinkName' => 'parking_lot',
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    'simulink_accelerator_running' => 0,
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    'simulink_debugger_running' => 0,
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      'Synth_file' => 'XST Defaults',
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      'Synth_file_sgadvanced' => '',
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      'base_system_period_hardware' => 5,
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patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
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patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
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patch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.155 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);
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patch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.155 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);
310 
fprintf(\'\',\'COMMENT: end icon graphics\');
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fprintf(\'\',\'COMMENT: begin icon text\');
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fprintf(\'\',\'COMMENT: end icon text\');',
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      'sggui_pos' => '-1,-1,-1,-1',
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      'xilinx_device' => 'xc6vlx240t-1ff1156',
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473 
      'hdlType' => 'std_logic',
474 
      'width' => 1,
475 
    },
476 
    '.reg11_td' => {
477 
      'hdlType' => 'std_logic_vector(31 downto 0)',
478 
      'width' => 32,
479 
    },
480 
    '.reg11_tv' => {
481 
      'hdlType' => 'std_logic',
482 
      'width' => 1,
483 
    },
484 
    '.reg12_td' => {
485 
      'hdlType' => 'std_logic_vector(31 downto 0)',
486 
      'width' => 32,
487 
    },
488 
    '.reg12_tv' => {
489 
      'hdlType' => 'std_logic',
490 
      'width' => 1,
491 
    },
492 
    '.reg13_td' => {
493 
      'hdlType' => 'std_logic_vector(31 downto 0)',
494 
      'width' => 32,
495 
    },
496 
    '.reg13_tv' => {
497 
      'hdlType' => 'std_logic',
498 
      'width' => 1,
499 
    },
500 
    '.reg14_td' => {
501 
      'hdlType' => 'std_logic_vector(31 downto 0)',
502 
      'width' => 32,
503 
    },
504 
    '.reg14_tv' => {
505 
      'hdlType' => 'std_logic',
506 
      'width' => 1,
507 
    },
508 
    'from_register1.data_out' => {
509 
      'hdlType' => 'std_logic',
510 
      'width' => 1,
511 
    },
512 
    'from_register10.data_out' => {
513 
      'hdlType' => 'std_logic_vector(31 downto 0)',
514 
      'width' => 32,
515 
    },
516 
    'from_register11.data_out' => {
517 
      'hdlType' => 'std_logic_vector(31 downto 0)',
518 
      'width' => 32,
519 
    },
520 
    'from_register12.data_out' => {
521 
      'hdlType' => 'std_logic',
522 
      'width' => 1,
523 
    },
524 
    'from_register13.data_out' => {
525 
      'hdlType' => 'std_logic_vector(31 downto 0)',
526 
      'width' => 32,
527 
    },
528 
    'from_register14.data_out' => {
529 
      'hdlType' => 'std_logic',
530 
      'width' => 1,
531 
    },
532 
    'from_register15.data_out' => {
533 
      'hdlType' => 'std_logic_vector(31 downto 0)',
534 
      'width' => 32,
535 
    },
536 
    'from_register16.data_out' => {
537 
      'hdlType' => 'std_logic',
538 
      'width' => 1,
539 
    },
540 
    'from_register17.data_out' => {
541 
      'hdlType' => 'std_logic_vector(31 downto 0)',
542 
      'width' => 32,
543 
    },
544 
    'from_register18.data_out' => {
545 
      'hdlType' => 'std_logic',
546 
      'width' => 1,
547 
    },
548 
    'from_register19.data_out' => {
549 
      'hdlType' => 'std_logic_vector(31 downto 0)',
550 
      'width' => 32,
551 
    },
552 
    'from_register2.data_out' => {
553 
      'hdlType' => 'std_logic',
554 
      'width' => 1,
555 
    },
556 
    'from_register20.data_out' => {
557 
      'hdlType' => 'std_logic',
558 
      'width' => 1,
559 
    },
560 
    'from_register21.data_out' => {
561 
      'hdlType' => 'std_logic_vector(31 downto 0)',
562 
      'width' => 32,
563 
    },
564 
    'from_register22.data_out' => {
565 
      'hdlType' => 'std_logic',
566 
      'width' => 1,
567 
    },
568 
    'from_register23.data_out' => {
569 
      'hdlType' => 'std_logic_vector(31 downto 0)',
570 
      'width' => 32,
571 
    },
572 
    'from_register24.data_out' => {
573 
      'hdlType' => 'std_logic',
574 
      'width' => 1,
575 
    },
576 
    'from_register25.data_out' => {
577 
      'hdlType' => 'std_logic_vector(31 downto 0)',
578 
      'width' => 32,
579 
    },
580 
    'from_register26.data_out' => {
581 
      'hdlType' => 'std_logic',
582 
      'width' => 1,
583 
    },
584 
    'from_register27.data_out' => {
585 
      'hdlType' => 'std_logic_vector(31 downto 0)',
586 
      'width' => 32,
587 
    },
588 
    'from_register28.data_out' => {
589 
      'hdlType' => 'std_logic',
590 
      'width' => 1,
591 
    },
592 
    'from_register3.data_out' => {
593 
      'hdlType' => 'std_logic_vector(31 downto 0)',
594 
      'width' => 32,
595 
    },
596 
    'from_register4.data_out' => {
597 
      'hdlType' => 'std_logic',
598 
      'width' => 1,
599 
    },
600 
    'from_register5.data_out' => {
601 
      'hdlType' => 'std_logic_vector(31 downto 0)',
602 
      'width' => 32,
603 
    },
604 
    'from_register6.data_out' => {
605 
      'hdlType' => 'std_logic',
606 
      'width' => 1,
607 
    },
608 
    'from_register7.data_out' => {
609 
      'hdlType' => 'std_logic_vector(31 downto 0)',
610 
      'width' => 32,
611 
    },
612 
    'from_register8.data_out' => {
613 
      'hdlType' => 'std_logic_vector(31 downto 0)',
614 
      'width' => 32,
615 
    },
616 
    'from_register9.data_out' => {
617 
      'hdlType' => 'std_logic',
618 
      'width' => 1,
619 
    },
620 
    'sysgen_dut.reg01_rd' => {
621 
      'hdlType' => 'std_logic_vector(31 downto 0)',
622 
      'width' => 32,
623 
    },
624 
    'sysgen_dut.reg01_rv' => {
625 
      'hdlType' => 'std_logic',
626 
      'width' => 1,
627 
    },
628 
    'sysgen_dut.reg02_rd' => {
629 
      'hdlType' => 'std_logic_vector(31 downto 0)',
630 
      'width' => 32,
631 
    },
632 
    'sysgen_dut.reg02_rv' => {
633 
      'hdlType' => 'std_logic',
634 
      'width' => 1,
635 
    },
636 
    'sysgen_dut.reg03_rd' => {
637 
      'hdlType' => 'std_logic_vector(31 downto 0)',
638 
      'width' => 32,
639 
    },
640 
    'sysgen_dut.reg03_rv' => {
641 
      'hdlType' => 'std_logic',
642 
      'width' => 1,
643 
    },
644 
    'sysgen_dut.reg04_rd' => {
645 
      'hdlType' => 'std_logic_vector(31 downto 0)',
646 
      'width' => 32,
647 
    },
648 
    'sysgen_dut.reg04_rv' => {
649 
      'hdlType' => 'std_logic',
650 
      'width' => 1,
651 
    },
652 
    'sysgen_dut.reg05_rd' => {
653 
      'hdlType' => 'std_logic_vector(31 downto 0)',
654 
      'width' => 32,
655 
    },
656 
    'sysgen_dut.reg05_rv' => {
657 
      'hdlType' => 'std_logic',
658 
      'width' => 1,
659 
    },
660 
    'sysgen_dut.reg06_rd' => {
661 
      'hdlType' => 'std_logic_vector(31 downto 0)',
662 
      'width' => 32,
663 
    },
664 
    'sysgen_dut.reg06_rv' => {
665 
      'hdlType' => 'std_logic',
666 
      'width' => 1,
667 
    },
668 
    'sysgen_dut.reg07_rd' => {
669 
      'hdlType' => 'std_logic_vector(31 downto 0)',
670 
      'width' => 32,
671 
    },
672 
    'sysgen_dut.reg07_rv' => {
673 
      'hdlType' => 'std_logic',
674 
      'width' => 1,
675 
    },
676 
    'sysgen_dut.reg08_rd' => {
677 
      'hdlType' => 'std_logic_vector(31 downto 0)',
678 
      'width' => 32,
679 
    },
680 
    'sysgen_dut.reg08_rv' => {
681 
      'hdlType' => 'std_logic',
682 
      'width' => 1,
683 
    },
684 
    'sysgen_dut.reg09_rd' => {
685 
      'hdlType' => 'std_logic_vector(31 downto 0)',
686 
      'width' => 32,
687 
    },
688 
    'sysgen_dut.reg09_rv' => {
689 
      'hdlType' => 'std_logic',
690 
      'width' => 1,
691 
    },
692 
    'sysgen_dut.reg10_rd' => {
693 
      'hdlType' => 'std_logic_vector(31 downto 0)',
694 
      'width' => 32,
695 
    },
696 
    'sysgen_dut.reg10_rv' => {
697 
      'hdlType' => 'std_logic',
698 
      'width' => 1,
699 
    },
700 
    'sysgen_dut.reg11_rd' => {
701 
      'hdlType' => 'std_logic_vector(31 downto 0)',
702 
      'width' => 32,
703 
    },
704 
    'sysgen_dut.reg11_rv' => {
705 
      'hdlType' => 'std_logic',
706 
      'width' => 1,
707 
    },
708 
    'sysgen_dut.reg12_rd' => {
709 
      'hdlType' => 'std_logic_vector(31 downto 0)',
710 
      'width' => 32,
711 
    },
712 
    'sysgen_dut.reg12_rv' => {
713 
      'hdlType' => 'std_logic',
714 
      'width' => 1,
715 
    },
716 
    'sysgen_dut.reg13_rd' => {
717 
      'hdlType' => 'std_logic_vector(31 downto 0)',
718 
      'width' => 32,
719 
    },
720 
    'sysgen_dut.reg13_rv' => {
721 
      'hdlType' => 'std_logic',
722 
      'width' => 1,
723 
    },
724 
    'sysgen_dut.reg14_rd' => {
725 
      'hdlType' => 'std_logic_vector(31 downto 0)',
726 
      'width' => 32,
727 
    },
728 
    'sysgen_dut.reg14_rv' => {
729 
      'hdlType' => 'std_logic',
730 
      'width' => 1,
731 
    },
732 
    'sysgen_dut.to_register10_ce' => {
733 
      'hdlType' => 'std_logic',
734 
      'width' => 1,
735 
    },
736 
    'sysgen_dut.to_register10_clk' => {
737 
      'hdlType' => 'std_logic',
738 
      'width' => 1,
739 
    },
740 
    'sysgen_dut.to_register10_clr' => {
741 
      'hdlType' => 'std_logic',
742 
      'width' => 1,
743 
    },
744 
    'sysgen_dut.to_register10_data_in' => {
745 
      'hdlType' => 'std_logic',
746 
      'width' => 1,
747 
    },
748 
    'sysgen_dut.to_register10_en' => {
749 
      'hdlType' => 'std_logic',
750 
      'width' => 1,
751 
    },
752 
    'sysgen_dut.to_register11_ce' => {
753 
      'hdlType' => 'std_logic',
754 
      'width' => 1,
755 
    },
756 
    'sysgen_dut.to_register11_clk' => {
757 
      'hdlType' => 'std_logic',
758 
      'width' => 1,
759 
    },
760 
    'sysgen_dut.to_register11_clr' => {
761 
      'hdlType' => 'std_logic',
762 
      'width' => 1,
763 
    },
764 
    'sysgen_dut.to_register11_data_in' => {
765 
      'hdlType' => 'std_logic_vector(31 downto 0)',
766 
      'width' => 32,
767 
    },
768 
    'sysgen_dut.to_register11_en' => {
769 
      'hdlType' => 'std_logic',
770 
      'width' => 1,
771 
    },
772 
    'sysgen_dut.to_register12_ce' => {
773 
      'hdlType' => 'std_logic',
774 
      'width' => 1,
775 
    },
776 
    'sysgen_dut.to_register12_clk' => {
777 
      'hdlType' => 'std_logic',
778 
      'width' => 1,
779 
    },
780 
    'sysgen_dut.to_register12_clr' => {
781 
      'hdlType' => 'std_logic',
782 
      'width' => 1,
783 
    },
784 
    'sysgen_dut.to_register12_data_in' => {
785 
      'hdlType' => 'std_logic',
786 
      'width' => 1,
787 
    },
788 
    'sysgen_dut.to_register12_en' => {
789 
      'hdlType' => 'std_logic',
790 
      'width' => 1,
791 
    },
792 
    'sysgen_dut.to_register13_ce' => {
793 
      'hdlType' => 'std_logic',
794 
      'width' => 1,
795 
    },
796 
    'sysgen_dut.to_register13_clk' => {
797 
      'hdlType' => 'std_logic',
798 
      'width' => 1,
799 
    },
800 
    'sysgen_dut.to_register13_clr' => {
801 
      'hdlType' => 'std_logic',
802 
      'width' => 1,
803 
    },
804 
    'sysgen_dut.to_register13_data_in' => {
805 
      'hdlType' => 'std_logic_vector(31 downto 0)',
806 
      'width' => 32,
807 
    },
808 
    'sysgen_dut.to_register13_en' => {
809 
      'hdlType' => 'std_logic',
810 
      'width' => 1,
811 
    },
812 
    'sysgen_dut.to_register14_ce' => {
813 
      'hdlType' => 'std_logic',
814 
      'width' => 1,
815 
    },
816 
    'sysgen_dut.to_register14_clk' => {
817 
      'hdlType' => 'std_logic',
818 
      'width' => 1,
819 
    },
820 
    'sysgen_dut.to_register14_clr' => {
821 
      'hdlType' => 'std_logic',
822 
      'width' => 1,
823 
    },
824 
    'sysgen_dut.to_register14_data_in' => {
825 
      'hdlType' => 'std_logic',
826 
      'width' => 1,
827 
    },
828 
    'sysgen_dut.to_register14_en' => {
829 
      'hdlType' => 'std_logic',
830 
      'width' => 1,
831 
    },
832 
    'sysgen_dut.to_register15_ce' => {
833 
      'hdlType' => 'std_logic',
834 
      'width' => 1,
835 
    },
836 
    'sysgen_dut.to_register15_clk' => {
837 
      'hdlType' => 'std_logic',
838 
      'width' => 1,
839 
    },
840 
    'sysgen_dut.to_register15_clr' => {
841 
      'hdlType' => 'std_logic',
842 
      'width' => 1,
843 
    },
844 
    'sysgen_dut.to_register15_data_in' => {
845 
      'hdlType' => 'std_logic_vector(31 downto 0)',
846 
      'width' => 32,
847 
    },
848 
    'sysgen_dut.to_register15_en' => {
849 
      'hdlType' => 'std_logic',
850 
      'width' => 1,
851 
    },
852 
    'sysgen_dut.to_register16_ce' => {
853 
      'hdlType' => 'std_logic',
854 
      'width' => 1,
855 
    },
856 
    'sysgen_dut.to_register16_clk' => {
857 
      'hdlType' => 'std_logic',
858 
      'width' => 1,
859 
    },
860 
    'sysgen_dut.to_register16_clr' => {
861 
      'hdlType' => 'std_logic',
862 
      'width' => 1,
863 
    },
864 
    'sysgen_dut.to_register16_data_in' => {
865 
      'hdlType' => 'std_logic',
866 
      'width' => 1,
867 
    },
868 
    'sysgen_dut.to_register16_en' => {
869 
      'hdlType' => 'std_logic',
870 
      'width' => 1,
871 
    },
872 
    'sysgen_dut.to_register17_ce' => {
873 
      'hdlType' => 'std_logic',
874 
      'width' => 1,
875 
    },
876 
    'sysgen_dut.to_register17_clk' => {
877 
      'hdlType' => 'std_logic',
878 
      'width' => 1,
879 
    },
880 
    'sysgen_dut.to_register17_clr' => {
881 
      'hdlType' => 'std_logic',
882 
      'width' => 1,
883 
    },
884 
    'sysgen_dut.to_register17_data_in' => {
885 
      'hdlType' => 'std_logic_vector(31 downto 0)',
886 
      'width' => 32,
887 
    },
888 
    'sysgen_dut.to_register17_en' => {
889 
      'hdlType' => 'std_logic',
890 
      'width' => 1,
891 
    },
892 
    'sysgen_dut.to_register18_ce' => {
893 
      'hdlType' => 'std_logic',
894 
      'width' => 1,
895 
    },
896 
    'sysgen_dut.to_register18_clk' => {
897 
      'hdlType' => 'std_logic',
898 
      'width' => 1,
899 
    },
900 
    'sysgen_dut.to_register18_clr' => {
901 
      'hdlType' => 'std_logic',
902 
      'width' => 1,
903 
    },
904 
    'sysgen_dut.to_register18_data_in' => {
905 
      'hdlType' => 'std_logic',
906 
      'width' => 1,
907 
    },
908 
    'sysgen_dut.to_register18_en' => {
909 
      'hdlType' => 'std_logic',
910 
      'width' => 1,
911 
    },
912 
    'sysgen_dut.to_register19_ce' => {
913 
      'hdlType' => 'std_logic',
914 
      'width' => 1,
915 
    },
916 
    'sysgen_dut.to_register19_clk' => {
917 
      'hdlType' => 'std_logic',
918 
      'width' => 1,
919 
    },
920 
    'sysgen_dut.to_register19_clr' => {
921 
      'hdlType' => 'std_logic',
922 
      'width' => 1,
923 
    },
924 
    'sysgen_dut.to_register19_data_in' => {
925 
      'hdlType' => 'std_logic',
926 
      'width' => 1,
927 
    },
928 
    'sysgen_dut.to_register19_en' => {
929 
      'hdlType' => 'std_logic',
930 
      'width' => 1,
931 
    },
932 
    'sysgen_dut.to_register1_ce' => {
933 
      'hdlType' => 'std_logic',
934 
      'width' => 1,
935 
    },
936 
    'sysgen_dut.to_register1_clk' => {
937 
      'hdlType' => 'std_logic',
938 
      'width' => 1,
939 
    },
940 
    'sysgen_dut.to_register1_clr' => {
941 
      'hdlType' => 'std_logic',
942 
      'width' => 1,
943 
    },
944 
    'sysgen_dut.to_register1_data_in' => {
945 
      'hdlType' => 'std_logic_vector(31 downto 0)',
946 
      'width' => 32,
947 
    },
948 
    'sysgen_dut.to_register1_en' => {
949 
      'hdlType' => 'std_logic',
950 
      'width' => 1,
951 
    },
952 
    'sysgen_dut.to_register20_ce' => {
953 
      'hdlType' => 'std_logic',
954 
      'width' => 1,
955 
    },
956 
    'sysgen_dut.to_register20_clk' => {
957 
      'hdlType' => 'std_logic',
958 
      'width' => 1,
959 
    },
960 
    'sysgen_dut.to_register20_clr' => {
961 
      'hdlType' => 'std_logic',
962 
      'width' => 1,
963 
    },
964 
    'sysgen_dut.to_register20_data_in' => {
965 
      'hdlType' => 'std_logic_vector(31 downto 0)',
966 
      'width' => 32,
967 
    },
968 
    'sysgen_dut.to_register20_en' => {
969 
      'hdlType' => 'std_logic',
970 
      'width' => 1,
971 
    },
972 
    'sysgen_dut.to_register21_ce' => {
973 
      'hdlType' => 'std_logic',
974 
      'width' => 1,
975 
    },
976 
    'sysgen_dut.to_register21_clk' => {
977 
      'hdlType' => 'std_logic',
978 
      'width' => 1,
979 
    },
980 
    'sysgen_dut.to_register21_clr' => {
981 
      'hdlType' => 'std_logic',
982 
      'width' => 1,
983 
    },
984 
    'sysgen_dut.to_register21_data_in' => {
985 
      'hdlType' => 'std_logic',
986 
      'width' => 1,
987 
    },
988 
    'sysgen_dut.to_register21_en' => {
989 
      'hdlType' => 'std_logic',
990 
      'width' => 1,
991 
    },
992 
    'sysgen_dut.to_register22_ce' => {
993 
      'hdlType' => 'std_logic',
994 
      'width' => 1,
995 
    },
996 
    'sysgen_dut.to_register22_clk' => {
997 
      'hdlType' => 'std_logic',
998 
      'width' => 1,
999 
    },
1000 
    'sysgen_dut.to_register22_clr' => {
1001 
      'hdlType' => 'std_logic',
1002 
      'width' => 1,
1003 
    },
1004 
    'sysgen_dut.to_register22_data_in' => {
1005 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1006 
      'width' => 32,
1007 
    },
1008 
    'sysgen_dut.to_register22_en' => {
1009 
      'hdlType' => 'std_logic',
1010 
      'width' => 1,
1011 
    },
1012 
    'sysgen_dut.to_register23_ce' => {
1013 
      'hdlType' => 'std_logic',
1014 
      'width' => 1,
1015 
    },
1016 
    'sysgen_dut.to_register23_clk' => {
1017 
      'hdlType' => 'std_logic',
1018 
      'width' => 1,
1019 
    },
1020 
    'sysgen_dut.to_register23_clr' => {
1021 
      'hdlType' => 'std_logic',
1022 
      'width' => 1,
1023 
    },
1024 
    'sysgen_dut.to_register23_data_in' => {
1025 
      'hdlType' => 'std_logic',
1026 
      'width' => 1,
1027 
    },
1028 
    'sysgen_dut.to_register23_en' => {
1029 
      'hdlType' => 'std_logic',
1030 
      'width' => 1,
1031 
    },
1032 
    'sysgen_dut.to_register24_ce' => {
1033 
      'hdlType' => 'std_logic',
1034 
      'width' => 1,
1035 
    },
1036 
    'sysgen_dut.to_register24_clk' => {
1037 
      'hdlType' => 'std_logic',
1038 
      'width' => 1,
1039 
    },
1040 
    'sysgen_dut.to_register24_clr' => {
1041 
      'hdlType' => 'std_logic',
1042 
      'width' => 1,
1043 
    },
1044 
    'sysgen_dut.to_register24_data_in' => {
1045 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1046 
      'width' => 32,
1047 
    },
1048 
    'sysgen_dut.to_register24_en' => {
1049 
      'hdlType' => 'std_logic',
1050 
      'width' => 1,
1051 
    },
1052 
    'sysgen_dut.to_register25_ce' => {
1053 
      'hdlType' => 'std_logic',
1054 
      'width' => 1,
1055 
    },
1056 
    'sysgen_dut.to_register25_clk' => {
1057 
      'hdlType' => 'std_logic',
1058 
      'width' => 1,
1059 
    },
1060 
    'sysgen_dut.to_register25_clr' => {
1061 
      'hdlType' => 'std_logic',
1062 
      'width' => 1,
1063 
    },
1064 
    'sysgen_dut.to_register25_data_in' => {
1065 
      'hdlType' => 'std_logic',
1066 
      'width' => 1,
1067 
    },
1068 
    'sysgen_dut.to_register25_en' => {
1069 
      'hdlType' => 'std_logic',
1070 
      'width' => 1,
1071 
    },
1072 
    'sysgen_dut.to_register26_ce' => {
1073 
      'hdlType' => 'std_logic',
1074 
      'width' => 1,
1075 
    },
1076 
    'sysgen_dut.to_register26_clk' => {
1077 
      'hdlType' => 'std_logic',
1078 
      'width' => 1,
1079 
    },
1080 
    'sysgen_dut.to_register26_clr' => {
1081 
      'hdlType' => 'std_logic',
1082 
      'width' => 1,
1083 
    },
1084 
    'sysgen_dut.to_register26_data_in' => {
1085 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1086 
      'width' => 32,
1087 
    },
1088 
    'sysgen_dut.to_register26_en' => {
1089 
      'hdlType' => 'std_logic',
1090 
      'width' => 1,
1091 
    },
1092 
    'sysgen_dut.to_register27_ce' => {
1093 
      'hdlType' => 'std_logic',
1094 
      'width' => 1,
1095 
    },
1096 
    'sysgen_dut.to_register27_clk' => {
1097 
      'hdlType' => 'std_logic',
1098 
      'width' => 1,
1099 
    },
1100 
    'sysgen_dut.to_register27_clr' => {
1101 
      'hdlType' => 'std_logic',
1102 
      'width' => 1,
1103 
    },
1104 
    'sysgen_dut.to_register27_data_in' => {
1105 
      'hdlType' => 'std_logic',
1106 
      'width' => 1,
1107 
    },
1108 
    'sysgen_dut.to_register27_en' => {
1109 
      'hdlType' => 'std_logic',
1110 
      'width' => 1,
1111 
    },
1112 
    'sysgen_dut.to_register28_ce' => {
1113 
      'hdlType' => 'std_logic',
1114 
      'width' => 1,
1115 
    },
1116 
    'sysgen_dut.to_register28_clk' => {
1117 
      'hdlType' => 'std_logic',
1118 
      'width' => 1,
1119 
    },
1120 
    'sysgen_dut.to_register28_clr' => {
1121 
      'hdlType' => 'std_logic',
1122 
      'width' => 1,
1123 
    },
1124 
    'sysgen_dut.to_register28_data_in' => {
1125 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1126 
      'width' => 32,
1127 
    },
1128 
    'sysgen_dut.to_register28_en' => {
1129 
      'hdlType' => 'std_logic',
1130 
      'width' => 1,
1131 
    },
1132 
    'sysgen_dut.to_register29_ce' => {
1133 
      'hdlType' => 'std_logic',
1134 
      'width' => 1,
1135 
    },
1136 
    'sysgen_dut.to_register29_clk' => {
1137 
      'hdlType' => 'std_logic',
1138 
      'width' => 1,
1139 
    },
1140 
    'sysgen_dut.to_register29_clr' => {
1141 
      'hdlType' => 'std_logic',
1142 
      'width' => 1,
1143 
    },
1144 
    'sysgen_dut.to_register29_data_in' => {
1145 
      'hdlType' => 'std_logic',
1146 
      'width' => 1,
1147 
    },
1148 
    'sysgen_dut.to_register29_en' => {
1149 
      'hdlType' => 'std_logic',
1150 
      'width' => 1,
1151 
    },
1152 
    'sysgen_dut.to_register2_ce' => {
1153 
      'hdlType' => 'std_logic',
1154 
      'width' => 1,
1155 
    },
1156 
    'sysgen_dut.to_register2_clk' => {
1157 
      'hdlType' => 'std_logic',
1158 
      'width' => 1,
1159 
    },
1160 
    'sysgen_dut.to_register2_clr' => {
1161 
      'hdlType' => 'std_logic',
1162 
      'width' => 1,
1163 
    },
1164 
    'sysgen_dut.to_register2_data_in' => {
1165 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1166 
      'width' => 32,
1167 
    },
1168 
    'sysgen_dut.to_register2_en' => {
1169 
      'hdlType' => 'std_logic',
1170 
      'width' => 1,
1171 
    },
1172 
    'sysgen_dut.to_register30_ce' => {
1173 
      'hdlType' => 'std_logic',
1174 
      'width' => 1,
1175 
    },
1176 
    'sysgen_dut.to_register30_clk' => {
1177 
      'hdlType' => 'std_logic',
1178 
      'width' => 1,
1179 
    },
1180 
    'sysgen_dut.to_register30_clr' => {
1181 
      'hdlType' => 'std_logic',
1182 
      'width' => 1,
1183 
    },
1184 
    'sysgen_dut.to_register30_data_in' => {
1185 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1186 
      'width' => 32,
1187 
    },
1188 
    'sysgen_dut.to_register30_en' => {
1189 
      'hdlType' => 'std_logic',
1190 
      'width' => 1,
1191 
    },
1192 
    'sysgen_dut.to_register31_ce' => {
1193 
      'hdlType' => 'std_logic',
1194 
      'width' => 1,
1195 
    },
1196 
    'sysgen_dut.to_register31_clk' => {
1197 
      'hdlType' => 'std_logic',
1198 
      'width' => 1,
1199 
    },
1200 
    'sysgen_dut.to_register31_clr' => {
1201 
      'hdlType' => 'std_logic',
1202 
      'width' => 1,
1203 
    },
1204 
    'sysgen_dut.to_register31_data_in' => {
1205 
      'hdlType' => 'std_logic',
1206 
      'width' => 1,
1207 
    },
1208 
    'sysgen_dut.to_register31_en' => {
1209 
      'hdlType' => 'std_logic',
1210 
      'width' => 1,
1211 
    },
1212 
    'sysgen_dut.to_register32_ce' => {
1213 
      'hdlType' => 'std_logic',
1214 
      'width' => 1,
1215 
    },
1216 
    'sysgen_dut.to_register32_clk' => {
1217 
      'hdlType' => 'std_logic',
1218 
      'width' => 1,
1219 
    },
1220 
    'sysgen_dut.to_register32_clr' => {
1221 
      'hdlType' => 'std_logic',
1222 
      'width' => 1,
1223 
    },
1224 
    'sysgen_dut.to_register32_data_in' => {
1225 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1226 
      'width' => 32,
1227 
    },
1228 
    'sysgen_dut.to_register32_en' => {
1229 
      'hdlType' => 'std_logic',
1230 
      'width' => 1,
1231 
    },
1232 
    'sysgen_dut.to_register33_ce' => {
1233 
      'hdlType' => 'std_logic',
1234 
      'width' => 1,
1235 
    },
1236 
    'sysgen_dut.to_register33_clk' => {
1237 
      'hdlType' => 'std_logic',
1238 
      'width' => 1,
1239 
    },
1240 
    'sysgen_dut.to_register33_clr' => {
1241 
      'hdlType' => 'std_logic',
1242 
      'width' => 1,
1243 
    },
1244 
    'sysgen_dut.to_register33_data_in' => {
1245 
      'hdlType' => 'std_logic',
1246 
      'width' => 1,
1247 
    },
1248 
    'sysgen_dut.to_register33_en' => {
1249 
      'hdlType' => 'std_logic',
1250 
      'width' => 1,
1251 
    },
1252 
    'sysgen_dut.to_register34_ce' => {
1253 
      'hdlType' => 'std_logic',
1254 
      'width' => 1,
1255 
    },
1256 
    'sysgen_dut.to_register34_clk' => {
1257 
      'hdlType' => 'std_logic',
1258 
      'width' => 1,
1259 
    },
1260 
    'sysgen_dut.to_register34_clr' => {
1261 
      'hdlType' => 'std_logic',
1262 
      'width' => 1,
1263 
    },
1264 
    'sysgen_dut.to_register34_data_in' => {
1265 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1266 
      'width' => 32,
1267 
    },
1268 
    'sysgen_dut.to_register34_en' => {
1269 
      'hdlType' => 'std_logic',
1270 
      'width' => 1,
1271 
    },
1272 
    'sysgen_dut.to_register3_ce' => {
1273 
      'hdlType' => 'std_logic',
1274 
      'width' => 1,
1275 
    },
1276 
    'sysgen_dut.to_register3_clk' => {
1277 
      'hdlType' => 'std_logic',
1278 
      'width' => 1,
1279 
    },
1280 
    'sysgen_dut.to_register3_clr' => {
1281 
      'hdlType' => 'std_logic',
1282 
      'width' => 1,
1283 
    },
1284 
    'sysgen_dut.to_register3_data_in' => {
1285 
      'hdlType' => 'std_logic',
1286 
      'width' => 1,
1287 
    },
1288 
    'sysgen_dut.to_register3_en' => {
1289 
      'hdlType' => 'std_logic',
1290 
      'width' => 1,
1291 
    },
1292 
    'sysgen_dut.to_register4_ce' => {
1293 
      'hdlType' => 'std_logic',
1294 
      'width' => 1,
1295 
    },
1296 
    'sysgen_dut.to_register4_clk' => {
1297 
      'hdlType' => 'std_logic',
1298 
      'width' => 1,
1299 
    },
1300 
    'sysgen_dut.to_register4_clr' => {
1301 
      'hdlType' => 'std_logic',
1302 
      'width' => 1,
1303 
    },
1304 
    'sysgen_dut.to_register4_data_in' => {
1305 
      'hdlType' => 'std_logic',
1306 
      'width' => 1,
1307 
    },
1308 
    'sysgen_dut.to_register4_en' => {
1309 
      'hdlType' => 'std_logic',
1310 
      'width' => 1,
1311 
    },
1312 
    'sysgen_dut.to_register5_ce' => {
1313 
      'hdlType' => 'std_logic',
1314 
      'width' => 1,
1315 
    },
1316 
    'sysgen_dut.to_register5_clk' => {
1317 
      'hdlType' => 'std_logic',
1318 
      'width' => 1,
1319 
    },
1320 
    'sysgen_dut.to_register5_clr' => {
1321 
      'hdlType' => 'std_logic',
1322 
      'width' => 1,
1323 
    },
1324 
    'sysgen_dut.to_register5_data_in' => {
1325 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1326 
      'width' => 32,
1327 
    },
1328 
    'sysgen_dut.to_register5_en' => {
1329 
      'hdlType' => 'std_logic',
1330 
      'width' => 1,
1331 
    },
1332 
    'sysgen_dut.to_register6_ce' => {
1333 
      'hdlType' => 'std_logic',
1334 
      'width' => 1,
1335 
    },
1336 
    'sysgen_dut.to_register6_clk' => {
1337 
      'hdlType' => 'std_logic',
1338 
      'width' => 1,
1339 
    },
1340 
    'sysgen_dut.to_register6_clr' => {
1341 
      'hdlType' => 'std_logic',
1342 
      'width' => 1,
1343 
    },
1344 
    'sysgen_dut.to_register6_data_in' => {
1345 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1346 
      'width' => 32,
1347 
    },
1348 
    'sysgen_dut.to_register6_en' => {
1349 
      'hdlType' => 'std_logic',
1350 
      'width' => 1,
1351 
    },
1352 
    'sysgen_dut.to_register7_ce' => {
1353 
      'hdlType' => 'std_logic',
1354 
      'width' => 1,
1355 
    },
1356 
    'sysgen_dut.to_register7_clk' => {
1357 
      'hdlType' => 'std_logic',
1358 
      'width' => 1,
1359 
    },
1360 
    'sysgen_dut.to_register7_clr' => {
1361 
      'hdlType' => 'std_logic',
1362 
      'width' => 1,
1363 
    },
1364 
    'sysgen_dut.to_register7_data_in' => {
1365 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1366 
      'width' => 32,
1367 
    },
1368 
    'sysgen_dut.to_register7_en' => {
1369 
      'hdlType' => 'std_logic',
1370 
      'width' => 1,
1371 
    },
1372 
    'sysgen_dut.to_register8_ce' => {
1373 
      'hdlType' => 'std_logic',
1374 
      'width' => 1,
1375 
    },
1376 
    'sysgen_dut.to_register8_clk' => {
1377 
      'hdlType' => 'std_logic',
1378 
      'width' => 1,
1379 
    },
1380 
    'sysgen_dut.to_register8_clr' => {
1381 
      'hdlType' => 'std_logic',
1382 
      'width' => 1,
1383 
    },
1384 
    'sysgen_dut.to_register8_data_in' => {
1385 
      'hdlType' => 'std_logic',
1386 
      'width' => 1,
1387 
    },
1388 
    'sysgen_dut.to_register8_en' => {
1389 
      'hdlType' => 'std_logic',
1390 
      'width' => 1,
1391 
    },
1392 
    'sysgen_dut.to_register9_ce' => {
1393 
      'hdlType' => 'std_logic',
1394 
      'width' => 1,
1395 
    },
1396 
    'sysgen_dut.to_register9_clk' => {
1397 
      'hdlType' => 'std_logic',
1398 
      'width' => 1,
1399 
    },
1400 
    'sysgen_dut.to_register9_clr' => {
1401 
      'hdlType' => 'std_logic',
1402 
      'width' => 1,
1403 
    },
1404 
    'sysgen_dut.to_register9_data_in' => {
1405 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1406 
      'width' => 32,
1407 
    },
1408 
    'sysgen_dut.to_register9_en' => {
1409 
      'hdlType' => 'std_logic',
1410 
      'width' => 1,
1411 
    },
1412 
    'to_register1.dout' => {
1413 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1414 
      'width' => 32,
1415 
    },
1416 
    'to_register10.dout' => {
1417 
      'hdlType' => 'std_logic',
1418 
      'width' => 1,
1419 
    },
1420 
    'to_register11.dout' => {
1421 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1422 
      'width' => 32,
1423 
    },
1424 
    'to_register12.dout' => {
1425 
      'hdlType' => 'std_logic',
1426 
      'width' => 1,
1427 
    },
1428 
    'to_register13.dout' => {
1429 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1430 
      'width' => 32,
1431 
    },
1432 
    'to_register14.dout' => {
1433 
      'hdlType' => 'std_logic',
1434 
      'width' => 1,
1435 
    },
1436 
    'to_register15.dout' => {
1437 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1438 
      'width' => 32,
1439 
    },
1440 
    'to_register16.dout' => {
1441 
      'hdlType' => 'std_logic',
1442 
      'width' => 1,
1443 
    },
1444 
    'to_register17.dout' => {
1445 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1446 
      'width' => 32,
1447 
    },
1448 
    'to_register18.dout' => {
1449 
      'hdlType' => 'std_logic',
1450 
      'width' => 1,
1451 
    },
1452 
    'to_register19.dout' => {
1453 
      'hdlType' => 'std_logic',
1454 
      'width' => 1,
1455 
    },
1456 
    'to_register2.dout' => {
1457 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1458 
      'width' => 32,
1459 
    },
1460 
    'to_register20.dout' => {
1461 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1462 
      'width' => 32,
1463 
    },
1464 
    'to_register21.dout' => {
1465 
      'hdlType' => 'std_logic',
1466 
      'width' => 1,
1467 
    },
1468 
    'to_register22.dout' => {
1469 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1470 
      'width' => 32,
1471 
    },
1472 
    'to_register23.dout' => {
1473 
      'hdlType' => 'std_logic',
1474 
      'width' => 1,
1475 
    },
1476 
    'to_register24.dout' => {
1477 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1478 
      'width' => 32,
1479 
    },
1480 
    'to_register25.dout' => {
1481 
      'hdlType' => 'std_logic',
1482 
      'width' => 1,
1483 
    },
1484 
    'to_register26.dout' => {
1485 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1486 
      'width' => 32,
1487 
    },
1488 
    'to_register27.dout' => {
1489 
      'hdlType' => 'std_logic',
1490 
      'width' => 1,
1491 
    },
1492 
    'to_register28.dout' => {
1493 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1494 
      'width' => 32,
1495 
    },
1496 
    'to_register29.dout' => {
1497 
      'hdlType' => 'std_logic',
1498 
      'width' => 1,
1499 
    },
1500 
    'to_register3.dout' => {
1501 
      'hdlType' => 'std_logic',
1502 
      'width' => 1,
1503 
    },
1504 
    'to_register30.dout' => {
1505 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1506 
      'width' => 32,
1507 
    },
1508 
    'to_register31.dout' => {
1509 
      'hdlType' => 'std_logic',
1510 
      'width' => 1,
1511 
    },
1512 
    'to_register32.dout' => {
1513 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1514 
      'width' => 32,
1515 
    },
1516 
    'to_register33.dout' => {
1517 
      'hdlType' => 'std_logic',
1518 
      'width' => 1,
1519 
    },
1520 
    'to_register34.dout' => {
1521 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1522 
      'width' => 32,
1523 
    },
1524 
    'to_register4.dout' => {
1525 
      'hdlType' => 'std_logic',
1526 
      'width' => 1,
1527 
    },
1528 
    'to_register5.dout' => {
1529 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1530 
      'width' => 32,
1531 
    },
1532 
    'to_register6.dout' => {
1533 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1534 
      'width' => 32,
1535 
    },
1536 
    'to_register7.dout' => {
1537 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1538 
      'width' => 32,
1539 
    },
1540 
    'to_register8.dout' => {
1541 
      'hdlType' => 'std_logic',
1542 
      'width' => 1,
1543 
    },
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              'type' => 'Bool',
4909 
            },
4910 
            'direction' => 'out',
4911 
            'hdlType' => 'std_logic',
4912 
            'width' => 1,
4913 
          },
4914 
        },
4915 
      },
4916 
      'entityName' => 'reg13_tv',
4917 
    },
4918 
    'reg14_rd' => {
4919 
      'connections' => { 'reg14_rd' => 'sysgen_dut.reg14_rd', },
4920 
      'entity' => {
4921 
        'attributes' => {
4922 
          'entityAlreadyNetlisted' => 1,
4923 
          'isGateway' => 1,
4924 
          'is_floating_block' => 1,
4925 
        },
4926 
        'entityName' => 'reg14_rd',
4927 
        'ports' => {
4928 
          'reg14_rd' => {
4929 
            'attributes' => {
4930 
              'bin_pt' => 0,
4931 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
4932 
              'is_floating_block' => 1,
4933 
              'is_gateway_port' => 1,
4934 
              'must_be_hdl_vector' => 1,
4935 
              'period' => 1,
4936 
              'port_id' => 0,
4937 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
4938 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
4939 
              'timingConstraint' => 'none',
4940 
              'type' => 'UFix_32_0',
4941 
            },
4942 
            'direction' => 'in',
4943 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4944 
            'width' => 32,
4945 
          },
4946 
        },
4947 
      },
4948 
      'entityName' => 'reg14_rd',
4949 
    },
4950 
    'reg14_rv' => {
4951 
      'connections' => { 'reg14_rv' => 'sysgen_dut.reg14_rv', },
4952 
      'entity' => {
4953 
        'attributes' => {
4954 
          'entityAlreadyNetlisted' => 1,
4955 
          'isGateway' => 1,
4956 
          'is_floating_block' => 1,
4957 
        },
4958 
        'entityName' => 'reg14_rv',
4959 
        'ports' => {
4960 
          'reg14_rv' => {
4961 
            'attributes' => {
4962 
              'bin_pt' => 0,
4963 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rv.dat',
4964 
              'is_floating_block' => 1,
4965 
              'is_gateway_port' => 1,
4966 
              'must_be_hdl_vector' => 1,
4967 
              'period' => 1,
4968 
              'port_id' => 0,
4969 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv/reg14_rv',
4970 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rv',
4971 
              'timingConstraint' => 'none',
4972 
              'type' => 'UFix_1_0',
4973 
            },
4974 
            'direction' => 'in',
4975 
            'hdlType' => 'std_logic',
4976 
            'width' => 1,
4977 
          },
4978 
        },
4979 
      },
4980 
      'entityName' => 'reg14_rv',
4981 
    },
4982 
    'reg14_td' => {
4983 
      'connections' => { 'reg14_td' => '.reg14_td', },
4984 
      'entity' => {
4985 
        'attributes' => {
4986 
          'entityAlreadyNetlisted' => 1,
4987 
          'isGateway' => 1,
4988 
          'is_floating_block' => 1,
4989 
        },
4990 
        'entityName' => 'reg14_td',
4991 
        'ports' => {
4992 
          'reg14_td' => {
4993 
            'attributes' => {
4994 
              'bin_pt' => 0,
4995 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_td.dat',
4996 
              'is_floating_block' => 1,
4997 
              'is_gateway_port' => 1,
4998 
              'must_be_hdl_vector' => 1,
4999 
              'period' => 1,
5000 
              'port_id' => 0,
5001 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td/reg14_td',
5002 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_td',
5003 
              'timingConstraint' => 'none',
5004 
              'type' => 'UFix_32_0',
5005 
            },
5006 
            'direction' => 'out',
5007 
            'hdlType' => 'std_logic_vector(31 downto 0)',
5008 
            'width' => 32,
5009 
          },
5010 
        },
5011 
      },
5012 
      'entityName' => 'reg14_td',
5013 
    },
5014 
    'reg14_tv' => {
5015 
      'connections' => { 'reg14_tv' => '.reg14_tv', },
5016 
      'entity' => {
5017 
        'attributes' => {
5018 
          'entityAlreadyNetlisted' => 1,
5019 
          'isGateway' => 1,
5020 
          'is_floating_block' => 1,
5021 
        },
5022 
        'entityName' => 'reg14_tv',
5023 
        'ports' => {
5024 
          'reg14_tv' => {
5025 
            'attributes' => {
5026 
              'bin_pt' => 0,
5027 
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_tv.dat',
5028 
              'is_floating_block' => 1,
5029 
              'is_gateway_port' => 1,
5030 
              'must_be_hdl_vector' => 1,
5031 
              'period' => 1,
5032 
              'port_id' => 0,
5033 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv/reg14_tv',
5034 
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_tv',
5035 
              'timingConstraint' => 'none',
5036 
              'type' => 'Bool',
5037 
            },
5038 
            'direction' => 'out',
5039 
            'hdlType' => 'std_logic',
5040 
            'width' => 1,
5041 
          },
5042 
        },
5043 
      },
5044 
      'entityName' => 'reg14_tv',
5045 
    },
5046 
    'sysgen_dut' => {
5047 
      'connections' => {
5048 
        'clk' => '.clk',
5049 
        'debug_in_1i' => '.debug_in_1i',
5050 
        'debug_in_2i' => '.debug_in_2i',
5051 
        'debug_in_3i' => '.debug_in_3i',
5052 
        'debug_in_4i' => '.debug_in_4i',
5053 
        'dma_host2board_busy' => '.dma_host2board_busy',
5054 
        'dma_host2board_done' => '.dma_host2board_done',
5055 
        'from_register10_data_out' => 'from_register10.data_out',
5056 
        'from_register11_data_out' => 'from_register11.data_out',
5057 
        'from_register12_data_out' => 'from_register12.data_out',
5058 
        'from_register13_data_out' => 'from_register13.data_out',
5059 
        'from_register14_data_out' => 'from_register14.data_out',
5060 
        'from_register15_data_out' => 'from_register15.data_out',
5061 
        'from_register16_data_out' => 'from_register16.data_out',
5062 
        'from_register17_data_out' => 'from_register17.data_out',
5063 
        'from_register18_data_out' => 'from_register18.data_out',
5064 
        'from_register19_data_out' => 'from_register19.data_out',
5065 
        'from_register1_data_out' => 'from_register1.data_out',
5066 
        'from_register20_data_out' => 'from_register20.data_out',
5067 
        'from_register21_data_out' => 'from_register21.data_out',
5068 
        'from_register22_data_out' => 'from_register22.data_out',
5069 
        'from_register23_data_out' => 'from_register23.data_out',
5070 
        'from_register24_data_out' => 'from_register24.data_out',
5071 
        'from_register25_data_out' => 'from_register25.data_out',
5072 
        'from_register26_data_out' => 'from_register26.data_out',
5073 
        'from_register27_data_out' => 'from_register27.data_out',
5074 
        'from_register28_data_out' => 'from_register28.data_out',
5075 
        'from_register2_data_out' => 'from_register2.data_out',
5076 
        'from_register3_data_out' => 'from_register3.data_out',
5077 
        'from_register4_data_out' => 'from_register4.data_out',
5078 
        'from_register5_data_out' => 'from_register5.data_out',
5079 
        'from_register6_data_out' => 'from_register6.data_out',
5080 
        'from_register7_data_out' => 'from_register7.data_out',
5081 
        'from_register8_data_out' => 'from_register8.data_out',
5082 
        'from_register9_data_out' => 'from_register9.data_out',
5083 
        'reg01_rd' => 'sysgen_dut.reg01_rd',
5084 
        'reg01_rv' => 'sysgen_dut.reg01_rv',
5085 
        'reg01_td' => '.reg01_td',
5086 
        'reg01_tv' => '.reg01_tv',
5087 
        'reg02_rd' => 'sysgen_dut.reg02_rd',
5088 
        'reg02_rv' => 'sysgen_dut.reg02_rv',
5089 
        'reg02_td' => '.reg02_td',
5090 
        'reg02_tv' => '.reg02_tv',
5091 
        'reg03_rd' => 'sysgen_dut.reg03_rd',
5092 
        'reg03_rv' => 'sysgen_dut.reg03_rv',
5093 
        'reg03_td' => '.reg03_td',
5094 
        'reg03_tv' => '.reg03_tv',
5095 
        'reg04_rd' => 'sysgen_dut.reg04_rd',
5096 
        'reg04_rv' => 'sysgen_dut.reg04_rv',
5097 
        'reg04_td' => '.reg04_td',
5098 
        'reg04_tv' => '.reg04_tv',
5099 
        'reg05_rd' => 'sysgen_dut.reg05_rd',
5100 
        'reg05_rv' => 'sysgen_dut.reg05_rv',
5101 
        'reg05_td' => '.reg05_td',
5102 
        'reg05_tv' => '.reg05_tv',
5103 
        'reg06_rd' => 'sysgen_dut.reg06_rd',
5104 
        'reg06_rv' => 'sysgen_dut.reg06_rv',
5105 
        'reg06_td' => '.reg06_td',
5106 
        'reg06_tv' => '.reg06_tv',
5107 
        'reg07_rd' => 'sysgen_dut.reg07_rd',
5108 
        'reg07_rv' => 'sysgen_dut.reg07_rv',
5109 
        'reg07_td' => '.reg07_td',
5110 
        'reg07_tv' => '.reg07_tv',
5111 
        'reg08_rd' => 'sysgen_dut.reg08_rd',
5112 
        'reg08_rv' => 'sysgen_dut.reg08_rv',
5113 
        'reg08_td' => '.reg08_td',
5114 
        'reg08_tv' => '.reg08_tv',
5115 
        'reg09_rd' => 'sysgen_dut.reg09_rd',
5116 
        'reg09_rv' => 'sysgen_dut.reg09_rv',
5117 
        'reg09_td' => '.reg09_td',
5118 
        'reg09_tv' => '.reg09_tv',
5119 
        'reg10_rd' => 'sysgen_dut.reg10_rd',
5120 
        'reg10_rv' => 'sysgen_dut.reg10_rv',
5121 
        'reg10_td' => '.reg10_td',
5122 
        'reg10_tv' => '.reg10_tv',
5123 
        'reg11_rd' => 'sysgen_dut.reg11_rd',
5124 
        'reg11_rv' => 'sysgen_dut.reg11_rv',
5125 
        'reg11_td' => '.reg11_td',
5126 
        'reg11_tv' => '.reg11_tv',
5127 
        'reg12_rd' => 'sysgen_dut.reg12_rd',
5128 
        'reg12_rv' => 'sysgen_dut.reg12_rv',
5129 
        'reg12_td' => '.reg12_td',
5130 
        'reg12_tv' => '.reg12_tv',
5131 
        'reg13_rd' => 'sysgen_dut.reg13_rd',
5132 
        'reg13_rv' => 'sysgen_dut.reg13_rv',
5133 
        'reg13_td' => '.reg13_td',
5134 
        'reg13_tv' => '.reg13_tv',
5135 
        'reg14_rd' => 'sysgen_dut.reg14_rd',
5136 
        'reg14_rv' => 'sysgen_dut.reg14_rv',
5137 
        'reg14_td' => '.reg14_td',
5138 
        'reg14_tv' => '.reg14_tv',
5139 
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
5140 
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
5141 
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
5142 
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
5143 
        'to_register10_dout' => 'to_register10.dout',
5144 
        'to_register10_en' => 'sysgen_dut.to_register10_en',
5145 
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
5146 
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
5147 
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
5148 
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
5149 
        'to_register11_dout' => 'to_register11.dout',
5150 
        'to_register11_en' => 'sysgen_dut.to_register11_en',
5151 
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
5152 
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
5153 
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
5154 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
5155 
        'to_register12_dout' => 'to_register12.dout',
5156 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
5157 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
5158 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
5159 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
5160 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
5161 
        'to_register13_dout' => 'to_register13.dout',
5162 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
5163 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
5164 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
5165 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
5166 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
5167 
        'to_register14_dout' => 'to_register14.dout',
5168 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
5169 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
5170 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
5171 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
5172 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
5173 
        'to_register15_dout' => 'to_register15.dout',
5174 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
5175 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
5176 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
5177 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
5178 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
5179 
        'to_register16_dout' => 'to_register16.dout',
5180 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
5181 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
5182 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
5183 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
5184 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
5185 
        'to_register17_dout' => 'to_register17.dout',
5186 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
5187 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
5188 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
5189 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
5190 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
5191 
        'to_register18_dout' => 'to_register18.dout',
5192 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
5193 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
5194 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
5195 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
5196 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
5197 
        'to_register19_dout' => 'to_register19.dout',
5198 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
5199 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
5200 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
5201 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
5202 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
5203 
        'to_register1_dout' => 'to_register1.dout',
5204 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
5205 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
5206 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
5207 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
5208 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
5209 
        'to_register20_dout' => 'to_register20.dout',
5210 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
5211 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
5212 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
5213 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
5214 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
5215 
        'to_register21_dout' => 'to_register21.dout',
5216 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
5217 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
5218 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
5219 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
5220 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
5221 
        'to_register22_dout' => 'to_register22.dout',
5222 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
5223 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
5224 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
5225 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
5226 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
5227 
        'to_register23_dout' => 'to_register23.dout',
5228 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
5229 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
5230 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
5231 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
5232 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
5233 
        'to_register24_dout' => 'to_register24.dout',
5234 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
5235 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
5236 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
5237 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
5238 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
5239 
        'to_register25_dout' => 'to_register25.dout',
5240 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
5241 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
5242 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
5243 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
5244 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
5245 
        'to_register26_dout' => 'to_register26.dout',
5246 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
5247 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
5248 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
5249 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
5250 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
5251 
        'to_register27_dout' => 'to_register27.dout',
5252 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
5253 
        'to_register28_ce' => 'sysgen_dut.to_register28_ce',
5254 
        'to_register28_clk' => 'sysgen_dut.to_register28_clk',
5255 
        'to_register28_clr' => 'sysgen_dut.to_register28_clr',
5256 
        'to_register28_data_in' => 'sysgen_dut.to_register28_data_in',
5257 
        'to_register28_dout' => 'to_register28.dout',
5258 
        'to_register28_en' => 'sysgen_dut.to_register28_en',
5259 
        'to_register29_ce' => 'sysgen_dut.to_register29_ce',
5260 
        'to_register29_clk' => 'sysgen_dut.to_register29_clk',
5261 
        'to_register29_clr' => 'sysgen_dut.to_register29_clr',
5262 
        'to_register29_data_in' => 'sysgen_dut.to_register29_data_in',
5263 
        'to_register29_dout' => 'to_register29.dout',
5264 
        'to_register29_en' => 'sysgen_dut.to_register29_en',
5265 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
5266 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
5267 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
5268 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
5269 
        'to_register2_dout' => 'to_register2.dout',
5270 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
5271 
        'to_register30_ce' => 'sysgen_dut.to_register30_ce',
5272 
        'to_register30_clk' => 'sysgen_dut.to_register30_clk',
5273 
        'to_register30_clr' => 'sysgen_dut.to_register30_clr',
5274 
        'to_register30_data_in' => 'sysgen_dut.to_register30_data_in',
5275 
        'to_register30_dout' => 'to_register30.dout',
5276 
        'to_register30_en' => 'sysgen_dut.to_register30_en',
5277 
        'to_register31_ce' => 'sysgen_dut.to_register31_ce',
5278 
        'to_register31_clk' => 'sysgen_dut.to_register31_clk',
5279 
        'to_register31_clr' => 'sysgen_dut.to_register31_clr',
5280 
        'to_register31_data_in' => 'sysgen_dut.to_register31_data_in',
5281 
        'to_register31_dout' => 'to_register31.dout',
5282 
        'to_register31_en' => 'sysgen_dut.to_register31_en',
5283 
        'to_register32_ce' => 'sysgen_dut.to_register32_ce',
5284 
        'to_register32_clk' => 'sysgen_dut.to_register32_clk',
5285 
        'to_register32_clr' => 'sysgen_dut.to_register32_clr',
5286 
        'to_register32_data_in' => 'sysgen_dut.to_register32_data_in',
5287 
        'to_register32_dout' => 'to_register32.dout',
5288 
        'to_register32_en' => 'sysgen_dut.to_register32_en',
5289 
        'to_register33_ce' => 'sysgen_dut.to_register33_ce',
5290 
        'to_register33_clk' => 'sysgen_dut.to_register33_clk',
5291 
        'to_register33_clr' => 'sysgen_dut.to_register33_clr',
5292 
        'to_register33_data_in' => 'sysgen_dut.to_register33_data_in',
5293 
        'to_register33_dout' => 'to_register33.dout',
5294 
        'to_register33_en' => 'sysgen_dut.to_register33_en',
5295 
        'to_register34_ce' => 'sysgen_dut.to_register34_ce',
5296 
        'to_register34_clk' => 'sysgen_dut.to_register34_clk',
5297 
        'to_register34_clr' => 'sysgen_dut.to_register34_clr',
5298 
        'to_register34_data_in' => 'sysgen_dut.to_register34_data_in',
5299 
        'to_register34_dout' => 'to_register34.dout',
5300 
        'to_register34_en' => 'sysgen_dut.to_register34_en',
5301 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
5302 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
5303 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
5304 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
5305 
        'to_register3_dout' => 'to_register3.dout',
5306 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
5307 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
5308 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
5309 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
5310 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
5311 
        'to_register4_dout' => 'to_register4.dout',
5312 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
5313 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
5314 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
5315 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
5316 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
5317 
        'to_register5_dout' => 'to_register5.dout',
5318 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
5319 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
5320 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
5321 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
5322 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
5323 
        'to_register6_dout' => 'to_register6.dout',
5324 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
5325 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
5326 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
5327 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
5328 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
5329 
        'to_register7_dout' => 'to_register7.dout',
5330 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
5331 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
5332 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
5333 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
5334 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
5335 
        'to_register8_dout' => 'to_register8.dout',
5336 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
5337 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
5338 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
5339 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
5340 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
5341 
        'to_register9_dout' => 'to_register9.dout',
5342 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
5343 
      },
5344 
      'entity' => {
5345 
        'attributes' => {
5346 
          'entityAlreadyNetlisted' => 1,
5347 
          'hdlArchAttributes' => [],
5348 
          'hdlEntityAttributes' => [],
5349 
          'isClkWrapper' => 1,
5350 
        },
5351 
        'connections' => {
5352 
          'clk' => 'clkNet',
5353 
          'debug_in_1i' => 'debug_in_1i_net',
5354 
          'debug_in_2i' => 'debug_in_2i_net',
5355 
          'debug_in_3i' => 'debug_in_3i_net',
5356 
          'debug_in_4i' => 'debug_in_4i_net',
5357 
          'dma_host2board_busy' => 'dma_host2board_busy_net',
5358 
          'dma_host2board_done' => 'dma_host2board_done_net',
5359 
          'from_register10_data_out' => 'from_register10_data_out_net',
5360 
          'from_register11_data_out' => 'from_register11_data_out_net',
5361 
          'from_register12_data_out' => 'from_register12_data_out_net',
5362 
          'from_register13_data_out' => 'from_register13_data_out_net',
5363 
          'from_register14_data_out' => 'from_register14_data_out_net',
5364 
          'from_register15_data_out' => 'from_register15_data_out_net',
5365 
          'from_register16_data_out' => 'from_register16_data_out_net',
5366 
          'from_register17_data_out' => 'from_register17_data_out_net',
5367 
          'from_register18_data_out' => 'from_register18_data_out_net',
5368 
          'from_register19_data_out' => 'from_register19_data_out_net',
5369 
          'from_register1_data_out' => 'from_register1_data_out_net',
5370 
          'from_register20_data_out' => 'from_register20_data_out_net',
5371 
          'from_register21_data_out' => 'from_register21_data_out_net',
5372 
          'from_register22_data_out' => 'from_register22_data_out_net',
5373 
          'from_register23_data_out' => 'from_register23_data_out_net',
5374 
          'from_register24_data_out' => 'from_register24_data_out_net',
5375 
          'from_register25_data_out' => 'from_register25_data_out_net',
5376 
          'from_register26_data_out' => 'from_register26_data_out_net',
5377 
          'from_register27_data_out' => 'from_register27_data_out_net',
5378 
          'from_register28_data_out' => 'from_register28_data_out_net',
5379 
          'from_register2_data_out' => 'from_register2_data_out_net',
5380 
          'from_register3_data_out' => 'from_register3_data_out_net',
5381 
          'from_register4_data_out' => 'from_register4_data_out_net',
5382 
          'from_register5_data_out' => 'from_register5_data_out_net',
5383 
          'from_register6_data_out' => 'from_register6_data_out_net',
5384 
          'from_register7_data_out' => 'from_register7_data_out_net',
5385 
          'from_register8_data_out' => 'from_register8_data_out_net',
5386 
          'from_register9_data_out' => 'from_register9_data_out_net',
5387 
          'reg01_rd' => 'from_register3_data_out_net_x0',
5388 
          'reg01_rv' => 'from_register1_data_out_net_x0',
5389 
          'reg01_td' => 'reg01_td_net',
5390 
          'reg01_tv' => 'reg01_tv_net',
5391 
          'reg02_rd' => 'from_register5_data_out_net_x0',
5392 
          'reg02_rv' => 'from_register2_data_out_net_x0',
5393 
          'reg02_td' => 'reg02_td_net',
5394 
          'reg02_tv' => 'reg02_tv_net',
5395 
          'reg03_rd' => 'from_register7_data_out_net_x0',
5396 
          'reg03_rv' => 'from_register6_data_out_net_x0',
5397 
          'reg03_td' => 'reg03_td_net',
5398 
          'reg03_tv' => 'reg03_tv_net',
5399 
          'reg04_rd' => 'from_register8_data_out_net_x0',
5400 
          'reg04_rv' => 'from_register4_data_out_net_x0',
5401 
          'reg04_td' => 'reg04_td_net',
5402 
          'reg04_tv' => 'reg04_tv_net',
5403 
          'reg05_rd' => 'from_register10_data_out_net_x0',
5404 
          'reg05_rv' => 'from_register9_data_out_net_x0',
5405 
          'reg05_td' => 'reg05_td_net',
5406 
          'reg05_tv' => 'reg05_tv_net',
5407 
          'reg06_rd' => 'from_register11_data_out_net_x0',
5408 
          'reg06_rv' => 'from_register12_data_out_net_x0',
5409 
          'reg06_td' => 'reg06_td_net',
5410 
          'reg06_tv' => 'reg06_tv_net',
5411 
          'reg07_rd' => 'from_register13_data_out_net_x0',
5412 
          'reg07_rv' => 'from_register14_data_out_net_x0',
5413 
          'reg07_td' => 'reg07_td_net',
5414 
          'reg07_tv' => 'reg07_tv_net',
5415 
          'reg08_rd' => 'from_register15_data_out_net_x0',
5416 
          'reg08_rv' => 'from_register16_data_out_net_x0',
5417 
          'reg08_td' => 'reg08_td_net',
5418 
          'reg08_tv' => 'reg08_tv_net',
5419 
          'reg09_rd' => 'from_register17_data_out_net_x0',
5420 
          'reg09_rv' => 'from_register18_data_out_net_x0',
5421 
          'reg09_td' => 'reg09_td_net',
5422 
          'reg09_tv' => 'reg09_tv_net',
5423 
          'reg10_rd' => 'from_register19_data_out_net_x0',
5424 
          'reg10_rv' => 'from_register20_data_out_net_x0',
5425 
          'reg10_td' => 'reg10_td_net',
5426 
          'reg10_tv' => 'reg10_tv_net',
5427 
          'reg11_rd' => 'from_register21_data_out_net_x0',
5428 
          'reg11_rv' => 'from_register22_data_out_net_x0',
5429 
          'reg11_td' => 'reg11_td_net',
5430 
          'reg11_tv' => 'reg11_tv_net',
5431 
          'reg12_rd' => 'from_register23_data_out_net_x0',
5432 
          'reg12_rv' => 'from_register24_data_out_net_x0',
5433 
          'reg12_td' => 'reg12_td_net',
5434 
          'reg12_tv' => 'reg12_tv_net',
5435 
          'reg13_rd' => 'from_register25_data_out_net_x0',
5436 
          'reg13_rv' => 'from_register26_data_out_net_x0',
5437 
          'reg13_td' => 'reg13_td_net',
5438 
          'reg13_tv' => 'reg13_tv_net',
5439 
          'reg14_rd' => 'from_register27_data_out_net_x0',
5440 
          'reg14_rv' => 'from_register28_data_out_net_x0',
5441 
          'reg14_td' => 'reg14_td_net',
5442 
          'reg14_tv' => 'reg14_tv_net',
5443 
          'to_register10_ce' => 'ce_1_sg',
5444 
          'to_register10_clk' => 'clk_1_sg',
5445 
          'to_register10_clr' => [
5446 
            'constant',
5447 
            '\'0\'',
5448 
          ],
5449 
          'to_register10_data_in' => 'reg04_tv_net_x0',
5450 
          'to_register10_dout' => 'to_register10_dout_net',
5451 
          'to_register10_en' => 'constant5_op_net_x1',
5452 
          'to_register11_ce' => 'ce_1_sg',
5453 
          'to_register11_clk' => 'clk_1_sg',
5454 
          'to_register11_clr' => [
5455 
            'constant',
5456 
            '\'0\'',
5457 
          ],
5458 
          'to_register11_data_in' => 'reg04_td_net_x0',
5459 
          'to_register11_dout' => 'to_register11_dout_net',
5460 
          'to_register11_en' => 'constant5_op_net_x2',
5461 
          'to_register12_ce' => 'ce_1_sg',
5462 
          'to_register12_clk' => 'clk_1_sg',
5463 
          'to_register12_clr' => [
5464 
            'constant',
5465 
            '\'0\'',
5466 
          ],
5467 
          'to_register12_data_in' => 'reg05_tv_net_x0',
5468 
          'to_register12_dout' => 'to_register12_dout_net',
5469 
          'to_register12_en' => 'constant5_op_net_x3',
5470 
          'to_register13_ce' => 'ce_1_sg',
5471 
          'to_register13_clk' => 'clk_1_sg',
5472 
          'to_register13_clr' => [
5473 
            'constant',
5474 
            '\'0\'',
5475 
          ],
5476 
          'to_register13_data_in' => 'reg05_td_net_x0',
5477 
          'to_register13_dout' => 'to_register13_dout_net',
5478 
          'to_register13_en' => 'constant5_op_net_x4',
5479 
          'to_register14_ce' => 'ce_1_sg',
5480 
          'to_register14_clk' => 'clk_1_sg',
5481 
          'to_register14_clr' => [
5482 
            'constant',
5483 
            '\'0\'',
5484 
          ],
5485 
          'to_register14_data_in' => 'reg06_tv_net_x0',
5486 
          'to_register14_dout' => 'to_register14_dout_net',
5487 
          'to_register14_en' => 'constant5_op_net_x5',
5488 
          'to_register15_ce' => 'ce_1_sg',
5489 
          'to_register15_clk' => 'clk_1_sg',
5490 
          'to_register15_clr' => [
5491 
            'constant',
5492 
            '\'0\'',
5493 
          ],
5494 
          'to_register15_data_in' => 'reg06_td_net_x0',
5495 
          'to_register15_dout' => 'to_register15_dout_net',
5496 
          'to_register15_en' => 'constant5_op_net_x6',
5497 
          'to_register16_ce' => 'ce_1_sg',
5498 
          'to_register16_clk' => 'clk_1_sg',
5499 
          'to_register16_clr' => [
5500 
            'constant',
5501 
            '\'0\'',
5502 
          ],
5503 
          'to_register16_data_in' => 'reg07_tv_net_x0',
5504 
          'to_register16_dout' => 'to_register16_dout_net',
5505 
          'to_register16_en' => 'constant5_op_net_x7',
5506 
          'to_register17_ce' => 'ce_1_sg',
5507 
          'to_register17_clk' => 'clk_1_sg',
5508 
          'to_register17_clr' => [
5509 
            'constant',
5510 
            '\'0\'',
5511 
          ],
5512 
          'to_register17_data_in' => 'reg07_td_net_x0',
5513 
          'to_register17_dout' => 'to_register17_dout_net',
5514 
          'to_register17_en' => 'constant5_op_net_x8',
5515 
          'to_register18_ce' => 'ce_1_sg',
5516 
          'to_register18_clk' => 'clk_1_sg',
5517 
          'to_register18_clr' => [
5518 
            'constant',
5519 
            '\'0\'',
5520 
          ],
5521 
          'to_register18_data_in' => 'dma_host2board_busy_net_x0',
5522 
          'to_register18_dout' => 'to_register18_dout_net',
5523 
          'to_register18_en' => 'constant5_op_net_x9',
5524 
          'to_register19_ce' => 'ce_1_sg',
5525 
          'to_register19_clk' => 'clk_1_sg',
5526 
          'to_register19_clr' => [
5527 
            'constant',
5528 
            '\'0\'',
5529 
          ],
5530 
          'to_register19_data_in' => 'dma_host2board_done_net_x0',
5531 
          'to_register19_dout' => 'to_register19_dout_net',
5532 
          'to_register19_en' => 'constant5_op_net_x10',
5533 
          'to_register1_ce' => 'ce_1_sg',
5534 
          'to_register1_clk' => 'clk_1_sg',
5535 
          'to_register1_clr' => [
5536 
            'constant',
5537 
            '\'0\'',
5538 
          ],
5539 
          'to_register1_data_in' => 'debug_in_2i_net_x0',
5540 
          'to_register1_dout' => 'to_register1_dout_net',
5541 
          'to_register1_en' => 'constant5_op_net_x0',
5542 
          'to_register20_ce' => 'ce_1_sg',
5543 
          'to_register20_clk' => 'clk_1_sg',
5544 
          'to_register20_clr' => [
5545 
            'constant',
5546 
            '\'0\'',
5547 
          ],
5548 
          'to_register20_data_in' => 'debug_in_4i_net_x0',
5549 
          'to_register20_dout' => 'to_register20_dout_net',
5550 
          'to_register20_en' => 'constant5_op_net_x12',
5551 
          'to_register21_ce' => 'ce_1_sg',
5552 
          'to_register21_clk' => 'clk_1_sg',
5553 
          'to_register21_clr' => [
5554 
            'constant',
5555 
            '\'0\'',
5556 
          ],
5557 
          'to_register21_data_in' => 'reg09_tv_net_x0',
5558 
          'to_register21_dout' => 'to_register21_dout_net',
5559 
          'to_register21_en' => 'constant1_op_net_x0',
5560 
          'to_register22_ce' => 'ce_1_sg',
5561 
          'to_register22_clk' => 'clk_1_sg',
5562 
          'to_register22_clr' => [
5563 
            'constant',
5564 
            '\'0\'',
5565 
          ],
5566 
          'to_register22_data_in' => 'reg09_td_net_x0',
5567 
          'to_register22_dout' => 'to_register22_dout_net',
5568 
          'to_register22_en' => 'constant1_op_net_x1',
5569 
          'to_register23_ce' => 'ce_1_sg',
5570 
          'to_register23_clk' => 'clk_1_sg',
5571 
          'to_register23_clr' => [
5572 
            'constant',
5573 
            '\'0\'',
5574 
          ],
5575 
          'to_register23_data_in' => 'reg10_tv_net_x0',
5576 
          'to_register23_dout' => 'to_register23_dout_net',
5577 
          'to_register23_en' => 'constant1_op_net_x2',
5578 
          'to_register24_ce' => 'ce_1_sg',
5579 
          'to_register24_clk' => 'clk_1_sg',
5580 
          'to_register24_clr' => [
5581 
            'constant',
5582 
            '\'0\'',
5583 
          ],
5584 
          'to_register24_data_in' => 'reg10_td_net_x0',
5585 
          'to_register24_dout' => 'to_register24_dout_net',
5586 
          'to_register24_en' => 'constant1_op_net_x3',
5587 
          'to_register25_ce' => 'ce_1_sg',
5588 
          'to_register25_clk' => 'clk_1_sg',
5589 
          'to_register25_clr' => [
5590 
            'constant',
5591 
            '\'0\'',
5592 
          ],
5593 
          'to_register25_data_in' => 'reg08_tv_net_x0',
5594 
          'to_register25_dout' => 'to_register25_dout_net',
5595 
          'to_register25_en' => 'constant1_op_net_x4',
5596 
          'to_register26_ce' => 'ce_1_sg',
5597 
          'to_register26_clk' => 'clk_1_sg',
5598 
          'to_register26_clr' => [
5599 
            'constant',
5600 
            '\'0\'',
5601 
          ],
5602 
          'to_register26_data_in' => 'reg08_td_net_x0',
5603 
          'to_register26_dout' => 'to_register26_dout_net',
5604 
          'to_register26_en' => 'constant1_op_net_x5',
5605 
          'to_register27_ce' => 'ce_1_sg',
5606 
          'to_register27_clk' => 'clk_1_sg',
5607 
          'to_register27_clr' => [
5608 
            'constant',
5609 
            '\'0\'',
5610 
          ],
5611 
          'to_register27_data_in' => 'reg11_tv_net_x0',
5612 
          'to_register27_dout' => 'to_register27_dout_net',
5613 
          'to_register27_en' => 'constant1_op_net_x6',
5614 
          'to_register28_ce' => 'ce_1_sg',
5615 
          'to_register28_clk' => 'clk_1_sg',
5616 
          'to_register28_clr' => [
5617 
            'constant',
5618 
            '\'0\'',
5619 
          ],
5620 
          'to_register28_data_in' => 'reg11_td_net_x0',
5621 
          'to_register28_dout' => 'to_register28_dout_net',
5622 
          'to_register28_en' => 'constant1_op_net_x7',
5623 
          'to_register29_ce' => 'ce_1_sg',
5624 
          'to_register29_clk' => 'clk_1_sg',
5625 
          'to_register29_clr' => [
5626 
            'constant',
5627 
            '\'0\'',
5628 
          ],
5629 
          'to_register29_data_in' => 'reg12_tv_net_x0',
5630 
          'to_register29_dout' => 'to_register29_dout_net',
5631 
          'to_register29_en' => 'constant1_op_net_x8',
5632 
          'to_register2_ce' => 'ce_1_sg',
5633 
          'to_register2_clk' => 'clk_1_sg',
5634 
          'to_register2_clr' => [
5635 
            'constant',
5636 
            '\'0\'',
5637 
          ],
5638 
          'to_register2_data_in' => 'debug_in_3i_net_x0',
5639 
          'to_register2_dout' => 'to_register2_dout_net',
5640 
          'to_register2_en' => 'constant5_op_net_x11',
5641 
          'to_register30_ce' => 'ce_1_sg',
5642 
          'to_register30_clk' => 'clk_1_sg',
5643 
          'to_register30_clr' => [
5644 
            'constant',
5645 
            '\'0\'',
5646 
          ],
5647 
          'to_register30_data_in' => 'reg12_td_net_x0',
5648 
          'to_register30_dout' => 'to_register30_dout_net',
5649 
          'to_register30_en' => 'constant1_op_net_x9',
5650 
          'to_register31_ce' => 'ce_1_sg',
5651 
          'to_register31_clk' => 'clk_1_sg',
5652 
          'to_register31_clr' => [
5653 
            'constant',
5654 
            '\'0\'',
5655 
          ],
5656 
          'to_register31_data_in' => 'reg13_tv_net_x0',
5657 
          'to_register31_dout' => 'to_register31_dout_net',
5658 
          'to_register31_en' => 'constant1_op_net_x10',
5659 
          'to_register32_ce' => 'ce_1_sg',
5660 
          'to_register32_clk' => 'clk_1_sg',
5661 
          'to_register32_clr' => [
5662 
            'constant',
5663 
            '\'0\'',
5664 
          ],
5665 
          'to_register32_data_in' => 'reg13_td_net_x0',
5666 
          'to_register32_dout' => 'to_register32_dout_net',
5667 
          'to_register32_en' => 'constant1_op_net_x11',
5668 
          'to_register33_ce' => 'ce_1_sg',
5669 
          'to_register33_clk' => 'clk_1_sg',
5670 
          'to_register33_clr' => [
5671 
            'constant',
5672 
            '\'0\'',
5673 
          ],
5674 
          'to_register33_data_in' => 'reg14_tv_net_x0',
5675 
          'to_register33_dout' => 'to_register33_dout_net',
5676 
          'to_register33_en' => 'constant1_op_net_x12',
5677 
          'to_register34_ce' => 'ce_1_sg',
5678 
          'to_register34_clk' => 'clk_1_sg',
5679 
          'to_register34_clr' => [
5680 
            'constant',
5681 
            '\'0\'',
5682 
          ],
5683 
          'to_register34_data_in' => 'reg14_td_net_x0',
5684 
          'to_register34_dout' => 'to_register34_dout_net',
5685 
          'to_register34_en' => 'constant1_op_net_x13',
5686 
          'to_register3_ce' => 'ce_1_sg',
5687 
          'to_register3_clk' => 'clk_1_sg',
5688 
          'to_register3_clr' => [
5689 
            'constant',
5690 
            '\'0\'',
5691 
          ],
5692 
          'to_register3_data_in' => 'reg01_tv_net_x0',
5693 
          'to_register3_dout' => 'to_register3_dout_net',
5694 
          'to_register3_en' => 'constant5_op_net_x13',
5695 
          'to_register4_ce' => 'ce_1_sg',
5696 
          'to_register4_clk' => 'clk_1_sg',
5697 
          'to_register4_clr' => [
5698 
            'constant',
5699 
            '\'0\'',
5700 
          ],
5701 
          'to_register4_data_in' => 'reg02_tv_net_x0',
5702 
          'to_register4_dout' => 'to_register4_dout_net',
5703 
          'to_register4_en' => 'constant5_op_net_x14',
5704 
          'to_register5_ce' => 'ce_1_sg',
5705 
          'to_register5_clk' => 'clk_1_sg',
5706 
          'to_register5_clr' => [
5707 
            'constant',
5708 
            '\'0\'',
5709 
          ],
5710 
          'to_register5_data_in' => 'reg02_td_net_x0',
5711 
          'to_register5_dout' => 'to_register5_dout_net',
5712 
          'to_register5_en' => 'constant5_op_net_x15',
5713 
          'to_register6_ce' => 'ce_1_sg',
5714 
          'to_register6_clk' => 'clk_1_sg',
5715 
          'to_register6_clr' => [
5716 
            'constant',
5717 
            '\'0\'',
5718 
          ],
5719 
          'to_register6_data_in' => 'debug_in_1i_net_x0',
5720 
          'to_register6_dout' => 'to_register6_dout_net',
5721 
          'to_register6_en' => 'constant5_op_net_x16',
5722 
          'to_register7_ce' => 'ce_1_sg',
5723 
          'to_register7_clk' => 'clk_1_sg',
5724 
          'to_register7_clr' => [
5725 
            'constant',
5726 
            '\'0\'',
5727 
          ],
5728 
          'to_register7_data_in' => 'reg01_td_net_x0',
5729 
          'to_register7_dout' => 'to_register7_dout_net',
5730 
          'to_register7_en' => 'constant5_op_net_x17',
5731 
          'to_register8_ce' => 'ce_1_sg',
5732 
          'to_register8_clk' => 'clk_1_sg',
5733 
          'to_register8_clr' => [
5734 
            'constant',
5735 
            '\'0\'',
5736 
          ],
5737 
          'to_register8_data_in' => 'reg03_tv_net_x0',
5738 
          'to_register8_dout' => 'to_register8_dout_net',
5739 
          'to_register8_en' => 'constant5_op_net_x18',
5740 
          'to_register9_ce' => 'ce_1_sg',
5741 
          'to_register9_clk' => 'clk_1_sg',
5742 
          'to_register9_clr' => [
5743 
            'constant',
5744 
            '\'0\'',
5745 
          ],
5746 
          'to_register9_data_in' => 'reg03_td_net_x0',
5747 
          'to_register9_dout' => 'to_register9_dout_net',
5748 
          'to_register9_en' => 'constant5_op_net_x19',
5749 
        },
5750 
        'entityName' => 'inout_logic_cw',
5751 
        'nets' => {
5752 
          'ce_1_sg' => {
5753 
            'attributes' => {
5754 
              'hdlNetAttributes' => [
5755 
                [
5756 
                  'MAX_FANOUT',
5757 
                  'string',
5758 
                  '"REDUCE"',
5759 
                ],
5760 
              ],
5761 
            },
5762 
            'hdlType' => 'std_logic',
5763 
            'width' => 1,
5764 
          },
5765 
          'clkNet' => {
5766 
            'attributes' => {
5767 
              'hdlNetAttributes' => [],
5768 
            },
5769 
            'hdlType' => 'std_logic',
5770 
            'width' => 1,
5771 
          },
5772 
          'clk_1_sg' => {
5773 
            'attributes' => {
5774 
              'hdlNetAttributes' => [],
5775 
            },
5776 
            'hdlType' => 'std_logic',
5777 
            'width' => 1,
5778 
          },
5779 
          'constant1_op_net_x0' => {
5780 
            'attributes' => {
5781 
              'hdlNetAttributes' => [],
5782 
            },
5783 
            'hdlType' => 'std_logic',
5784 
            'width' => 1,
5785 
          },
5786 
          'constant1_op_net_x1' => {
5787 
            'attributes' => {
5788 
              'hdlNetAttributes' => [],
5789 
            },
5790 
            'hdlType' => 'std_logic',
5791 
            'width' => 1,
5792 
          },
5793 
          'constant1_op_net_x10' => {
5794 
            'attributes' => {
5795 
              'hdlNetAttributes' => [],
5796 
            },
5797 
            'hdlType' => 'std_logic',
5798 
            'width' => 1,
5799 
          },
5800 
          'constant1_op_net_x11' => {
5801 
            'attributes' => {
5802 
              'hdlNetAttributes' => [],
5803 
            },
5804 
            'hdlType' => 'std_logic',
5805 
            'width' => 1,
5806 
          },
5807 
          'constant1_op_net_x12' => {
5808 
            'attributes' => {
5809 
              'hdlNetAttributes' => [],
5810 
            },
5811 
            'hdlType' => 'std_logic',
5812 
            'width' => 1,
5813 
          },
5814 
          'constant1_op_net_x13' => {
5815 
            'attributes' => {
5816 
              'hdlNetAttributes' => [],
5817 
            },
5818 
            'hdlType' => 'std_logic',
5819 
            'width' => 1,
5820 
          },
5821 
          'constant1_op_net_x2' => {
5822 
            'attributes' => {
5823 
              'hdlNetAttributes' => [],
5824 
            },
5825 
            'hdlType' => 'std_logic',
5826 
            'width' => 1,
5827 
          },
5828 
          'constant1_op_net_x3' => {
5829 
            'attributes' => {
5830 
              'hdlNetAttributes' => [],
5831 
            },
5832 
            'hdlType' => 'std_logic',
5833 
            'width' => 1,
5834 
          },
5835 
          'constant1_op_net_x4' => {
5836 
            'attributes' => {
5837 
              'hdlNetAttributes' => [],
5838 
            },
5839 
            'hdlType' => 'std_logic',
5840 
            'width' => 1,
5841 
          },
5842 
          'constant1_op_net_x5' => {
5843 
            'attributes' => {
5844 
              'hdlNetAttributes' => [],
5845 
            },
5846 
            'hdlType' => 'std_logic',
5847 
            'width' => 1,
5848 
          },
5849 
          'constant1_op_net_x6' => {
5850 
            'attributes' => {
5851 
              'hdlNetAttributes' => [],
5852 
            },
5853 
            'hdlType' => 'std_logic',
5854 
            'width' => 1,
5855 
          },
5856 
          'constant1_op_net_x7' => {
5857 
            'attributes' => {
5858 
              'hdlNetAttributes' => [],
5859 
            },
5860 
            'hdlType' => 'std_logic',
5861 
            'width' => 1,
5862 
          },
5863 
          'constant1_op_net_x8' => {
5864 
            'attributes' => {
5865 
              'hdlNetAttributes' => [],
5866 
            },
5867 
            'hdlType' => 'std_logic',
5868 
            'width' => 1,
5869 
          },
5870 
          'constant1_op_net_x9' => {
5871 
            'attributes' => {
5872 
              'hdlNetAttributes' => [],
5873 
            },
5874 
            'hdlType' => 'std_logic',
5875 
            'width' => 1,
5876 
          },
5877 
          'constant5_op_net_x0' => {
5878 
            'attributes' => {
5879 
              'hdlNetAttributes' => [],
5880 
            },
5881 
            'hdlType' => 'std_logic',
5882 
            'width' => 1,
5883 
          },
5884 
          'constant5_op_net_x1' => {
5885 
            'attributes' => {
5886 
              'hdlNetAttributes' => [],
5887 
            },
5888 
            'hdlType' => 'std_logic',
5889 
            'width' => 1,
5890 
          },
5891 
          'constant5_op_net_x10' => {
5892 
            'attributes' => {
5893 
              'hdlNetAttributes' => [],
5894 
            },
5895 
            'hdlType' => 'std_logic',
5896 
            'width' => 1,
5897 
          },
5898 
          'constant5_op_net_x11' => {
5899 
            'attributes' => {
5900 
              'hdlNetAttributes' => [],
5901 
            },
5902 
            'hdlType' => 'std_logic',
5903 
            'width' => 1,
5904 
          },
5905 
          'constant5_op_net_x12' => {
5906 
            'attributes' => {
5907 
              'hdlNetAttributes' => [],
5908 
            },
5909 
            'hdlType' => 'std_logic',
5910 
            'width' => 1,
5911 
          },
5912 
          'constant5_op_net_x13' => {
5913 
            'attributes' => {
5914 
              'hdlNetAttributes' => [],
5915 
            },
5916 
            'hdlType' => 'std_logic',
5917 
            'width' => 1,
5918 
          },
5919 
          'constant5_op_net_x14' => {
5920 
            'attributes' => {
5921 
              'hdlNetAttributes' => [],
5922 
            },
5923 
            'hdlType' => 'std_logic',
5924 
            'width' => 1,
5925 
          },
5926 
          'constant5_op_net_x15' => {
5927 
            'attributes' => {
5928 
              'hdlNetAttributes' => [],
5929 
            },
5930 
            'hdlType' => 'std_logic',
5931 
            'width' => 1,
5932 
          },
5933 
          'constant5_op_net_x16' => {
5934 
            'attributes' => {
5935 
              'hdlNetAttributes' => [],
5936 
            },
5937 
            'hdlType' => 'std_logic',
5938 
            'width' => 1,
5939 
          },
5940 
          'constant5_op_net_x17' => {
5941 
            'attributes' => {
5942 
              'hdlNetAttributes' => [],
5943 
            },
5944 
            'hdlType' => 'std_logic',
5945 
            'width' => 1,
5946 
          },
5947 
          'constant5_op_net_x18' => {
5948 
            'attributes' => {
5949 
              'hdlNetAttributes' => [],
5950 
            },
5951 
            'hdlType' => 'std_logic',
5952 
            'width' => 1,
5953 
          },
5954 
          'constant5_op_net_x19' => {
5955 
            'attributes' => {
5956 
              'hdlNetAttributes' => [],
5957 
            },
5958 
            'hdlType' => 'std_logic',
5959 
            'width' => 1,
5960 
          },
5961 
          'constant5_op_net_x2' => {
5962 
            'attributes' => {
5963 
              'hdlNetAttributes' => [],
5964 
            },
5965 
            'hdlType' => 'std_logic',
5966 
            'width' => 1,
5967 
          },
5968 
          'constant5_op_net_x3' => {
5969 
            'attributes' => {
5970 
              'hdlNetAttributes' => [],
5971 
            },
5972 
            'hdlType' => 'std_logic',
5973 
            'width' => 1,
5974 
          },
5975 
          'constant5_op_net_x4' => {
5976 
            'attributes' => {
5977 
              'hdlNetAttributes' => [],
5978 
            },
5979 
            'hdlType' => 'std_logic',
5980 
            'width' => 1,
5981 
          },
5982 
          'constant5_op_net_x5' => {
5983 
            'attributes' => {
5984 
              'hdlNetAttributes' => [],
5985 
            },
5986 
            'hdlType' => 'std_logic',
5987 
            'width' => 1,
5988 
          },
5989 
          'constant5_op_net_x6' => {
5990 
            'attributes' => {
5991 
              'hdlNetAttributes' => [],
5992 
            },
5993 
            'hdlType' => 'std_logic',
5994 
            'width' => 1,
5995 
          },
5996 
          'constant5_op_net_x7' => {
5997 
            'attributes' => {
5998 
              'hdlNetAttributes' => [],
5999 
            },
6000 
            'hdlType' => 'std_logic',
6001 
            'width' => 1,
6002 
          },
6003 
          'constant5_op_net_x8' => {
6004 
            'attributes' => {
6005 
              'hdlNetAttributes' => [],
6006 
            },
6007 
            'hdlType' => 'std_logic',
6008 
            'width' => 1,
6009 
          },
6010 
          'constant5_op_net_x9' => {
6011 
            'attributes' => {
6012 
              'hdlNetAttributes' => [],
6013 
            },
6014 
            'hdlType' => 'std_logic',
6015 
            'width' => 1,
6016 
          },
6017 
          'debug_in_1i_net' => {
6018 
            'attributes' => {
6019 
              'hdlNetAttributes' => [],
6020 
            },
6021 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6022 
            'width' => 32,
6023 
          },
6024 
          'debug_in_1i_net_x0' => {
6025 
            'attributes' => {
6026 
              'hdlNetAttributes' => [],
6027 
            },
6028 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6029 
            'width' => 32,
6030 
          },
6031 
          'debug_in_2i_net' => {
6032 
            'attributes' => {
6033 
              'hdlNetAttributes' => [],
6034 
            },
6035 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6036 
            'width' => 32,
6037 
          },
6038 
          'debug_in_2i_net_x0' => {
6039 
            'attributes' => {
6040 
              'hdlNetAttributes' => [],
6041 
            },
6042 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6043 
            'width' => 32,
6044 
          },
6045 
          'debug_in_3i_net' => {
6046 
            'attributes' => {
6047 
              'hdlNetAttributes' => [],
6048 
            },
6049 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6050 
            'width' => 32,
6051 
          },
6052 
          'debug_in_3i_net_x0' => {
6053 
            'attributes' => {
6054 
              'hdlNetAttributes' => [],
6055 
            },
6056 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6057 
            'width' => 32,
6058 
          },
6059 
          'debug_in_4i_net' => {
6060 
            'attributes' => {
6061 
              'hdlNetAttributes' => [],
6062 
            },
6063 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6064 
            'width' => 32,
6065 
          },
6066 
          'debug_in_4i_net_x0' => {
6067 
            'attributes' => {
6068 
              'hdlNetAttributes' => [],
6069 
            },
6070 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6071 
            'width' => 32,
6072 
          },
6073 
          'dma_host2board_busy_net' => {
6074 
            'attributes' => {
6075 
              'hdlNetAttributes' => [],
6076 
            },
6077 
            'hdlType' => 'std_logic',
6078 
            'width' => 1,
6079 
          },
6080 
          'dma_host2board_busy_net_x0' => {
6081 
            'attributes' => {
6082 
              'hdlNetAttributes' => [],
6083 
            },
6084 
            'hdlType' => 'std_logic',
6085 
            'width' => 1,
6086 
          },
6087 
          'dma_host2board_done_net' => {
6088 
            'attributes' => {
6089 
              'hdlNetAttributes' => [],
6090 
            },
6091 
            'hdlType' => 'std_logic',
6092 
            'width' => 1,
6093 
          },
6094 
          'dma_host2board_done_net_x0' => {
6095 
            'attributes' => {
6096 
              'hdlNetAttributes' => [],
6097 
            },
6098 
            'hdlType' => 'std_logic',
6099 
            'width' => 1,
6100 
          },
6101 
          'from_register10_data_out_net' => {
6102 
            'attributes' => {
6103 
              'hdlNetAttributes' => [],
6104 
            },
6105 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6106 
            'width' => 32,
6107 
          },
6108 
          'from_register10_data_out_net_x0' => {
6109 
            'attributes' => {
6110 
              'hdlNetAttributes' => [],
6111 
            },
6112 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6113 
            'width' => 32,
6114 
          },
6115 
          'from_register11_data_out_net' => {
6116 
            'attributes' => {
6117 
              'hdlNetAttributes' => [],
6118 
            },
6119 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6120 
            'width' => 32,
6121 
          },
6122 
          'from_register11_data_out_net_x0' => {
6123 
            'attributes' => {
6124 
              'hdlNetAttributes' => [],
6125 
            },
6126 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6127 
            'width' => 32,
6128 
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              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register3/dout',
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11060 
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11099 
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11100 
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11112 
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11113 
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11114 
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11119 
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11142 
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11168 
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11224 
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11250 
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11254 
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11258 
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11260 
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11261 
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11262 
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11263 
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11264 
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11265 
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11267 
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11290 
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11291 
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11294 
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11295 
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11297 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register7/en',
11298 
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11299 
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11301 
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11306 
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11313 
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11315 
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11316 
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11317 
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11318 
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11319 
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11320 
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11321 
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11322 
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11323 
              'period' => 1,
11324 
              'type' => 'logic',
11325 
            },
11326 
            'direction' => 'out',
11327 
            'hdlType' => 'std_logic',
11328 
            'width' => 1,
11329 
          },
11330 
          'to_register8_clr' => {
11331 
            'attributes' => {
11332 
              'domain' => '',
11333 
              'group' => 1,
11334 
              'isClr' => 1,
11335 
              'is_floating_block' => 1,
11336 
              'period' => 1,
11337 
              'type' => 'logic',
11338 
              'valid_bit_used' => 0,
11339 
            },
11340 
            'direction' => 'out',
11341 
            'hdlType' => 'std_logic',
11342 
            'width' => 1,
11343 
          },
11344 
          'to_register8_data_in' => {
11345 
            'attributes' => {
11346 
              'bin_pt' => 0,
11347 
              'is_floating_block' => 1,
11348 
              'must_be_hdl_vector' => 1,
11349 
              'period' => 1,
11350 
              'port_id' => 0,
11351 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
11352 
              'type' => 'Bool',
11353 
            },
11354 
            'direction' => 'out',
11355 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11356 
            'width' => 1,
11357 
          },
11358 
          'to_register8_dout' => {
11359 
            'attributes' => {
11360 
              'bin_pt' => 0,
11361 
              'is_floating_block' => 1,
11362 
              'must_be_hdl_vector' => 1,
11363 
              'period' => 1,
11364 
              'port_id' => 0,
11365 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
11366 
              'type' => 'Bool',
11367 
            },
11368 
            'direction' => 'in',
11369 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11370 
            'width' => 1,
11371 
          },
11372 
          'to_register8_en' => {
11373 
            'attributes' => {
11374 
              'bin_pt' => 0,
11375 
              'is_floating_block' => 1,
11376 
              'must_be_hdl_vector' => 1,
11377 
              'period' => 1,
11378 
              'port_id' => 1,
11379 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
11380 
              'type' => 'Bool',
11381 
            },
11382 
            'direction' => 'out',
11383 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11384 
            'width' => 1,
11385 
          },
11386 
          'to_register9_ce' => {
11387 
            'attributes' => {
11388 
              'domain' => '',
11389 
              'group' => 1,
11390 
              'isCe' => 1,
11391 
              'is_floating_block' => 1,
11392 
              'period' => 1,
11393 
              'type' => 'logic',
11394 
            },
11395 
            'direction' => 'out',
11396 
            'hdlType' => 'std_logic',
11397 
            'width' => 1,
11398 
          },
11399 
          'to_register9_clk' => {
11400 
            'attributes' => {
11401 
              'domain' => '',
11402 
              'group' => 1,
11403 
              'isClk' => 1,
11404 
              'is_floating_block' => 1,
11405 
              'period' => 1,
11406 
              'type' => 'logic',
11407 
            },
11408 
            'direction' => 'out',
11409 
            'hdlType' => 'std_logic',
11410 
            'width' => 1,
11411 
          },
11412 
          'to_register9_clr' => {
11413 
            'attributes' => {
11414 
              'domain' => '',
11415 
              'group' => 1,
11416 
              'isClr' => 1,
11417 
              'is_floating_block' => 1,
11418 
              'period' => 1,
11419 
              'type' => 'logic',
11420 
              'valid_bit_used' => 0,
11421 
            },
11422 
            'direction' => 'out',
11423 
            'hdlType' => 'std_logic',
11424 
            'width' => 1,
11425 
          },
11426 
          'to_register9_data_in' => {
11427 
            'attributes' => {
11428 
              'bin_pt' => 0,
11429 
              'is_floating_block' => 1,
11430 
              'must_be_hdl_vector' => 1,
11431 
              'period' => 1,
11432 
              'port_id' => 0,
11433 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
11434 
              'type' => 'UFix_32_0',
11435 
            },
11436 
            'direction' => 'out',
11437 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11438 
            'width' => 32,
11439 
          },
11440 
          'to_register9_dout' => {
11441 
            'attributes' => {
11442 
              'bin_pt' => 0,
11443 
              'is_floating_block' => 1,
11444 
              'must_be_hdl_vector' => 1,
11445 
              'period' => 1,
11446 
              'port_id' => 0,
11447 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
11448 
              'type' => 'UFix_32_0',
11449 
            },
11450 
            'direction' => 'in',
11451 
            'hdlType' => 'std_logic_vector(31 downto 0)',
11452 
            'width' => 32,
11453 
          },
11454 
          'to_register9_en' => {
11455 
            'attributes' => {
11456 
              'bin_pt' => 0,
11457 
              'is_floating_block' => 1,
11458 
              'must_be_hdl_vector' => 1,
11459 
              'period' => 1,
11460 
              'port_id' => 1,
11461 
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
11462 
              'type' => 'Bool',
11463 
            },
11464 
            'direction' => 'out',
11465 
            'hdlType' => 'std_logic_vector(0 downto 0)',
11466 
            'width' => 1,
11467 
          },
11468 
        },
11469 
        'subblocks' => {
11470 
          'default_clock_driver_x0' => {
11471 
            'connections' => {
11472 
              'ce_1' => 'ce_1_sg',
11473 
              'clk_1' => 'clk_1_sg',
11474 
              'sysce' => [
11475 
                'constant',
11476 
                '\'1\'',
11477 
              ],
11478 
              'sysce_clr' => [
11479 
                'constant',
11480 
                '\'0\'',
11481 
              ],
11482 
              'sysclk' => 'clkNet',
11483 
            },
11484 
            'entity' => {
11485 
              'attributes' => {
11486 
                'domain' => 'default',
11487 
                'hdlArchAttributes' => [
11488 
                  [
11489 
                    'syn_noprune',
11490 
                    'boolean',
11491 
                    'true',
11492 
                  ],
11493 
                  [
11494 
                    'optimize_primitives',
11495 
                    'boolean',
11496 
                    'false',
11497 
                  ],
11498 
                  [
11499 
                    'dont_touch',
11500 
                    'boolean',
11501 
                    'true',
11502 
                  ],
11503 
                ],
11504 
                'hdlEntityAttributes' => [],
11505 
                'isClkDriver' => 1,
11506 
              },
11507 
              'entityName' => 'default_clock_driver',
11508 
              'ports' => {
11509 
                'ce_1' => {
11510 
                  'attributes' => {
11511 
                    'domain' => 'default',
11512 
                    'group' => 1,
11513 
                    'isCe' => 1,
11514 
                    'period' => 1,
11515 
                    'type' => 'logic',
11516 
                  },
11517 
                  'direction' => 'out',
11518 
                  'hdlType' => 'std_logic',
11519 
                  'width' => 1,
11520 
                },
11521 
                'clk_1' => {
11522 
                  'attributes' => {
11523 
                    'domain' => 'default',
11524 
                    'group' => 1,
11525 
                    'isClk' => 1,
11526 
                    'period' => 1,
11527 
                    'type' => 'logic',
11528 
                  },
11529 
                  'direction' => 'out',
11530 
                  'hdlType' => 'std_logic',
11531 
                  'width' => 1,
11532 
                },
11533 
                'sysce' => {
11534 
                  'attributes' => {
11535 
                    'group' => 4,
11536 
                    'isCe' => 1,
11537 
                    'period' => 1,
11538 
                  },
11539 
                  'direction' => 'in',
11540 
                  'hdlType' => 'std_logic',
11541 
                  'width' => 1,
11542 
                },
11543 
                'sysce_clr' => {
11544 
                  'attributes' => {
11545 
                    'group' => 4,
11546 
                    'isClr' => 1,
11547 
                    'period' => 1,
11548 
                  },
11549 
                  'direction' => 'in',
11550 
                  'hdlType' => 'std_logic',
11551 
                  'width' => 1,
11552 
                },
11553 
                'sysclk' => {
11554 
                  'attributes' => {
11555 
                    'group' => 4,
11556 
                    'isClk' => 1,
11557 
                    'period' => 1,
11558 
                  },
11559 
                  'direction' => 'in',
11560 
                  'hdlType' => 'std_logic',
11561 
                  'width' => 1,
11562 
                },
11563 
              },
11564 
            },
11565 
            'entityName' => 'default_clock_driver',
11566 
          },
11567 
          'inout_logic_x0' => {
11568 
            'connections' => {
11569 
              'data_in' => 'debug_in_2i_net_x0',
11570 
              'data_in_x0' => 'reg04_tv_net_x0',
11571 
              'data_in_x1' => 'reg04_td_net_x0',
11572 
              'data_in_x10' => 'debug_in_3i_net_x0',
11573 
              'data_in_x11' => 'debug_in_4i_net_x0',
11574 
              'data_in_x12' => 'reg09_tv_net_x0',
11575 
              'data_in_x13' => 'reg09_td_net_x0',
11576 
              'data_in_x14' => 'reg10_tv_net_x0',
11577 
              'data_in_x15' => 'reg10_td_net_x0',
11578 
              'data_in_x16' => 'reg08_tv_net_x0',
11579 
              'data_in_x17' => 'reg08_td_net_x0',
11580 
              'data_in_x18' => 'reg11_tv_net_x0',
11581 
              'data_in_x19' => 'reg11_td_net_x0',
11582 
              'data_in_x2' => 'reg05_tv_net_x0',
11583 
              'data_in_x20' => 'reg12_tv_net_x0',
11584 
              'data_in_x21' => 'reg01_tv_net_x0',
11585 
              'data_in_x22' => 'reg12_td_net_x0',
11586 
              'data_in_x23' => 'reg13_tv_net_x0',
11587 
              'data_in_x24' => 'reg13_td_net_x0',
11588 
              'data_in_x25' => 'reg14_tv_net_x0',
11589 
              'data_in_x26' => 'reg14_td_net_x0',
11590 
              'data_in_x27' => 'reg02_tv_net_x0',
11591 
              'data_in_x28' => 'reg02_td_net_x0',
11592 
              'data_in_x29' => 'debug_in_1i_net_x0',
11593 
              'data_in_x3' => 'reg05_td_net_x0',
11594 
              'data_in_x30' => 'reg01_td_net_x0',
11595 
              'data_in_x31' => 'reg03_tv_net_x0',
11596 
              'data_in_x32' => 'reg03_td_net_x0',
11597 
              'data_in_x4' => 'reg06_tv_net_x0',
11598 
              'data_in_x5' => 'reg06_td_net_x0',
11599 
              'data_in_x6' => 'reg07_tv_net_x0',
11600 
              'data_in_x7' => 'reg07_td_net_x0',
11601 
              'data_in_x8' => 'dma_host2board_busy_net_x0',
11602 
              'data_in_x9' => 'dma_host2board_done_net_x0',
11603 
              'data_out' => 'from_register1_data_out_net',
11604 
              'data_out_x0' => 'from_register10_data_out_net',
11605 
              'data_out_x1' => 'from_register11_data_out_net',
11606 
              'data_out_x10' => 'from_register2_data_out_net',
11607 
              'data_out_x11' => 'from_register20_data_out_net',
11608 
              'data_out_x12' => 'from_register21_data_out_net',
11609 
              'data_out_x13' => 'from_register22_data_out_net',
11610 
              'data_out_x14' => 'from_register23_data_out_net',
11611 
              'data_out_x15' => 'from_register24_data_out_net',
11612 
              'data_out_x16' => 'from_register25_data_out_net',
11613 
              'data_out_x17' => 'from_register26_data_out_net',
11614 
              'data_out_x18' => 'from_register27_data_out_net',
11615 
              'data_out_x19' => 'from_register28_data_out_net',
11616 
              'data_out_x2' => 'from_register12_data_out_net',
11617 
              'data_out_x20' => 'from_register3_data_out_net',
11618 
              'data_out_x21' => 'from_register4_data_out_net',
11619 
              'data_out_x22' => 'from_register5_data_out_net',
11620 
              'data_out_x23' => 'from_register6_data_out_net',
11621 
              'data_out_x24' => 'from_register7_data_out_net',
11622 
              'data_out_x25' => 'from_register8_data_out_net',
11623 
              'data_out_x26' => 'from_register9_data_out_net',
11624 
              'data_out_x3' => 'from_register13_data_out_net',
11625 
              'data_out_x4' => 'from_register14_data_out_net',
11626 
              'data_out_x5' => 'from_register15_data_out_net',
11627 
              'data_out_x6' => 'from_register16_data_out_net',
11628 
              'data_out_x7' => 'from_register17_data_out_net',
11629 
              'data_out_x8' => 'from_register18_data_out_net',
11630 
              'data_out_x9' => 'from_register19_data_out_net',
11631 
              'debug_in_1i' => 'debug_in_1i_net',
11632 
              'debug_in_2i' => 'debug_in_2i_net',
11633 
              'debug_in_3i' => 'debug_in_3i_net',
11634 
              'debug_in_4i' => 'debug_in_4i_net',
11635 
              'dma_host2board_busy' => 'dma_host2board_busy_net',
11636 
              'dma_host2board_done' => 'dma_host2board_done_net',
11637 
              'en' => 'constant5_op_net_x0',
11638 
              'en_x0' => 'constant5_op_net_x1',
11639 
              'en_x1' => 'constant5_op_net_x2',
11640 
              'en_x10' => 'constant5_op_net_x11',
11641 
              'en_x11' => 'constant5_op_net_x12',
11642 
              'en_x12' => 'constant1_op_net_x0',
11643 
              'en_x13' => 'constant1_op_net_x1',
11644 
              'en_x14' => 'constant1_op_net_x2',
11645 
              'en_x15' => 'constant1_op_net_x3',
11646 
              'en_x16' => 'constant1_op_net_x4',
11647 
              'en_x17' => 'constant1_op_net_x5',
11648 
              'en_x18' => 'constant1_op_net_x6',
11649 
              'en_x19' => 'constant1_op_net_x7',
11650 
              'en_x2' => 'constant5_op_net_x3',
11651 
              'en_x20' => 'constant1_op_net_x8',
11652 
              'en_x21' => 'constant5_op_net_x13',
11653 
              'en_x22' => 'constant1_op_net_x9',
11654 
              'en_x23' => 'constant1_op_net_x10',
11655 
              'en_x24' => 'constant1_op_net_x11',
11656 
              'en_x25' => 'constant1_op_net_x12',
11657 
              'en_x26' => 'constant1_op_net_x13',
11658 
              'en_x27' => 'constant5_op_net_x14',
11659 
              'en_x28' => 'constant5_op_net_x15',
11660 
              'en_x29' => 'constant5_op_net_x16',
11661 
              'en_x3' => 'constant5_op_net_x4',
11662 
              'en_x30' => 'constant5_op_net_x17',
11663 
              'en_x31' => 'constant5_op_net_x18',
11664 
              'en_x32' => 'constant5_op_net_x19',
11665 
              'en_x4' => 'constant5_op_net_x5',
11666 
              'en_x5' => 'constant5_op_net_x6',
11667 
              'en_x6' => 'constant5_op_net_x7',
11668 
              'en_x7' => 'constant5_op_net_x8',
11669 
              'en_x8' => 'constant5_op_net_x9',
11670 
              'en_x9' => 'constant5_op_net_x10',
11671 
              'reg01_rd' => 'from_register3_data_out_net_x0',
11672 
              'reg01_rv' => 'from_register1_data_out_net_x0',
11673 
              'reg01_td' => 'reg01_td_net',
11674 
              'reg01_tv' => 'reg01_tv_net',
11675 
              'reg02_rd' => 'from_register5_data_out_net_x0',
11676 
              'reg02_rv' => 'from_register2_data_out_net_x0',
11677 
              'reg02_td' => 'reg02_td_net',
11678 
              'reg02_tv' => 'reg02_tv_net',
11679 
              'reg03_rd' => 'from_register7_data_out_net_x0',
11680 
              'reg03_rv' => 'from_register6_data_out_net_x0',
11681 
              'reg03_td' => 'reg03_td_net',
11682 
              'reg03_tv' => 'reg03_tv_net',
11683 
              'reg04_rd' => 'from_register8_data_out_net_x0',
11684 
              'reg04_rv' => 'from_register4_data_out_net_x0',
11685 
              'reg04_td' => 'reg04_td_net',
11686 
              'reg04_tv' => 'reg04_tv_net',
11687 
              'reg05_rd' => 'from_register10_data_out_net_x0',
11688 
              'reg05_rv' => 'from_register9_data_out_net_x0',
11689 
              'reg05_td' => 'reg05_td_net',
11690 
              'reg05_tv' => 'reg05_tv_net',
11691 
              'reg06_rd' => 'from_register11_data_out_net_x0',
11692 
              'reg06_rv' => 'from_register12_data_out_net_x0',
11693 
              'reg06_td' => 'reg06_td_net',
11694 
              'reg06_tv' => 'reg06_tv_net',
11695 
              'reg07_rd' => 'from_register13_data_out_net_x0',
11696 
              'reg07_rv' => 'from_register14_data_out_net_x0',
11697 
              'reg07_td' => 'reg07_td_net',
11698 
              'reg07_tv' => 'reg07_tv_net',
11699 
              'reg08_rd' => 'from_register15_data_out_net_x0',
11700 
              'reg08_rv' => 'from_register16_data_out_net_x0',
11701 
              'reg08_td' => 'reg08_td_net',
11702 
              'reg08_tv' => 'reg08_tv_net',
11703 
              'reg09_rd' => 'from_register17_data_out_net_x0',
11704 
              'reg09_rv' => 'from_register18_data_out_net_x0',
11705 
              'reg09_td' => 'reg09_td_net',
11706 
              'reg09_tv' => 'reg09_tv_net',
11707 
              'reg10_rd' => 'from_register19_data_out_net_x0',
11708 
              'reg10_rv' => 'from_register20_data_out_net_x0',
11709 
              'reg10_td' => 'reg10_td_net',
11710 
              'reg10_tv' => 'reg10_tv_net',
11711 
              'reg11_rd' => 'from_register21_data_out_net_x0',
11712 
              'reg11_rv' => 'from_register22_data_out_net_x0',
11713 
              'reg11_td' => 'reg11_td_net',
11714 
              'reg11_tv' => 'reg11_tv_net',
11715 
              'reg12_rd' => 'from_register23_data_out_net_x0',
11716 
              'reg12_rv' => 'from_register24_data_out_net_x0',
11717 
              'reg12_td' => 'reg12_td_net',
11718 
              'reg12_tv' => 'reg12_tv_net',
11719 
              'reg13_rd' => 'from_register25_data_out_net_x0',
11720 
              'reg13_rv' => 'from_register26_data_out_net_x0',
11721 
              'reg13_td' => 'reg13_td_net',
11722 
              'reg13_tv' => 'reg13_tv_net',
11723 
              'reg14_rd' => 'from_register27_data_out_net_x0',
11724 
              'reg14_rv' => 'from_register28_data_out_net_x0',
11725 
              'reg14_td' => 'reg14_td_net',
11726 
              'reg14_tv' => 'reg14_tv_net',
11727 
            },
11728 
            'entity' => {
11729 
              'attributes' => {
11730 
                'entityAlreadyNetlisted' => 1,
11731 
                'hdlKind' => 'vhdl',
11732 
                'isDesign' => 1,
11733 
                'simulinkName' => 'INOUT_LOGIC',
11734 
              },
11735 
              'entityName' => 'inout_logic',
11736 
              'ports' => {
11737 
                'data_in' => {
11738 
                  'attributes' => {
11739 
                    'bin_pt' => 0,
11740 
                    'is_floating_block' => 1,
11741 
                    'must_be_hdl_vector' => 1,
11742 
                    'period' => 1,
11743 
                    'port_id' => 0,
11744 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11745 
                    'type' => 'UFix_32_0',
11746 
                  },
11747 
                  'direction' => 'out',
11748 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11749 
                  'width' => 32,
11750 
                },
11751 
                'data_in_x0' => {
11752 
                  'attributes' => {
11753 
                    'bin_pt' => 0,
11754 
                    'is_floating_block' => 1,
11755 
                    'must_be_hdl_vector' => 1,
11756 
                    'period' => 1,
11757 
                    'port_id' => 0,
11758 
                    'simulinkName' => 'INOUT_LOGIC/data_in',
11759 
                    'type' => 'Bool',
11760 
                  },
11761 
                  'direction' => 'out',
11762 
                  'hdlType' => 'std_logic',
11763 
                  'width' => 1,
11764 
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14203 
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14212 
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}

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