OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [synopsis.1] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
{
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      'hdlType' => 'std_logic',
445 
      'width' => 1,
446 
    },
447 
    'constant6_op_net_x20' => {
448 
      'hdlType' => 'std_logic',
449 
      'width' => 1,
450 
    },
451 
    'constant6_op_net_x21' => {
452 
      'hdlType' => 'std_logic',
453 
      'width' => 1,
454 
    },
455 
    'constant6_op_net_x22' => {
456 
      'hdlType' => 'std_logic',
457 
      'width' => 1,
458 
    },
459 
    'constant6_op_net_x23' => {
460 
      'hdlType' => 'std_logic',
461 
      'width' => 1,
462 
    },
463 
    'constant6_op_net_x24' => {
464 
      'hdlType' => 'std_logic',
465 
      'width' => 1,
466 
    },
467 
    'constant6_op_net_x25' => {
468 
      'hdlType' => 'std_logic',
469 
      'width' => 1,
470 
    },
471 
    'constant6_op_net_x26' => {
472 
      'hdlType' => 'std_logic',
473 
      'width' => 1,
474 
    },
475 
    'constant6_op_net_x27' => {
476 
      'hdlType' => 'std_logic',
477 
      'width' => 1,
478 
    },
479 
    'constant6_op_net_x3' => {
480 
      'hdlType' => 'std_logic',
481 
      'width' => 1,
482 
    },
483 
    'constant6_op_net_x4' => {
484 
      'hdlType' => 'std_logic',
485 
      'width' => 1,
486 
    },
487 
    'constant6_op_net_x5' => {
488 
      'hdlType' => 'std_logic',
489 
      'width' => 1,
490 
    },
491 
    'constant6_op_net_x6' => {
492 
      'hdlType' => 'std_logic',
493 
      'width' => 1,
494 
    },
495 
    'constant6_op_net_x7' => {
496 
      'hdlType' => 'std_logic',
497 
      'width' => 1,
498 
    },
499 
    'constant6_op_net_x8' => {
500 
      'hdlType' => 'std_logic',
501 
      'width' => 1,
502 
    },
503 
    'constant6_op_net_x9' => {
504 
      'hdlType' => 'std_logic',
505 
      'width' => 1,
506 
    },
507 
    'data_in_net' => {
508 
      'hdlType' => 'std_logic_vector(31 downto 0)',
509 
      'width' => 32,
510 
    },
511 
    'data_in_x0_net' => {
512 
      'hdlType' => 'std_logic',
513 
      'width' => 1,
514 
    },
515 
    'data_in_x10_net' => {
516 
      'hdlType' => 'std_logic_vector(31 downto 0)',
517 
      'width' => 32,
518 
    },
519 
    'data_in_x11_net' => {
520 
      'hdlType' => 'std_logic_vector(31 downto 0)',
521 
      'width' => 32,
522 
    },
523 
    'data_in_x12_net' => {
524 
      'hdlType' => 'std_logic',
525 
      'width' => 1,
526 
    },
527 
    'data_in_x13_net' => {
528 
      'hdlType' => 'std_logic_vector(31 downto 0)',
529 
      'width' => 32,
530 
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531 
    'data_in_x14_net' => {
532 
      'hdlType' => 'std_logic',
533 
      'width' => 1,
534 
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535 
    'data_in_x15_net' => {
536 
      'hdlType' => 'std_logic_vector(31 downto 0)',
537 
      'width' => 32,
538 
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539 
    'data_in_x16_net' => {
540 
      'hdlType' => 'std_logic',
541 
      'width' => 1,
542 
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543 
    'data_in_x17_net' => {
544 
      'hdlType' => 'std_logic_vector(31 downto 0)',
545 
      'width' => 32,
546 
    },
547 
    'data_in_x18_net' => {
548 
      'hdlType' => 'std_logic',
549 
      'width' => 1,
550 
    },
551 
    'data_in_x19_net' => {
552 
      'hdlType' => 'std_logic_vector(31 downto 0)',
553 
      'width' => 32,
554 
    },
555 
    'data_in_x1_net' => {
556 
      'hdlType' => 'std_logic',
557 
      'width' => 1,
558 
    },
559 
    'data_in_x20_net' => {
560 
      'hdlType' => 'std_logic_vector(31 downto 0)',
561 
      'width' => 32,
562 
    },
563 
    'data_in_x21_net' => {
564 
      'hdlType' => 'std_logic',
565 
      'width' => 1,
566 
    },
567 
    'data_in_x22_net' => {
568 
      'hdlType' => 'std_logic',
569 
      'width' => 1,
570 
    },
571 
    'data_in_x23_net' => {
572 
      'hdlType' => 'std_logic_vector(31 downto 0)',
573 
      'width' => 32,
574 
    },
575 
    'data_in_x24_net' => {
576 
      'hdlType' => 'std_logic',
577 
      'width' => 1,
578 
    },
579 
    'data_in_x25_net' => {
580 
      'hdlType' => 'std_logic_vector(31 downto 0)',
581 
      'width' => 32,
582 
    },
583 
    'data_in_x26_net' => {
584 
      'hdlType' => 'std_logic_vector(31 downto 0)',
585 
      'width' => 32,
586 
    },
587 
    'data_in_x2_net' => {
588 
      'hdlType' => 'std_logic',
589 
      'width' => 1,
590 
    },
591 
    'data_in_x3_net' => {
592 
      'hdlType' => 'std_logic',
593 
      'width' => 1,
594 
    },
595 
    'data_in_x4_net' => {
596 
      'hdlType' => 'std_logic_vector(31 downto 0)',
597 
      'width' => 32,
598 
    },
599 
    'data_in_x5_net' => {
600 
      'hdlType' => 'std_logic',
601 
      'width' => 1,
602 
    },
603 
    'data_in_x6_net' => {
604 
      'hdlType' => 'std_logic_vector(31 downto 0)',
605 
      'width' => 32,
606 
    },
607 
    'data_in_x7_net' => {
608 
      'hdlType' => 'std_logic',
609 
      'width' => 1,
610 
    },
611 
    'data_in_x8_net' => {
612 
      'hdlType' => 'std_logic_vector(31 downto 0)',
613 
      'width' => 32,
614 
    },
615 
    'data_in_x9_net' => {
616 
      'hdlType' => 'std_logic',
617 
      'width' => 1,
618 
    },
619 
    'data_out_x12_net' => {
620 
      'hdlType' => 'std_logic_vector(31 downto 0)',
621 
      'width' => 32,
622 
    },
623 
    'data_out_x13_net' => {
624 
      'hdlType' => 'std_logic',
625 
      'width' => 1,
626 
    },
627 
    'data_out_x14_net' => {
628 
      'hdlType' => 'std_logic_vector(31 downto 0)',
629 
      'width' => 32,
630 
    },
631 
    'data_out_x15_net' => {
632 
      'hdlType' => 'std_logic',
633 
      'width' => 1,
634 
    },
635 
    'data_out_x16_net' => {
636 
      'hdlType' => 'std_logic_vector(31 downto 0)',
637 
      'width' => 32,
638 
    },
639 
    'data_out_x17_net' => {
640 
      'hdlType' => 'std_logic',
641 
      'width' => 1,
642 
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643 
    'data_out_x18_net' => {
644 
      'hdlType' => 'std_logic_vector(31 downto 0)',
645 
      'width' => 32,
646 
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647 
    'data_out_x19_net' => {
648 
      'hdlType' => 'std_logic',
649 
      'width' => 1,
650 
    },
651 
    'data_out_x1_net' => {
652 
      'hdlType' => 'std_logic',
653 
      'width' => 1,
654 
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655 
    'data_out_x20_net' => {
656 
      'hdlType' => 'std_logic_vector(31 downto 0)',
657 
      'width' => 32,
658 
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659 
    'data_out_x21_net' => {
660 
      'hdlType' => 'std_logic',
661 
      'width' => 1,
662 
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663 
    'data_out_x22_net' => {
664 
      'hdlType' => 'std_logic_vector(31 downto 0)',
665 
      'width' => 32,
666 
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667 
    'data_out_x23_net' => {
668 
      'hdlType' => 'std_logic_vector(31 downto 0)',
669 
      'width' => 32,
670 
    },
671 
    'data_out_x24_net' => {
672 
      'hdlType' => 'std_logic',
673 
      'width' => 1,
674 
    },
675 
    'data_out_x25_net' => {
676 
      'hdlType' => 'std_logic_vector(31 downto 0)',
677 
      'width' => 32,
678 
    },
679 
    'data_out_x26_net' => {
680 
      'hdlType' => 'std_logic',
681 
      'width' => 1,
682 
    },
683 
    'data_out_x27_net' => {
684 
      'hdlType' => 'std_logic',
685 
      'width' => 1,
686 
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687 
    'data_out_x28_net' => {
688 
      'hdlType' => 'std_logic_vector(31 downto 0)',
689 
      'width' => 32,
690 
    },
691 
    'data_out_x29_net' => {
692 
      'hdlType' => 'std_logic',
693 
      'width' => 1,
694 
    },
695 
    'data_out_x2_net' => {
696 
      'hdlType' => 'std_logic_vector(31 downto 0)',
697 
      'width' => 32,
698 
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699 
    'data_out_x30_net' => {
700 
      'hdlType' => 'std_logic_vector(31 downto 0)',
701 
      'width' => 32,
702 
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703 
    'data_out_x31_net' => {
704 
      'hdlType' => 'std_logic',
705 
      'width' => 1,
706 
    },
707 
    'data_out_x32_net' => {
708 
      'hdlType' => 'std_logic_vector(31 downto 0)',
709 
      'width' => 32,
710 
    },
711 
    'data_out_x3_net' => {
712 
      'hdlType' => 'std_logic',
713 
      'width' => 1,
714 
    },
715 
    'data_out_x4_net' => {
716 
      'hdlType' => 'std_logic_vector(31 downto 0)',
717 
      'width' => 32,
718 
    },
719 
    'data_out_x5_net' => {
720 
      'hdlType' => 'std_logic',
721 
      'width' => 1,
722 
    },
723 
    'data_out_x8_net' => {
724 
      'hdlType' => 'std_logic_vector(31 downto 0)',
725 
      'width' => 32,
726 
    },
727 
    'data_out_x9_net' => {
728 
      'hdlType' => 'std_logic',
729 
      'width' => 1,
730 
    },
731 
    'fifo_rd_count_net' => {
732 
      'hdlType' => 'std_logic_vector(14 downto 0)',
733 
      'width' => 15,
734 
    },
735 
    'fifo_rd_dout_net' => {
736 
      'hdlType' => 'std_logic_vector(71 downto 0)',
737 
      'width' => 72,
738 
    },
739 
    'fifo_rd_empty_net' => {
740 
      'hdlType' => 'std_logic',
741 
      'width' => 1,
742 
    },
743 
    'fifo_rd_en_net' => {
744 
      'hdlType' => 'std_logic',
745 
      'width' => 1,
746 
    },
747 
    'fifo_rd_pempty_net' => {
748 
      'hdlType' => 'std_logic',
749 
      'width' => 1,
750 
    },
751 
    'fifo_rd_valid_net' => {
752 
      'hdlType' => 'std_logic',
753 
      'width' => 1,
754 
    },
755 
    'fifo_wr_count_net' => {
756 
      'hdlType' => 'std_logic_vector(14 downto 0)',
757 
      'width' => 15,
758 
    },
759 
    'fifo_wr_din_net' => {
760 
      'hdlType' => 'std_logic_vector(71 downto 0)',
761 
      'width' => 72,
762 
    },
763 
    'fifo_wr_en_net' => {
764 
      'hdlType' => 'std_logic',
765 
      'width' => 1,
766 
    },
767 
    'fifo_wr_full_net' => {
768 
      'hdlType' => 'std_logic',
769 
      'width' => 1,
770 
    },
771 
    'fifo_wr_pfull_net' => {
772 
      'hdlType' => 'std_logic',
773 
      'width' => 1,
774 
    },
775 
    'from_register15_data_out_net' => {
776 
      'hdlType' => 'std_logic',
777 
      'width' => 1,
778 
    },
779 
    'from_register16_data_out_net' => {
780 
      'hdlType' => 'std_logic',
781 
      'width' => 1,
782 
    },
783 
    'from_register19_data_out_net' => {
784 
      'hdlType' => 'std_logic_vector(31 downto 0)',
785 
      'width' => 32,
786 
    },
787 
    'from_register1_data_out_net' => {
788 
      'hdlType' => 'std_logic_vector(31 downto 0)',
789 
      'width' => 32,
790 
    },
791 
    'from_register2_data_out_net' => {
792 
      'hdlType' => 'std_logic_vector(31 downto 0)',
793 
      'width' => 32,
794 
    },
795 
    'from_register_data_out_net' => {
796 
      'hdlType' => 'std_logic_vector(31 downto 0)',
797 
      'width' => 32,
798 
    },
799 
    'rst_i_net' => {
800 
      'hdlType' => 'std_logic',
801 
      'width' => 1,
802 
    },
803 
    'rst_o_net' => {
804 
      'hdlType' => 'std_logic',
805 
      'width' => 1,
806 
    },
807 
    'to_register10_dout_net' => {
808 
      'hdlType' => 'std_logic',
809 
      'width' => 1,
810 
    },
811 
    'to_register11_dout_net' => {
812 
      'hdlType' => 'std_logic',
813 
      'width' => 1,
814 
    },
815 
    'to_register12_dout_net' => {
816 
      'hdlType' => 'std_logic',
817 
      'width' => 1,
818 
    },
819 
    'to_register13_dout_net' => {
820 
      'hdlType' => 'std_logic_vector(31 downto 0)',
821 
      'width' => 32,
822 
    },
823 
    'to_register14_dout_net' => {
824 
      'hdlType' => 'std_logic',
825 
      'width' => 1,
826 
    },
827 
    'to_register15_dout_net' => {
828 
      'hdlType' => 'std_logic_vector(31 downto 0)',
829 
      'width' => 32,
830 
    },
831 
    'to_register16_dout_net' => {
832 
      'hdlType' => 'std_logic',
833 
      'width' => 1,
834 
    },
835 
    'to_register17_dout_net' => {
836 
      'hdlType' => 'std_logic_vector(31 downto 0)',
837 
      'width' => 32,
838 
    },
839 
    'to_register18_dout_net' => {
840 
      'hdlType' => 'std_logic',
841 
      'width' => 1,
842 
    },
843 
    'to_register19_dout_net' => {
844 
      'hdlType' => 'std_logic_vector(31 downto 0)',
845 
      'width' => 32,
846 
    },
847 
    'to_register1_dout_net' => {
848 
      'hdlType' => 'std_logic',
849 
      'width' => 1,
850 
    },
851 
    'to_register20_dout_net' => {
852 
      'hdlType' => 'std_logic',
853 
      'width' => 1,
854 
    },
855 
    'to_register21_dout_net' => {
856 
      'hdlType' => 'std_logic_vector(31 downto 0)',
857 
      'width' => 32,
858 
    },
859 
    'to_register22_dout_net' => {
860 
      'hdlType' => 'std_logic',
861 
      'width' => 1,
862 
    },
863 
    'to_register23_dout_net' => {
864 
      'hdlType' => 'std_logic_vector(31 downto 0)',
865 
      'width' => 32,
866 
    },
867 
    'to_register24_dout_net' => {
868 
      'hdlType' => 'std_logic',
869 
      'width' => 1,
870 
    },
871 
    'to_register25_dout_net' => {
872 
      'hdlType' => 'std_logic_vector(31 downto 0)',
873 
      'width' => 32,
874 
    },
875 
    'to_register26_dout_net' => {
876 
      'hdlType' => 'std_logic',
877 
      'width' => 1,
878 
    },
879 
    'to_register27_dout_net' => {
880 
      'hdlType' => 'std_logic_vector(31 downto 0)',
881 
      'width' => 32,
882 
    },
883 
    'to_register2_dout_net' => {
884 
      'hdlType' => 'std_logic_vector(31 downto 0)',
885 
      'width' => 32,
886 
    },
887 
    'to_register3_dout_net' => {
888 
      'hdlType' => 'std_logic_vector(31 downto 0)',
889 
      'width' => 32,
890 
    },
891 
    'to_register4_dout_net' => {
892 
      'hdlType' => 'std_logic',
893 
      'width' => 1,
894 
    },
895 
    'to_register5_dout_net' => {
896 
      'hdlType' => 'std_logic',
897 
      'width' => 1,
898 
    },
899 
    'to_register6_dout_net' => {
900 
      'hdlType' => 'std_logic_vector(31 downto 0)',
901 
      'width' => 32,
902 
    },
903 
    'to_register7_dout_net' => {
904 
      'hdlType' => 'std_logic',
905 
      'width' => 1,
906 
    },
907 
    'to_register8_dout_net' => {
908 
      'hdlType' => 'std_logic_vector(31 downto 0)',
909 
      'width' => 32,
910 
    },
911 
    'to_register9_dout_net' => {
912 
      'hdlType' => 'std_logic_vector(31 downto 0)',
913 
      'width' => 32,
914 
    },
915 
    'to_register_dout_net' => {
916 
      'hdlType' => 'std_logic_vector(31 downto 0)',
917 
      'width' => 32,
918 
    },
919 
    'user_int_1o_net' => {
920 
      'hdlType' => 'std_logic',
921 
      'width' => 1,
922 
    },
923 
    'user_int_2o_net' => {
924 
      'hdlType' => 'std_logic',
925 
      'width' => 1,
926 
    },
927 
    'user_int_3o_net' => {
928 
      'hdlType' => 'std_logic',
929 
      'width' => 1,
930 
    },
931 
  },
932 
  'subblocks' => {
933 
    'bram_rd_addr' => {
934 
      'connections' => { 'bram_rd_addr' => 'bram_rd_addr_net', },
935 
      'entity' => {
936 
        'attributes' => {
937 
          'isGateway' => 1,
938 
          'is_floating_block' => 1,
939 
        },
940 
        'entityName' => 'bram_rd_addr',
941 
        'ports' => {
942 
          'bram_rd_addr' => {
943 
            'attributes' => {
944 
              'bin_pt' => 0,
945 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
946 
              'is_floating_block' => 1,
947 
              'is_gateway_port' => 1,
948 
              'must_be_hdl_vector' => 1,
949 
              'period' => 1.0,
950 
              'port_id' => '0',
951 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr/BRAM_rd_addr',
952 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr',
953 
              'timingConstraint' => 'none',
954 
              'type' => 'UFix_12_0',
955 
            },
956 
            'direction' => 'in',
957 
            'hdlType' => 'std_logic_vector(11 downto 0)',
958 
            'width' => 12,
959 
          },
960 
        },
961 
      },
962 
      'entityName' => 'bram_rd_addr',
963 
    },
964 
    'bram_rd_dout' => {
965 
      'connections' => { 'bram_rd_dout' => 'bram_rd_dout_net', },
966 
      'entity' => {
967 
        'attributes' => {
968 
          'isGateway' => 1,
969 
          'is_floating_block' => 1,
970 
        },
971 
        'entityName' => 'bram_rd_dout',
972 
        'ports' => {
973 
          'bram_rd_dout' => {
974 
            'attributes' => {
975 
              'bin_pt' => 0,
976 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
977 
              'is_floating_block' => 1,
978 
              'is_gateway_port' => 1,
979 
              'must_be_hdl_vector' => 1,
980 
              'period' => 1.0,
981 
              'port_id' => '0',
982 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_dout/BRAM_rd_dout',
983 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_dout',
984 
              'timingConstraint' => 'none',
985 
              'type' => 'UFix_64_0',
986 
            },
987 
            'direction' => 'out',
988 
            'hdlType' => 'std_logic_vector(63 downto 0)',
989 
            'width' => 64,
990 
          },
991 
        },
992 
      },
993 
      'entityName' => 'bram_rd_dout',
994 
    },
995 
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996 
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              'port_id' => '0',
6976 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/dout',
6977 
              'type' => 'UFix_32_0',
6978 
            },
6979 
            'direction' => 'out',
6980 
            'hdlType' => 'std_logic_vector(31 downto 0)',
6981 
            'width' => 32,
6982 
          },
6983 
          'en' => {
6984 
            'attributes' => {
6985 
              'bin_pt' => 0,
6986 
              'is_floating_block' => 1,
6987 
              'must_be_hdl_vector' => 1,
6988 
              'period' => 1.0,
6989 
              'port_id' => '1',
6990 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/en',
6991 
              'type' => 'Bool',
6992 
            },
6993 
            'direction' => 'in',
6994 
            'hdlType' => 'std_logic_vector(0 downto 0)',
6995 
            'width' => 1,
6996 
          },
6997 
        },
6998 
      },
6999 
      'entityName' => 'x_x60',
7000 
    },
7001 
    'user_int_1o' => {
7002 
      'connections' => { 'user_int_1o' => 'user_int_1o_net', },
7003 
      'entity' => {
7004 
        'attributes' => {
7005 
          'isGateway' => 1,
7006 
          'is_floating_block' => 1,
7007 
        },
7008 
        'entityName' => 'user_int_1o',
7009 
        'ports' => {
7010 
          'user_int_1o' => {
7011 
            'attributes' => {
7012 
              'bin_pt' => 0,
7013 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
7014 
              'is_floating_block' => 1,
7015 
              'is_gateway_port' => 1,
7016 
              'must_be_hdl_vector' => 1,
7017 
              'period' => 1.0,
7018 
              'port_id' => '0',
7019 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o/user_int_1o',
7020 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o',
7021 
              'timingConstraint' => 'none',
7022 
              'type' => 'Bool',
7023 
            },
7024 
            'direction' => 'in',
7025 
            'hdlType' => 'std_logic',
7026 
            'width' => 1,
7027 
          },
7028 
        },
7029 
      },
7030 
      'entityName' => 'user_int_1o',
7031 
    },
7032 
    'user_int_2o' => {
7033 
      'connections' => { 'user_int_2o' => 'user_int_2o_net', },
7034 
      'entity' => {
7035 
        'attributes' => {
7036 
          'isGateway' => 1,
7037 
          'is_floating_block' => 1,
7038 
        },
7039 
        'entityName' => 'user_int_2o',
7040 
        'ports' => {
7041 
          'user_int_2o' => {
7042 
            'attributes' => {
7043 
              'bin_pt' => 0,
7044 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
7045 
              'is_floating_block' => 1,
7046 
              'is_gateway_port' => 1,
7047 
              'must_be_hdl_vector' => 1,
7048 
              'period' => 1.0,
7049 
              'port_id' => '0',
7050 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
7051 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
7052 
              'timingConstraint' => 'none',
7053 
              'type' => 'Bool',
7054 
            },
7055 
            'direction' => 'in',
7056 
            'hdlType' => 'std_logic',
7057 
            'width' => 1,
7058 
          },
7059 
        },
7060 
      },
7061 
      'entityName' => 'user_int_2o',
7062 
    },
7063 
    'user_int_3o' => {
7064 
      'connections' => { 'user_int_3o' => 'user_int_3o_net', },
7065 
      'entity' => {
7066 
        'attributes' => {
7067 
          'isGateway' => 1,
7068 
          'is_floating_block' => 1,
7069 
        },
7070 
        'entityName' => 'user_int_3o',
7071 
        'ports' => {
7072 
          'user_int_3o' => {
7073 
            'attributes' => {
7074 
              'bin_pt' => 0,
7075 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
7076 
              'is_floating_block' => 1,
7077 
              'is_gateway_port' => 1,
7078 
              'must_be_hdl_vector' => 1,
7079 
              'period' => 1.0,
7080 
              'port_id' => '0',
7081 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o/user_int_3o',
7082 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o',
7083 
              'timingConstraint' => 'none',
7084 
              'type' => 'Bool',
7085 
            },
7086 
            'direction' => 'in',
7087 
            'hdlType' => 'std_logic',
7088 
            'width' => 1,
7089 
          },
7090 
        },
7091 
      },
7092 
      'entityName' => 'user_int_3o',
7093 
    },
7094 
    'user_logic' => {
7095 
      'connections' => {
7096 
        'bram_rd_addr' => 'bram_rd_addr_net',
7097 
        'bram_rd_dout' => 'bram_rd_dout_net',
7098 
        'bram_wr_addr' => 'bram_wr_addr_net',
7099 
        'bram_wr_din' => 'bram_wr_din_net',
7100 
        'bram_wr_en' => 'bram_wr_en_net',
7101 
        'ce_1' => 'ce_1_sg_x0',
7102 
        'clk_1' => 'clk_1_sg_x0',
7103 
        'data_in' => 'data_in_net',
7104 
        'data_in_x0' => 'data_in_x0_net',
7105 
        'data_in_x1' => 'data_in_x1_net',
7106 
        'data_in_x10' => 'data_in_x10_net',
7107 
        'data_in_x11' => 'data_in_x11_net',
7108 
        'data_in_x12' => 'data_in_x12_net',
7109 
        'data_in_x13' => 'data_in_x13_net',
7110 
        'data_in_x14' => 'data_in_x14_net',
7111 
        'data_in_x15' => 'data_in_x15_net',
7112 
        'data_in_x16' => 'data_in_x16_net',
7113 
        'data_in_x17' => 'data_in_x17_net',
7114 
        'data_in_x18' => 'data_in_x18_net',
7115 
        'data_in_x19' => 'data_in_x19_net',
7116 
        'data_in_x2' => 'data_in_x2_net',
7117 
        'data_in_x20' => 'data_in_x20_net',
7118 
        'data_in_x21' => 'data_in_x21_net',
7119 
        'data_in_x22' => 'data_in_x22_net',
7120 
        'data_in_x23' => 'data_in_x23_net',
7121 
        'data_in_x24' => 'data_in_x24_net',
7122 
        'data_in_x25' => 'data_in_x25_net',
7123 
        'data_in_x26' => 'data_in_x26_net',
7124 
        'data_in_x3' => 'data_in_x3_net',
7125 
        'data_in_x4' => 'data_in_x4_net',
7126 
        'data_in_x5' => 'data_in_x5_net',
7127 
        'data_in_x6' => 'data_in_x6_net',
7128 
        'data_in_x7' => 'data_in_x7_net',
7129 
        'data_in_x8' => 'data_in_x8_net',
7130 
        'data_in_x9' => 'data_in_x9_net',
7131 
        'data_out_x1' => 'data_out_x1_net',
7132 
        'data_out_x12' => 'data_out_x12_net',
7133 
        'data_out_x13' => 'data_out_x13_net',
7134 
        'data_out_x14' => 'data_out_x14_net',
7135 
        'data_out_x15' => 'data_out_x15_net',
7136 
        'data_out_x16' => 'data_out_x16_net',
7137 
        'data_out_x17' => 'data_out_x17_net',
7138 
        'data_out_x18' => 'data_out_x18_net',
7139 
        'data_out_x19' => 'data_out_x19_net',
7140 
        'data_out_x2' => 'data_out_x2_net',
7141 
        'data_out_x20' => 'data_out_x20_net',
7142 
        'data_out_x21' => 'data_out_x21_net',
7143 
        'data_out_x22' => 'data_out_x22_net',
7144 
        'data_out_x23' => 'data_out_x23_net',
7145 
        'data_out_x24' => 'data_out_x24_net',
7146 
        'data_out_x25' => 'data_out_x25_net',
7147 
        'data_out_x26' => 'data_out_x26_net',
7148 
        'data_out_x27' => 'data_out_x27_net',
7149 
        'data_out_x28' => 'data_out_x28_net',
7150 
        'data_out_x29' => 'data_out_x29_net',
7151 
        'data_out_x3' => 'data_out_x3_net',
7152 
        'data_out_x30' => 'data_out_x30_net',
7153 
        'data_out_x31' => 'data_out_x31_net',
7154 
        'data_out_x32' => 'data_out_x32_net',
7155 
        'data_out_x4' => 'data_out_x4_net',
7156 
        'data_out_x5' => 'data_out_x5_net',
7157 
        'data_out_x8' => 'data_out_x8_net',
7158 
        'data_out_x9' => 'data_out_x9_net',
7159 
        'en' => 'constant6_op_net_x0',
7160 
        'en_x0' => 'constant6_op_net_x1',
7161 
        'en_x1' => 'constant6_op_net_x2',
7162 
        'en_x10' => 'constant6_op_net_x11',
7163 
        'en_x11' => 'constant6_op_net_x12',
7164 
        'en_x12' => 'constant6_op_net_x13',
7165 
        'en_x13' => 'constant6_op_net_x14',
7166 
        'en_x14' => 'constant6_op_net_x15',
7167 
        'en_x15' => 'constant6_op_net_x16',
7168 
        'en_x16' => 'constant6_op_net_x17',
7169 
        'en_x17' => 'constant6_op_net_x18',
7170 
        'en_x18' => 'constant6_op_net_x19',
7171 
        'en_x19' => 'constant6_op_net_x20',
7172 
        'en_x2' => 'constant6_op_net_x3',
7173 
        'en_x20' => 'constant6_op_net_x21',
7174 
        'en_x21' => 'constant6_op_net_x22',
7175 
        'en_x22' => 'constant6_op_net_x23',
7176 
        'en_x23' => 'constant6_op_net_x24',
7177 
        'en_x24' => 'constant6_op_net_x25',
7178 
        'en_x25' => 'constant6_op_net_x26',
7179 
        'en_x26' => 'constant6_op_net_x27',
7180 
        'en_x3' => 'constant6_op_net_x4',
7181 
        'en_x4' => 'constant6_op_net_x5',
7182 
        'en_x5' => 'constant6_op_net_x6',
7183 
        'en_x6' => 'constant6_op_net_x7',
7184 
        'en_x7' => 'constant6_op_net_x8',
7185 
        'en_x8' => 'constant6_op_net_x9',
7186 
        'en_x9' => 'constant6_op_net_x10',
7187 
        'fifo_rd_count_x0' => 'fifo_rd_count_net',
7188 
        'fifo_rd_dout' => 'fifo_rd_dout_net',
7189 
        'fifo_rd_empty' => 'fifo_rd_empty_net',
7190 
        'fifo_rd_en_x1' => 'fifo_rd_en_net',
7191 
        'fifo_rd_pempty_x0' => 'fifo_rd_pempty_net',
7192 
        'fifo_rd_valid' => 'fifo_rd_valid_net',
7193 
        'fifo_wr_count_x0' => 'fifo_wr_count_net',
7194 
        'fifo_wr_din' => 'fifo_wr_din_net',
7195 
        'fifo_wr_en_x0' => 'fifo_wr_en_net',
7196 
        'fifo_wr_full_x0' => 'fifo_wr_full_net',
7197 
        'fifo_wr_pfull_x0' => 'fifo_wr_pfull_net',
7198 
        'rst_i' => 'rst_i_net',
7199 
        'rst_o' => 'rst_o_net',
7200 
        'user_int_1o' => 'user_int_1o_net',
7201 
        'user_int_2o' => 'user_int_2o_net',
7202 
        'user_int_3o' => 'user_int_3o_net',
7203 
      },
7204 
      'entity' => {
7205 
        'attributes' => {
7206 
          'entityAlreadyNetlisted' => 1,
7207 
          'hdlKind' => 'vhdl',
7208 
          'isDesign' => 1,
7209 
          'simulinkName' => 'USER_LOGIC',
7210 
        },
7211 
        'entityName' => 'user_logic',
7212 
        'ports' => {
7213 
          'bram_rd_addr' => {
7214 
            'attributes' => {
7215 
              'bin_pt' => 0,
7216 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
7217 
              'is_floating_block' => 1,
7218 
              'is_gateway_port' => 1,
7219 
              'must_be_hdl_vector' => 1,
7220 
              'period' => 1.0,
7221 
              'port_id' => '15',
7222 
              'simulinkName' => 'USER_LOGIC/BRAM_rd_addr',
7223 
              'source_block' => 'USER_LOGIC',
7224 
              'timingConstraint' => 'none',
7225 
              'type' => 'UFix_12_0',
7226 
            },
7227 
            'direction' => 'out',
7228 
            'hdlType' => 'std_logic_vector(11 downto 0)',
7229 
            'width' => 12,
7230 
          },
7231 
          'bram_rd_dout' => {
7232 
            'attributes' => {
7233 
              'bin_pt' => 0,
7234 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
7235 
              'is_floating_block' => 1,
7236 
              'is_gateway_port' => 1,
7237 
              'must_be_hdl_vector' => 1,
7238 
              'period' => 1.0,
7239 
              'port_id' => '0',
7240 
              'simulinkName' => 'USER_LOGIC/BRAM_rd_dout',
7241 
              'source_block' => 'USER_LOGIC',
7242 
              'timingConstraint' => 'none',
7243 
              'type' => 'UFix_64_0',
7244 
            },
7245 
            'direction' => 'in',
7246 
            'hdlType' => 'std_logic_vector(63 downto 0)',
7247 
            'width' => 64,
7248 
          },
7249 
          'bram_wr_addr' => {
7250 
            'attributes' => {
7251 
              'bin_pt' => 0,
7252 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
7253 
              'is_floating_block' => 1,
7254 
              'is_gateway_port' => 1,
7255 
              'must_be_hdl_vector' => 1,
7256 
              'period' => 1.0,
7257 
              'port_id' => '16',
7258 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_addr',
7259 
              'source_block' => 'USER_LOGIC',
7260 
              'timingConstraint' => 'none',
7261 
              'type' => 'UFix_12_0',
7262 
            },
7263 
            'direction' => 'out',
7264 
            'hdlType' => 'std_logic_vector(11 downto 0)',
7265 
            'width' => 12,
7266 
          },
7267 
          'bram_wr_din' => {
7268 
            'attributes' => {
7269 
              'bin_pt' => 0,
7270 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
7271 
              'is_floating_block' => 1,
7272 
              'is_gateway_port' => 1,
7273 
              'must_be_hdl_vector' => 1,
7274 
              'period' => 1.0,
7275 
              'port_id' => '18',
7276 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_din',
7277 
              'source_block' => 'USER_LOGIC',
7278 
              'timingConstraint' => 'none',
7279 
              'type' => 'UFix_64_0',
7280 
            },
7281 
            'direction' => 'out',
7282 
            'hdlType' => 'std_logic_vector(63 downto 0)',
7283 
            'width' => 64,
7284 
          },
7285 
          'bram_wr_en' => {
7286 
            'attributes' => {
7287 
              'bin_pt' => 0,
7288 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_en.dat',
7289 
              'is_floating_block' => 1,
7290 
              'is_gateway_port' => 1,
7291 
              'must_be_hdl_vector' => 1,
7292 
              'period' => 1.0,
7293 
              'port_id' => '23',
7294 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_en',
7295 
              'source_block' => 'USER_LOGIC',
7296 
              'timingConstraint' => 'none',
7297 
              'type' => 'UFix_8_0',
7298 
            },
7299 
            'direction' => 'out',
7300 
            'hdlType' => 'std_logic_vector(7 downto 0)',
7301 
            'width' => 8,
7302 
          },
7303 
          'ce_1' => {
7304 
            'attributes' => {
7305 
              'domain' => '',
7306 
              'group' => 1,
7307 
              'isCe' => 1,
7308 
              'is_subsys_port' => 1,
7309 
              'period' => 1.0,
7310 
              'subsys_port_index' => '0',
7311 
              'type' => 'logic',
7312 
            },
7313 
            'direction' => 'in',
7314 
            'hdlType' => 'std_logic',
7315 
            'width' => 1,
7316 
          },
7317 
          'clk_1' => {
7318 
            'attributes' => {
7319 
              'domain' => '',
7320 
              'group' => 1,
7321 
              'isClk' => 1,
7322 
              'is_subsys_port' => 1,
7323 
              'period' => 1.0,
7324 
              'subsys_port_index' => '0',
7325 
              'type' => 'logic',
7326 
            },
7327 
            'direction' => 'in',
7328 
            'hdlType' => 'std_logic',
7329 
            'width' => 1,
7330 
          },
7331 
          'data_in' => {
7332 
            'attributes' => {
7333 
              'bin_pt' => 0,
7334 
              'is_floating_block' => 1,
7335 
              'must_be_hdl_vector' => 1,
7336 
              'period' => 1.0,
7337 
              'port_id' => '17',
7338 
              'simulinkName' => 'USER_LOGIC/tx_en_in2',
7339 
              'type' => 'UFix_32_0',
7340 
            },
7341 
            'direction' => 'out',
7342 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7343 
            'width' => 32,
7344 
          },
7345 
          'data_in_x0' => {
7346 
            'attributes' => {
7347 
              'bin_pt' => 0,
7348 
              'is_floating_block' => 1,
7349 
              'must_be_hdl_vector' => 1,
7350 
              'period' => 1.0,
7351 
              'port_id' => '1',
7352 
              'simulinkName' => 'USER_LOGIC/tx_en_in1',
7353 
              'type' => 'Bool',
7354 
            },
7355 
            'direction' => 'out',
7356 
            'hdlType' => 'std_logic',
7357 
            'width' => 1,
7358 
          },
7359 
          'data_in_x1' => {
7360 
            'attributes' => {
7361 
              'bin_pt' => 0,
7362 
              'is_floating_block' => 1,
7363 
              'must_be_hdl_vector' => 1,
7364 
              'period' => 1.0,
7365 
              'port_id' => '36',
7366 
              'simulinkName' => 'USER_LOGIC/tx_en_in96',
7367 
              'type' => 'Bool',
7368 
            },
7369 
            'direction' => 'out',
7370 
            'hdlType' => 'std_logic',
7371 
            'width' => 1,
7372 
          },
7373 
          'data_in_x10' => {
7374 
            'attributes' => {
7375 
              'bin_pt' => 0,
7376 
              'is_floating_block' => 1,
7377 
              'must_be_hdl_vector' => 1,
7378 
              'period' => 1.0,
7379 
              'port_id' => '33',
7380 
              'simulinkName' => 'USER_LOGIC/tx_en_in91',
7381 
              'type' => 'UFix_32_0',
7382 
            },
7383 
            'direction' => 'out',
7384 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7385 
            'width' => 32,
7386 
          },
7387 
          'data_in_x11' => {
7388 
            'attributes' => {
7389 
              'bin_pt' => 0,
7390 
              'is_floating_block' => 1,
7391 
              'must_be_hdl_vector' => 1,
7392 
              'period' => 1.0,
7393 
              'port_id' => '21',
7394 
              'simulinkName' => 'USER_LOGIC/tx_en_in33',
7395 
              'type' => 'UFix_32_0',
7396 
            },
7397 
            'direction' => 'out',
7398 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7399 
            'width' => 32,
7400 
          },
7401 
          'data_in_x12' => {
7402 
            'attributes' => {
7403 
              'bin_pt' => 0,
7404 
              'is_floating_block' => 1,
7405 
              'must_be_hdl_vector' => 1,
7406 
              'period' => 1.0,
7407 
              'port_id' => '6',
7408 
              'simulinkName' => 'USER_LOGIC/tx_en_in113',
7409 
              'type' => 'Bool',
7410 
            },
7411 
            'direction' => 'out',
7412 
            'hdlType' => 'std_logic',
7413 
            'width' => 1,
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