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URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [synopsis.2] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
{
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fprintf(\'\',\'COMMENT: end icon graphics\');
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    'constant6_op_net_x8' => {
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    'constant6_op_net_x9' => {
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566 
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570 
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578 
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629 
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669 
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686 
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714 
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722 
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726 
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728 
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729 
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730 
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731 
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732 
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733 
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735 
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737 
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738 
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739 
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740 
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741 
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742 
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743 
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744 
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745 
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746 
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748 
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749 
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750 
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751 
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752 
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753 
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754 
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756 
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757 
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758 
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761 
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762 
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763 
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764 
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765 
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766 
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768 
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769 
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770 
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772 
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773 
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774 
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775 
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776 
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777 
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778 
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779 
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780 
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781 
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782 
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783 
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784 
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785 
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790 
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793 
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794 
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795 
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796 
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797 
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798 
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799 
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800 
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801 
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802 
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803 
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804 
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805 
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806 
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807 
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808 
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809 
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810 
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811 
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812 
    'to_register11_dout_net' => {
813 
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814 
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815 
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816 
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817 
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818 
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819 
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820 
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821 
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822 
      'width' => 32,
823 
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824 
    'to_register14_dout_net' => {
825 
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826 
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827 
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828 
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829 
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830 
      'width' => 32,
831 
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832 
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833 
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834 
      'width' => 1,
835 
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836 
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837 
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838 
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839 
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840 
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841 
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842 
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843 
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844 
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845 
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846 
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847 
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848 
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849 
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850 
      'width' => 1,
851 
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852 
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853 
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854 
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855 
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856 
    'to_register21_dout_net' => {
857 
      'hdlType' => 'std_logic_vector(31 downto 0)',
858 
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859 
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860 
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861 
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862 
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863 
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864 
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865 
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866 
      'width' => 32,
867 
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868 
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869 
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870 
      'width' => 1,
871 
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872 
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873 
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874 
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875 
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876 
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877 
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878 
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879 
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880 
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881 
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882 
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883 
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884 
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885 
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886 
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887 
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888 
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889 
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890 
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891 
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892 
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893 
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894 
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895 
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896 
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897 
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898 
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899 
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900 
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901 
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902 
      'width' => 32,
903 
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904 
    'to_register7_dout_net' => {
905 
      'hdlType' => 'std_logic',
906 
      'width' => 1,
907 
    },
908 
    'to_register8_dout_net' => {
909 
      'hdlType' => 'std_logic_vector(31 downto 0)',
910 
      'width' => 32,
911 
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912 
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913 
      'hdlType' => 'std_logic_vector(31 downto 0)',
914 
      'width' => 32,
915 
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916 
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917 
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918 
      'width' => 32,
919 
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920 
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921 
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922 
      'width' => 1,
923 
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924 
    'user_int_2o_net' => {
925 
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926 
      'width' => 1,
927 
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928 
    'user_int_3o_net' => {
929 
      'hdlType' => 'std_logic',
930 
      'width' => 1,
931 
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932 
  },
933 
  'subblocks' => {
934 
    'bram_rd_addr' => {
935 
      'connections' => {
936 
        'bram_rd_addr' => 'bram_rd_addr_net',
937 
      },
938 
      'entity' => {
939 
        'attributes' => {
940 
          'isGateway' => 1,
941 
          'is_floating_block' => 1,
942 
        },
943 
        'entityName' => 'bram_rd_addr',
944 
        'ports' => {
945 
          'bram_rd_addr' => {
946 
            'attributes' => {
947 
              'bin_pt' => 0,
948 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
949 
              'is_floating_block' => 1,
950 
              'is_gateway_port' => 1,
951 
              'must_be_hdl_vector' => 1,
952 
              'period' => 1,
953 
              'port_id' => 0,
954 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr/BRAM_rd_addr',
955 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr',
956 
              'timingConstraint' => 'none',
957 
              'type' => 'UFix_12_0',
958 
            },
959 
            'direction' => 'in',
960 
            'hdlType' => 'std_logic_vector(11 downto 0)',
961 
            'width' => 12,
962 
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963 
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964 
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965 
      'entityName' => 'bram_rd_addr',
966 
    },
967 
    'bram_rd_dout' => {
968 
      'connections' => {
969 
        'bram_rd_dout' => 'bram_rd_dout_net',
970 
      },
971 
      'entity' => {
972 
        'attributes' => {
973 
          'isGateway' => 1,
974 
          'is_floating_block' => 1,
975 
        },
976 
        'entityName' => 'bram_rd_dout',
977 
        'ports' => {
978 
          'bram_rd_dout' => {
979 
            'attributes' => {
980 
              'bin_pt' => 0,
981 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
982 
              'is_floating_block' => 1,
983 
              'is_gateway_port' => 1,
984 
              'must_be_hdl_vector' => 1,
985 
              'period' => 1,
986 
              'port_id' => 0,
987 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_dout/BRAM_rd_dout',
988 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_dout',
989 
              'timingConstraint' => 'none',
990 
              'type' => 'UFix_64_0',
991 
            },
992 
            'direction' => 'out',
993 
            'hdlType' => 'std_logic_vector(63 downto 0)',
994 
            'width' => 64,
995 
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996 
        },
997 
      },
998 
      'entityName' => 'bram_rd_dout',
999 
    },
1000 
    'bram_wr_addr' => {
1001 
      'connections' => {
1002 
        'bram_wr_addr' => 'bram_wr_addr_net',
1003 
      },
1004 
      'entity' => {
1005 
        'attributes' => {
1006 
          'isGateway' => 1,
1007 
          'is_floating_block' => 1,
1008 
        },
1009 
        'entityName' => 'bram_wr_addr',
1010 
        'ports' => {
1011 
          'bram_wr_addr' => {
1012 
            'attributes' => {
1013 
              'bin_pt' => 0,
1014 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
1015 
              'is_floating_block' => 1,
1016 
              'is_gateway_port' => 1,
1017 
              'must_be_hdl_vector' => 1,
1018 
              'period' => 1,
1019 
              'port_id' => 0,
1020 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_addr/BRAM_wr_addr',
1021 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_addr',
1022 
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            'direction' => 'in',
7133 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7134 
            'width' => 32,
7135 
          },
7136 
          'dout' => {
7137 
            'attributes' => {
7138 
              'bin_pt' => 0,
7139 
              'is_floating_block' => 1,
7140 
              'must_be_hdl_vector' => 1,
7141 
              'period' => 1,
7142 
              'port_id' => 0,
7143 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/dout',
7144 
              'type' => 'UFix_32_0',
7145 
            },
7146 
            'direction' => 'out',
7147 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7148 
            'width' => 32,
7149 
          },
7150 
          'en' => {
7151 
            'attributes' => {
7152 
              'bin_pt' => 0,
7153 
              'is_floating_block' => 1,
7154 
              'must_be_hdl_vector' => 1,
7155 
              'period' => 1,
7156 
              'port_id' => 1,
7157 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/en',
7158 
              'type' => 'Bool',
7159 
            },
7160 
            'direction' => 'in',
7161 
            'hdlType' => 'std_logic_vector(0 downto 0)',
7162 
            'width' => 1,
7163 
          },
7164 
        },
7165 
      },
7166 
      'entityName' => 'x_x60',
7167 
    },
7168 
    'user_int_1o' => {
7169 
      'connections' => {
7170 
        'user_int_1o' => 'user_int_1o_net',
7171 
      },
7172 
      'entity' => {
7173 
        'attributes' => {
7174 
          'isGateway' => 1,
7175 
          'is_floating_block' => 1,
7176 
        },
7177 
        'entityName' => 'user_int_1o',
7178 
        'ports' => {
7179 
          'user_int_1o' => {
7180 
            'attributes' => {
7181 
              'bin_pt' => 0,
7182 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
7183 
              'is_floating_block' => 1,
7184 
              'is_gateway_port' => 1,
7185 
              'must_be_hdl_vector' => 1,
7186 
              'period' => 1,
7187 
              'port_id' => 0,
7188 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o/user_int_1o',
7189 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o',
7190 
              'timingConstraint' => 'none',
7191 
              'type' => 'Bool',
7192 
            },
7193 
            'direction' => 'in',
7194 
            'hdlType' => 'std_logic',
7195 
            'width' => 1,
7196 
          },
7197 
        },
7198 
      },
7199 
      'entityName' => 'user_int_1o',
7200 
    },
7201 
    'user_int_2o' => {
7202 
      'connections' => {
7203 
        'user_int_2o' => 'user_int_2o_net',
7204 
      },
7205 
      'entity' => {
7206 
        'attributes' => {
7207 
          'isGateway' => 1,
7208 
          'is_floating_block' => 1,
7209 
        },
7210 
        'entityName' => 'user_int_2o',
7211 
        'ports' => {
7212 
          'user_int_2o' => {
7213 
            'attributes' => {
7214 
              'bin_pt' => 0,
7215 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
7216 
              'is_floating_block' => 1,
7217 
              'is_gateway_port' => 1,
7218 
              'must_be_hdl_vector' => 1,
7219 
              'period' => 1,
7220 
              'port_id' => 0,
7221 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
7222 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
7223 
              'timingConstraint' => 'none',
7224 
              'type' => 'Bool',
7225 
            },
7226 
            'direction' => 'in',
7227 
            'hdlType' => 'std_logic',
7228 
            'width' => 1,
7229 
          },
7230 
        },
7231 
      },
7232 
      'entityName' => 'user_int_2o',
7233 
    },
7234 
    'user_int_3o' => {
7235 
      'connections' => {
7236 
        'user_int_3o' => 'user_int_3o_net',
7237 
      },
7238 
      'entity' => {
7239 
        'attributes' => {
7240 
          'isGateway' => 1,
7241 
          'is_floating_block' => 1,
7242 
        },
7243 
        'entityName' => 'user_int_3o',
7244 
        'ports' => {
7245 
          'user_int_3o' => {
7246 
            'attributes' => {
7247 
              'bin_pt' => 0,
7248 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
7249 
              'is_floating_block' => 1,
7250 
              'is_gateway_port' => 1,
7251 
              'must_be_hdl_vector' => 1,
7252 
              'period' => 1,
7253 
              'port_id' => 0,
7254 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o/user_int_3o',
7255 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o',
7256 
              'timingConstraint' => 'none',
7257 
              'type' => 'Bool',
7258 
            },
7259 
            'direction' => 'in',
7260 
            'hdlType' => 'std_logic',
7261 
            'width' => 1,
7262 
          },
7263 
        },
7264 
      },
7265 
      'entityName' => 'user_int_3o',
7266 
    },
7267 
    'user_logic' => {
7268 
      'connections' => {
7269 
        'bram_rd_addr' => 'bram_rd_addr_net',
7270 
        'bram_rd_dout' => 'bram_rd_dout_net',
7271 
        'bram_wr_addr' => 'bram_wr_addr_net',
7272 
        'bram_wr_din' => 'bram_wr_din_net',
7273 
        'bram_wr_en' => 'bram_wr_en_net',
7274 
        'ce_1' => 'ce_1_sg_x0',
7275 
        'clk_1' => 'clk_1_sg_x0',
7276 
        'data_in' => 'data_in_net',
7277 
        'data_in_x0' => 'data_in_x0_net',
7278 
        'data_in_x1' => 'data_in_x1_net',
7279 
        'data_in_x10' => 'data_in_x10_net',
7280 
        'data_in_x11' => 'data_in_x11_net',
7281 
        'data_in_x12' => 'data_in_x12_net',
7282 
        'data_in_x13' => 'data_in_x13_net',
7283 
        'data_in_x14' => 'data_in_x14_net',
7284 
        'data_in_x15' => 'data_in_x15_net',
7285 
        'data_in_x16' => 'data_in_x16_net',
7286 
        'data_in_x17' => 'data_in_x17_net',
7287 
        'data_in_x18' => 'data_in_x18_net',
7288 
        'data_in_x19' => 'data_in_x19_net',
7289 
        'data_in_x2' => 'data_in_x2_net',
7290 
        'data_in_x20' => 'data_in_x20_net',
7291 
        'data_in_x21' => 'data_in_x21_net',
7292 
        'data_in_x22' => 'data_in_x22_net',
7293 
        'data_in_x23' => 'data_in_x23_net',
7294 
        'data_in_x24' => 'data_in_x24_net',
7295 
        'data_in_x25' => 'data_in_x25_net',
7296 
        'data_in_x26' => 'data_in_x26_net',
7297 
        'data_in_x3' => 'data_in_x3_net',
7298 
        'data_in_x4' => 'data_in_x4_net',
7299 
        'data_in_x5' => 'data_in_x5_net',
7300 
        'data_in_x6' => 'data_in_x6_net',
7301 
        'data_in_x7' => 'data_in_x7_net',
7302 
        'data_in_x8' => 'data_in_x8_net',
7303 
        'data_in_x9' => 'data_in_x9_net',
7304 
        'data_out_x1' => 'data_out_x1_net',
7305 
        'data_out_x12' => 'data_out_x12_net',
7306 
        'data_out_x13' => 'data_out_x13_net',
7307 
        'data_out_x14' => 'data_out_x14_net',
7308 
        'data_out_x15' => 'data_out_x15_net',
7309 
        'data_out_x16' => 'data_out_x16_net',
7310 
        'data_out_x17' => 'data_out_x17_net',
7311 
        'data_out_x18' => 'data_out_x18_net',
7312 
        'data_out_x19' => 'data_out_x19_net',
7313 
        'data_out_x2' => 'data_out_x2_net',
7314 
        'data_out_x20' => 'data_out_x20_net',
7315 
        'data_out_x21' => 'data_out_x21_net',
7316 
        'data_out_x22' => 'data_out_x22_net',
7317 
        'data_out_x23' => 'data_out_x23_net',
7318 
        'data_out_x24' => 'data_out_x24_net',
7319 
        'data_out_x25' => 'data_out_x25_net',
7320 
        'data_out_x26' => 'data_out_x26_net',
7321 
        'data_out_x27' => 'data_out_x27_net',
7322 
        'data_out_x28' => 'data_out_x28_net',
7323 
        'data_out_x29' => 'data_out_x29_net',
7324 
        'data_out_x3' => 'data_out_x3_net',
7325 
        'data_out_x30' => 'data_out_x30_net',
7326 
        'data_out_x31' => 'data_out_x31_net',
7327 
        'data_out_x32' => 'data_out_x32_net',
7328 
        'data_out_x4' => 'data_out_x4_net',
7329 
        'data_out_x5' => 'data_out_x5_net',
7330 
        'data_out_x8' => 'data_out_x8_net',
7331 
        'data_out_x9' => 'data_out_x9_net',
7332 
        'en' => 'constant6_op_net_x0',
7333 
        'en_x0' => 'constant6_op_net_x1',
7334 
        'en_x1' => 'constant6_op_net_x2',
7335 
        'en_x10' => 'constant6_op_net_x11',
7336 
        'en_x11' => 'constant6_op_net_x12',
7337 
        'en_x12' => 'constant6_op_net_x13',
7338 
        'en_x13' => 'constant6_op_net_x14',
7339 
        'en_x14' => 'constant6_op_net_x15',
7340 
        'en_x15' => 'constant6_op_net_x16',
7341 
        'en_x16' => 'constant6_op_net_x17',
7342 
        'en_x17' => 'constant6_op_net_x18',
7343 
        'en_x18' => 'constant6_op_net_x19',
7344 
        'en_x19' => 'constant6_op_net_x20',
7345 
        'en_x2' => 'constant6_op_net_x3',
7346 
        'en_x20' => 'constant6_op_net_x21',
7347 
        'en_x21' => 'constant6_op_net_x22',
7348 
        'en_x22' => 'constant6_op_net_x23',
7349 
        'en_x23' => 'constant6_op_net_x24',
7350 
        'en_x24' => 'constant6_op_net_x25',
7351 
        'en_x25' => 'constant6_op_net_x26',
7352 
        'en_x26' => 'constant6_op_net_x27',
7353 
        'en_x3' => 'constant6_op_net_x4',
7354 
        'en_x4' => 'constant6_op_net_x5',
7355 
        'en_x5' => 'constant6_op_net_x6',
7356 
        'en_x6' => 'constant6_op_net_x7',
7357 
        'en_x7' => 'constant6_op_net_x8',
7358 
        'en_x8' => 'constant6_op_net_x9',
7359 
        'en_x9' => 'constant6_op_net_x10',
7360 
        'fifo_rd_count_x0' => 'fifo_rd_count_net',
7361 
        'fifo_rd_dout' => 'fifo_rd_dout_net',
7362 
        'fifo_rd_empty' => 'fifo_rd_empty_net',
7363 
        'fifo_rd_en_x1' => 'fifo_rd_en_net',
7364 
        'fifo_rd_pempty_x0' => 'fifo_rd_pempty_net',
7365 
        'fifo_rd_valid' => 'fifo_rd_valid_net',
7366 
        'fifo_wr_count_x0' => 'fifo_wr_count_net',
7367 
        'fifo_wr_din' => 'fifo_wr_din_net',
7368 
        'fifo_wr_en_x0' => 'fifo_wr_en_net',
7369 
        'fifo_wr_full_x0' => 'fifo_wr_full_net',
7370 
        'fifo_wr_pfull_x0' => 'fifo_wr_pfull_net',
7371 
        'rst_i' => 'rst_i_net',
7372 
        'rst_o' => 'rst_o_net',
7373 
        'user_int_1o' => 'user_int_1o_net',
7374 
        'user_int_2o' => 'user_int_2o_net',
7375 
        'user_int_3o' => 'user_int_3o_net',
7376 
      },
7377 
      'entity' => {
7378 
        'attributes' => {
7379 
          'entityAlreadyNetlisted' => 1,
7380 
          'hdlKind' => 'vhdl',
7381 
          'isDesign' => 1,
7382 
          'simulinkName' => 'USER_LOGIC',
7383 
        },
7384 
        'entityName' => 'user_logic',
7385 
        'ports' => {
7386 
          'bram_rd_addr' => {
7387 
            'attributes' => {
7388 
              'bin_pt' => 0,
7389 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
7390 
              'is_floating_block' => 1,
7391 
              'is_gateway_port' => 1,
7392 
              'must_be_hdl_vector' => 1,
7393 
              'period' => 1,
7394 
              'port_id' => 15,
7395 
              'simulinkName' => 'USER_LOGIC/BRAM_rd_addr',
7396 
              'source_block' => 'USER_LOGIC',
7397 
              'timingConstraint' => 'none',
7398 
              'type' => 'UFix_12_0',
7399 
            },
7400 
            'direction' => 'out',
7401 
            'hdlType' => 'std_logic_vector(11 downto 0)',
7402 
            'width' => 12,
7403 
          },
7404 
          'bram_rd_dout' => {
7405 
            'attributes' => {
7406 
              'bin_pt' => 0,
7407 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
7408 
              'is_floating_block' => 1,
7409 
              'is_gateway_port' => 1,
7410 
              'must_be_hdl_vector' => 1,
7411 
              'period' => 1,
7412 
              'port_id' => 0,
7413 
              'simulinkName' => 'USER_LOGIC/BRAM_rd_dout',
7414 
              'source_block' => 'USER_LOGIC',
7415 
              'timingConstraint' => 'none',
7416 
              'type' => 'UFix_64_0',
7417 
            },
7418 
            'direction' => 'in',
7419 
            'hdlType' => 'std_logic_vector(63 downto 0)',
7420 
            'width' => 64,
7421 
          },
7422 
          'bram_wr_addr' => {
7423 
            'attributes' => {
7424 
              'bin_pt' => 0,
7425 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
7426 
              'is_floating_block' => 1,
7427 
              'is_gateway_port' => 1,
7428 
              'must_be_hdl_vector' => 1,
7429 
              'period' => 1,
7430 
              'port_id' => 16,
7431 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_addr',
7432 
              'source_block' => 'USER_LOGIC',
7433 
              'timingConstraint' => 'none',
7434 
              'type' => 'UFix_12_0',
7435 
            },
7436 
            'direction' => 'out',
7437 
            'hdlType' => 'std_logic_vector(11 downto 0)',
7438 
            'width' => 12,
7439 
          },
7440 
          'bram_wr_din' => {
7441 
            'attributes' => {
7442 
              'bin_pt' => 0,
7443 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
7444 
              'is_floating_block' => 1,
7445 
              'is_gateway_port' => 1,
7446 
              'must_be_hdl_vector' => 1,
7447 
              'period' => 1,
7448 
              'port_id' => 18,
7449 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_din',
7450 
              'source_block' => 'USER_LOGIC',
7451 
              'timingConstraint' => 'none',
7452 
              'type' => 'UFix_64_0',
7453 
            },
7454 
            'direction' => 'out',
7455 
            'hdlType' => 'std_logic_vector(63 downto 0)',
7456 
            'width' => 64,
7457 
          },
7458 
          'bram_wr_en' => {
7459 
            'attributes' => {
7460 
              'bin_pt' => 0,
7461 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_en.dat',
7462 
              'is_floating_block' => 1,
7463 
              'is_gateway_port' => 1,
7464 
              'must_be_hdl_vector' => 1,
7465 
              'period' => 1,
7466 
              'port_id' => 23,
7467 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_en',
7468 
              'source_block' => 'USER_LOGIC',
7469 
              'timingConstraint' => 'none',
7470 
              'type' => 'UFix_8_0',
7471 
            },
7472 
            'direction' => 'out',
7473 
            'hdlType' => 'std_logic_vector(7 downto 0)',
7474 
            'width' => 8,
7475 
          },
7476 
          'ce_1' => {
7477 
            'attributes' => {
7478 
              'domain' => '',
7479 
              'group' => 1,
7480 
              'isCe' => 1,
7481 
              'is_subsys_port' => 1,
7482 
              'period' => 1,
7483 
              'subsys_port_index' => 0,
7484 
              'type' => 'logic',
7485 
            },
7486 
            'direction' => 'in',
7487 
            'hdlType' => 'std_logic',
7488 
            'width' => 1,
7489 
          },
7490 
          'clk_1' => {
7491 
            'attributes' => {
7492 
              'domain' => '',
7493 
              'group' => 1,
7494 
              'isClk' => 1,
7495 
              'is_subsys_port' => 1,
7496 
              'period' => 1,
7497 
              'subsys_port_index' => 0,
7498 
              'type' => 'logic',
7499 
            },
7500 
            'direction' => 'in',
7501 
            'hdlType' => 'std_logic',
7502 
            'width' => 1,
7503 
          },
7504 
          'data_in' => {
7505 
            'attributes' => {
7506 
              'bin_pt' => 0,
7507 
              'is_floating_block' => 1,
7508 
              'must_be_hdl_vector' => 1,
7509 
              'period' => 1,
7510 
              'port_id' => 17,
7511 
              'simulinkName' => 'USER_LOGIC/tx_en_in2',
7512 
              'type' => 'UFix_32_0',
7513 
            },
7514 
            'direction' => 'out',
7515 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7516 
            'width' => 32,
7517 
          },
7518 
          'data_in_x0' => {
7519 
            'attributes' => {
7520 
              'bin_pt' => 0,
7521 
              'is_floating_block' => 1,
7522 
              'must_be_hdl_vector' => 1,
7523 
              'period' => 1,
7524 
              'port_id' => 1,
7525 
              'simulinkName' => 'USER_LOGIC/tx_en_in1',
7526 
              'type' => 'Bool',
7527 
            },
7528 
            'direction' => 'out',
7529 
            'hdlType' => 'std_logic',
7530 
            'width' => 1,
7531 
          },
7532 
          'data_in_x1' => {
7533 
            'attributes' => {
7534 
              'bin_pt' => 0,
7535 
              'is_floating_block' => 1,
7536 
              'must_be_hdl_vector' => 1,
7537 
              'period' => 1,
7538 
              'port_id' => 36,
7539 
              'simulinkName' => 'USER_LOGIC/tx_en_in96',
7540 
              'type' => 'Bool',
7541 
            },
7542 
            'direction' => 'out',
7543 
            'hdlType' => 'std_logic',
7544 
            'width' => 1,
7545 
          },
7546 
          'data_in_x10' => {
7547 
            'attributes' => {
7548 
              'bin_pt' => 0,
7549 
              'is_floating_block' => 1,
7550 
              'must_be_hdl_vector' => 1,
7551 
              'period' => 1,
7552 
              'port_id' => 33,
7553 
              'simulinkName' => 'USER_LOGIC/tx_en_in91',
7554 
              'type' => 'UFix_32_0',
7555 
            },
7556 
            'direction' => 'out',
7557 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7558 
            'width' => 32,
7559 
          },
7560 
          'data_in_x11' => {
7561 
            'attributes' => {
7562 
              'bin_pt' => 0,
7563 
              'is_floating_block' => 1,
7564 
              'must_be_hdl_vector' => 1,
7565 
              'period' => 1,
7566 
              'port_id' => 21,
7567 
              'simulinkName' => 'USER_LOGIC/tx_en_in33',
7568 
              'type' => 'UFix_32_0',
7569 
            },
7570 
            'direction' => 'out',
7571 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7572 
            'width' => 32,
7573 
          },
7574 
          'data_in_x12' => {
7575 
            'attributes' => {
7576 
              'bin_pt' => 0,
7577 
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