OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [synopsis_com.xilinx.sysgen.netlister.CfWriter] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
{
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    'HDLCodeGenStatus' => 0,
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    'TEMP' => 'C:/DOCUME~1/root/IMPOST~1/Temp',
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    'clkWrapperFile' => 'user_logic_cw.vhd',
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    'clock_wrapper_sgadvanced' => '',
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    'netlistingWrapupScript' => 'java:com.xilinx.sysgen.netlister.DefaultWrapupNetlister',
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    'ngc_config' => {
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patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
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fprintf(\'\',\'COMMENT: end icon graphics\');
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fprintf(\'\',\'COMMENT: begin icon text\');
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fprintf(\'\',\'COMMENT: end icon text\');',
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patch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]);
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patch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.155 36.655 ],[0.933333 0.203922 0.141176 ]);
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fprintf(\'\',\'COMMENT: end icon graphics\');
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fprintf(\'\',\'COMMENT: begin icon text\');
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fprintf(\'\',\'COMMENT: end icon text\');',
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    },
464 
    'from_register2.data_out' => {
465 
      'hdlType' => 'std_logic_vector(31 downto 0)',
466 
      'width' => 32,
467 
    },
468 
    'from_register20.data_out' => {
469 
      'hdlType' => 'std_logic_vector(31 downto 0)',
470 
      'width' => 32,
471 
    },
472 
    'from_register21.data_out' => {
473 
      'hdlType' => 'std_logic',
474 
      'width' => 1,
475 
    },
476 
    'from_register22.data_out' => {
477 
      'hdlType' => 'std_logic_vector(31 downto 0)',
478 
      'width' => 32,
479 
    },
480 
    'from_register23.data_out' => {
481 
      'hdlType' => 'std_logic',
482 
      'width' => 1,
483 
    },
484 
    'from_register24.data_out' => {
485 
      'hdlType' => 'std_logic_vector(31 downto 0)',
486 
      'width' => 32,
487 
    },
488 
    'from_register25.data_out' => {
489 
      'hdlType' => 'std_logic',
490 
      'width' => 1,
491 
    },
492 
    'from_register26.data_out' => {
493 
      'hdlType' => 'std_logic_vector(31 downto 0)',
494 
      'width' => 32,
495 
    },
496 
    'from_register27.data_out' => {
497 
      'hdlType' => 'std_logic',
498 
      'width' => 1,
499 
    },
500 
    'from_register28.data_out' => {
501 
      'hdlType' => 'std_logic_vector(31 downto 0)',
502 
      'width' => 32,
503 
    },
504 
    'from_register29.data_out' => {
505 
      'hdlType' => 'std_logic',
506 
      'width' => 1,
507 
    },
508 
    'from_register3.data_out' => {
509 
      'hdlType' => 'std_logic_vector(31 downto 0)',
510 
      'width' => 32,
511 
    },
512 
    'from_register30.data_out' => {
513 
      'hdlType' => 'std_logic_vector(31 downto 0)',
514 
      'width' => 32,
515 
    },
516 
    'from_register31.data_out' => {
517 
      'hdlType' => 'std_logic',
518 
      'width' => 1,
519 
    },
520 
    'from_register32.data_out' => {
521 
      'hdlType' => 'std_logic_vector(31 downto 0)',
522 
      'width' => 32,
523 
    },
524 
    'from_register33.data_out' => {
525 
      'hdlType' => 'std_logic',
526 
      'width' => 1,
527 
    },
528 
    'from_register4.data_out' => {
529 
      'hdlType' => 'std_logic',
530 
      'width' => 1,
531 
    },
532 
    'from_register5.data_out' => {
533 
      'hdlType' => 'std_logic_vector(31 downto 0)',
534 
      'width' => 32,
535 
    },
536 
    'from_register6.data_out' => {
537 
      'hdlType' => 'std_logic',
538 
      'width' => 1,
539 
    },
540 
    'from_register7.data_out' => {
541 
      'hdlType' => 'std_logic_vector(31 downto 0)',
542 
      'width' => 32,
543 
    },
544 
    'from_register8.data_out' => {
545 
      'hdlType' => 'std_logic',
546 
      'width' => 1,
547 
    },
548 
    'from_register9.data_out' => {
549 
      'hdlType' => 'std_logic_vector(31 downto 0)',
550 
      'width' => 32,
551 
    },
552 
    'sysgen_dut.bram_rd_addr' => {
553 
      'hdlType' => 'std_logic_vector(11 downto 0)',
554 
      'width' => 12,
555 
    },
556 
    'sysgen_dut.bram_wr_addr' => {
557 
      'hdlType' => 'std_logic_vector(11 downto 0)',
558 
      'width' => 12,
559 
    },
560 
    'sysgen_dut.bram_wr_din' => {
561 
      'hdlType' => 'std_logic_vector(63 downto 0)',
562 
      'width' => 64,
563 
    },
564 
    'sysgen_dut.bram_wr_en' => {
565 
      'hdlType' => 'std_logic_vector(7 downto 0)',
566 
      'width' => 8,
567 
    },
568 
    'sysgen_dut.fifo_rd_en' => {
569 
      'hdlType' => 'std_logic',
570 
      'width' => 1,
571 
    },
572 
    'sysgen_dut.fifo_wr_din' => {
573 
      'hdlType' => 'std_logic_vector(71 downto 0)',
574 
      'width' => 72,
575 
    },
576 
    'sysgen_dut.fifo_wr_en' => {
577 
      'hdlType' => 'std_logic',
578 
      'width' => 1,
579 
    },
580 
    'sysgen_dut.rst_o' => {
581 
      'hdlType' => 'std_logic',
582 
      'width' => 1,
583 
    },
584 
    'sysgen_dut.to_register10_ce' => {
585 
      'hdlType' => 'std_logic',
586 
      'width' => 1,
587 
    },
588 
    'sysgen_dut.to_register10_clk' => {
589 
      'hdlType' => 'std_logic',
590 
      'width' => 1,
591 
    },
592 
    'sysgen_dut.to_register10_clr' => {
593 
      'hdlType' => 'std_logic',
594 
      'width' => 1,
595 
    },
596 
    'sysgen_dut.to_register10_data_in' => {
597 
      'hdlType' => 'std_logic',
598 
      'width' => 1,
599 
    },
600 
    'sysgen_dut.to_register10_en' => {
601 
      'hdlType' => 'std_logic',
602 
      'width' => 1,
603 
    },
604 
    'sysgen_dut.to_register11_ce' => {
605 
      'hdlType' => 'std_logic',
606 
      'width' => 1,
607 
    },
608 
    'sysgen_dut.to_register11_clk' => {
609 
      'hdlType' => 'std_logic',
610 
      'width' => 1,
611 
    },
612 
    'sysgen_dut.to_register11_clr' => {
613 
      'hdlType' => 'std_logic',
614 
      'width' => 1,
615 
    },
616 
    'sysgen_dut.to_register11_data_in' => {
617 
      'hdlType' => 'std_logic',
618 
      'width' => 1,
619 
    },
620 
    'sysgen_dut.to_register11_en' => {
621 
      'hdlType' => 'std_logic',
622 
      'width' => 1,
623 
    },
624 
    'sysgen_dut.to_register12_ce' => {
625 
      'hdlType' => 'std_logic',
626 
      'width' => 1,
627 
    },
628 
    'sysgen_dut.to_register12_clk' => {
629 
      'hdlType' => 'std_logic',
630 
      'width' => 1,
631 
    },
632 
    'sysgen_dut.to_register12_clr' => {
633 
      'hdlType' => 'std_logic',
634 
      'width' => 1,
635 
    },
636 
    'sysgen_dut.to_register12_data_in' => {
637 
      'hdlType' => 'std_logic',
638 
      'width' => 1,
639 
    },
640 
    'sysgen_dut.to_register12_en' => {
641 
      'hdlType' => 'std_logic',
642 
      'width' => 1,
643 
    },
644 
    'sysgen_dut.to_register13_ce' => {
645 
      'hdlType' => 'std_logic',
646 
      'width' => 1,
647 
    },
648 
    'sysgen_dut.to_register13_clk' => {
649 
      'hdlType' => 'std_logic',
650 
      'width' => 1,
651 
    },
652 
    'sysgen_dut.to_register13_clr' => {
653 
      'hdlType' => 'std_logic',
654 
      'width' => 1,
655 
    },
656 
    'sysgen_dut.to_register13_data_in' => {
657 
      'hdlType' => 'std_logic_vector(31 downto 0)',
658 
      'width' => 32,
659 
    },
660 
    'sysgen_dut.to_register13_en' => {
661 
      'hdlType' => 'std_logic',
662 
      'width' => 1,
663 
    },
664 
    'sysgen_dut.to_register14_ce' => {
665 
      'hdlType' => 'std_logic',
666 
      'width' => 1,
667 
    },
668 
    'sysgen_dut.to_register14_clk' => {
669 
      'hdlType' => 'std_logic',
670 
      'width' => 1,
671 
    },
672 
    'sysgen_dut.to_register14_clr' => {
673 
      'hdlType' => 'std_logic',
674 
      'width' => 1,
675 
    },
676 
    'sysgen_dut.to_register14_data_in' => {
677 
      'hdlType' => 'std_logic',
678 
      'width' => 1,
679 
    },
680 
    'sysgen_dut.to_register14_en' => {
681 
      'hdlType' => 'std_logic',
682 
      'width' => 1,
683 
    },
684 
    'sysgen_dut.to_register15_ce' => {
685 
      'hdlType' => 'std_logic',
686 
      'width' => 1,
687 
    },
688 
    'sysgen_dut.to_register15_clk' => {
689 
      'hdlType' => 'std_logic',
690 
      'width' => 1,
691 
    },
692 
    'sysgen_dut.to_register15_clr' => {
693 
      'hdlType' => 'std_logic',
694 
      'width' => 1,
695 
    },
696 
    'sysgen_dut.to_register15_data_in' => {
697 
      'hdlType' => 'std_logic_vector(31 downto 0)',
698 
      'width' => 32,
699 
    },
700 
    'sysgen_dut.to_register15_en' => {
701 
      'hdlType' => 'std_logic',
702 
      'width' => 1,
703 
    },
704 
    'sysgen_dut.to_register16_ce' => {
705 
      'hdlType' => 'std_logic',
706 
      'width' => 1,
707 
    },
708 
    'sysgen_dut.to_register16_clk' => {
709 
      'hdlType' => 'std_logic',
710 
      'width' => 1,
711 
    },
712 
    'sysgen_dut.to_register16_clr' => {
713 
      'hdlType' => 'std_logic',
714 
      'width' => 1,
715 
    },
716 
    'sysgen_dut.to_register16_data_in' => {
717 
      'hdlType' => 'std_logic',
718 
      'width' => 1,
719 
    },
720 
    'sysgen_dut.to_register16_en' => {
721 
      'hdlType' => 'std_logic',
722 
      'width' => 1,
723 
    },
724 
    'sysgen_dut.to_register17_ce' => {
725 
      'hdlType' => 'std_logic',
726 
      'width' => 1,
727 
    },
728 
    'sysgen_dut.to_register17_clk' => {
729 
      'hdlType' => 'std_logic',
730 
      'width' => 1,
731 
    },
732 
    'sysgen_dut.to_register17_clr' => {
733 
      'hdlType' => 'std_logic',
734 
      'width' => 1,
735 
    },
736 
    'sysgen_dut.to_register17_data_in' => {
737 
      'hdlType' => 'std_logic_vector(31 downto 0)',
738 
      'width' => 32,
739 
    },
740 
    'sysgen_dut.to_register17_en' => {
741 
      'hdlType' => 'std_logic',
742 
      'width' => 1,
743 
    },
744 
    'sysgen_dut.to_register18_ce' => {
745 
      'hdlType' => 'std_logic',
746 
      'width' => 1,
747 
    },
748 
    'sysgen_dut.to_register18_clk' => {
749 
      'hdlType' => 'std_logic',
750 
      'width' => 1,
751 
    },
752 
    'sysgen_dut.to_register18_clr' => {
753 
      'hdlType' => 'std_logic',
754 
      'width' => 1,
755 
    },
756 
    'sysgen_dut.to_register18_data_in' => {
757 
      'hdlType' => 'std_logic',
758 
      'width' => 1,
759 
    },
760 
    'sysgen_dut.to_register18_en' => {
761 
      'hdlType' => 'std_logic',
762 
      'width' => 1,
763 
    },
764 
    'sysgen_dut.to_register19_ce' => {
765 
      'hdlType' => 'std_logic',
766 
      'width' => 1,
767 
    },
768 
    'sysgen_dut.to_register19_clk' => {
769 
      'hdlType' => 'std_logic',
770 
      'width' => 1,
771 
    },
772 
    'sysgen_dut.to_register19_clr' => {
773 
      'hdlType' => 'std_logic',
774 
      'width' => 1,
775 
    },
776 
    'sysgen_dut.to_register19_data_in' => {
777 
      'hdlType' => 'std_logic_vector(31 downto 0)',
778 
      'width' => 32,
779 
    },
780 
    'sysgen_dut.to_register19_en' => {
781 
      'hdlType' => 'std_logic',
782 
      'width' => 1,
783 
    },
784 
    'sysgen_dut.to_register1_ce' => {
785 
      'hdlType' => 'std_logic',
786 
      'width' => 1,
787 
    },
788 
    'sysgen_dut.to_register1_clk' => {
789 
      'hdlType' => 'std_logic',
790 
      'width' => 1,
791 
    },
792 
    'sysgen_dut.to_register1_clr' => {
793 
      'hdlType' => 'std_logic',
794 
      'width' => 1,
795 
    },
796 
    'sysgen_dut.to_register1_data_in' => {
797 
      'hdlType' => 'std_logic',
798 
      'width' => 1,
799 
    },
800 
    'sysgen_dut.to_register1_en' => {
801 
      'hdlType' => 'std_logic',
802 
      'width' => 1,
803 
    },
804 
    'sysgen_dut.to_register20_ce' => {
805 
      'hdlType' => 'std_logic',
806 
      'width' => 1,
807 
    },
808 
    'sysgen_dut.to_register20_clk' => {
809 
      'hdlType' => 'std_logic',
810 
      'width' => 1,
811 
    },
812 
    'sysgen_dut.to_register20_clr' => {
813 
      'hdlType' => 'std_logic',
814 
      'width' => 1,
815 
    },
816 
    'sysgen_dut.to_register20_data_in' => {
817 
      'hdlType' => 'std_logic',
818 
      'width' => 1,
819 
    },
820 
    'sysgen_dut.to_register20_en' => {
821 
      'hdlType' => 'std_logic',
822 
      'width' => 1,
823 
    },
824 
    'sysgen_dut.to_register21_ce' => {
825 
      'hdlType' => 'std_logic',
826 
      'width' => 1,
827 
    },
828 
    'sysgen_dut.to_register21_clk' => {
829 
      'hdlType' => 'std_logic',
830 
      'width' => 1,
831 
    },
832 
    'sysgen_dut.to_register21_clr' => {
833 
      'hdlType' => 'std_logic',
834 
      'width' => 1,
835 
    },
836 
    'sysgen_dut.to_register21_data_in' => {
837 
      'hdlType' => 'std_logic_vector(31 downto 0)',
838 
      'width' => 32,
839 
    },
840 
    'sysgen_dut.to_register21_en' => {
841 
      'hdlType' => 'std_logic',
842 
      'width' => 1,
843 
    },
844 
    'sysgen_dut.to_register22_ce' => {
845 
      'hdlType' => 'std_logic',
846 
      'width' => 1,
847 
    },
848 
    'sysgen_dut.to_register22_clk' => {
849 
      'hdlType' => 'std_logic',
850 
      'width' => 1,
851 
    },
852 
    'sysgen_dut.to_register22_clr' => {
853 
      'hdlType' => 'std_logic',
854 
      'width' => 1,
855 
    },
856 
    'sysgen_dut.to_register22_data_in' => {
857 
      'hdlType' => 'std_logic',
858 
      'width' => 1,
859 
    },
860 
    'sysgen_dut.to_register22_en' => {
861 
      'hdlType' => 'std_logic',
862 
      'width' => 1,
863 
    },
864 
    'sysgen_dut.to_register23_ce' => {
865 
      'hdlType' => 'std_logic',
866 
      'width' => 1,
867 
    },
868 
    'sysgen_dut.to_register23_clk' => {
869 
      'hdlType' => 'std_logic',
870 
      'width' => 1,
871 
    },
872 
    'sysgen_dut.to_register23_clr' => {
873 
      'hdlType' => 'std_logic',
874 
      'width' => 1,
875 
    },
876 
    'sysgen_dut.to_register23_data_in' => {
877 
      'hdlType' => 'std_logic_vector(31 downto 0)',
878 
      'width' => 32,
879 
    },
880 
    'sysgen_dut.to_register23_en' => {
881 
      'hdlType' => 'std_logic',
882 
      'width' => 1,
883 
    },
884 
    'sysgen_dut.to_register24_ce' => {
885 
      'hdlType' => 'std_logic',
886 
      'width' => 1,
887 
    },
888 
    'sysgen_dut.to_register24_clk' => {
889 
      'hdlType' => 'std_logic',
890 
      'width' => 1,
891 
    },
892 
    'sysgen_dut.to_register24_clr' => {
893 
      'hdlType' => 'std_logic',
894 
      'width' => 1,
895 
    },
896 
    'sysgen_dut.to_register24_data_in' => {
897 
      'hdlType' => 'std_logic',
898 
      'width' => 1,
899 
    },
900 
    'sysgen_dut.to_register24_en' => {
901 
      'hdlType' => 'std_logic',
902 
      'width' => 1,
903 
    },
904 
    'sysgen_dut.to_register25_ce' => {
905 
      'hdlType' => 'std_logic',
906 
      'width' => 1,
907 
    },
908 
    'sysgen_dut.to_register25_clk' => {
909 
      'hdlType' => 'std_logic',
910 
      'width' => 1,
911 
    },
912 
    'sysgen_dut.to_register25_clr' => {
913 
      'hdlType' => 'std_logic',
914 
      'width' => 1,
915 
    },
916 
    'sysgen_dut.to_register25_data_in' => {
917 
      'hdlType' => 'std_logic_vector(31 downto 0)',
918 
      'width' => 32,
919 
    },
920 
    'sysgen_dut.to_register25_en' => {
921 
      'hdlType' => 'std_logic',
922 
      'width' => 1,
923 
    },
924 
    'sysgen_dut.to_register26_ce' => {
925 
      'hdlType' => 'std_logic',
926 
      'width' => 1,
927 
    },
928 
    'sysgen_dut.to_register26_clk' => {
929 
      'hdlType' => 'std_logic',
930 
      'width' => 1,
931 
    },
932 
    'sysgen_dut.to_register26_clr' => {
933 
      'hdlType' => 'std_logic',
934 
      'width' => 1,
935 
    },
936 
    'sysgen_dut.to_register26_data_in' => {
937 
      'hdlType' => 'std_logic',
938 
      'width' => 1,
939 
    },
940 
    'sysgen_dut.to_register26_en' => {
941 
      'hdlType' => 'std_logic',
942 
      'width' => 1,
943 
    },
944 
    'sysgen_dut.to_register27_ce' => {
945 
      'hdlType' => 'std_logic',
946 
      'width' => 1,
947 
    },
948 
    'sysgen_dut.to_register27_clk' => {
949 
      'hdlType' => 'std_logic',
950 
      'width' => 1,
951 
    },
952 
    'sysgen_dut.to_register27_clr' => {
953 
      'hdlType' => 'std_logic',
954 
      'width' => 1,
955 
    },
956 
    'sysgen_dut.to_register27_data_in' => {
957 
      'hdlType' => 'std_logic_vector(31 downto 0)',
958 
      'width' => 32,
959 
    },
960 
    'sysgen_dut.to_register27_en' => {
961 
      'hdlType' => 'std_logic',
962 
      'width' => 1,
963 
    },
964 
    'sysgen_dut.to_register2_ce' => {
965 
      'hdlType' => 'std_logic',
966 
      'width' => 1,
967 
    },
968 
    'sysgen_dut.to_register2_clk' => {
969 
      'hdlType' => 'std_logic',
970 
      'width' => 1,
971 
    },
972 
    'sysgen_dut.to_register2_clr' => {
973 
      'hdlType' => 'std_logic',
974 
      'width' => 1,
975 
    },
976 
    'sysgen_dut.to_register2_data_in' => {
977 
      'hdlType' => 'std_logic_vector(31 downto 0)',
978 
      'width' => 32,
979 
    },
980 
    'sysgen_dut.to_register2_en' => {
981 
      'hdlType' => 'std_logic',
982 
      'width' => 1,
983 
    },
984 
    'sysgen_dut.to_register3_ce' => {
985 
      'hdlType' => 'std_logic',
986 
      'width' => 1,
987 
    },
988 
    'sysgen_dut.to_register3_clk' => {
989 
      'hdlType' => 'std_logic',
990 
      'width' => 1,
991 
    },
992 
    'sysgen_dut.to_register3_clr' => {
993 
      'hdlType' => 'std_logic',
994 
      'width' => 1,
995 
    },
996 
    'sysgen_dut.to_register3_data_in' => {
997 
      'hdlType' => 'std_logic_vector(31 downto 0)',
998 
      'width' => 32,
999 
    },
1000 
    'sysgen_dut.to_register3_en' => {
1001 
      'hdlType' => 'std_logic',
1002 
      'width' => 1,
1003 
    },
1004 
    'sysgen_dut.to_register4_ce' => {
1005 
      'hdlType' => 'std_logic',
1006 
      'width' => 1,
1007 
    },
1008 
    'sysgen_dut.to_register4_clk' => {
1009 
      'hdlType' => 'std_logic',
1010 
      'width' => 1,
1011 
    },
1012 
    'sysgen_dut.to_register4_clr' => {
1013 
      'hdlType' => 'std_logic',
1014 
      'width' => 1,
1015 
    },
1016 
    'sysgen_dut.to_register4_data_in' => {
1017 
      'hdlType' => 'std_logic',
1018 
      'width' => 1,
1019 
    },
1020 
    'sysgen_dut.to_register4_en' => {
1021 
      'hdlType' => 'std_logic',
1022 
      'width' => 1,
1023 
    },
1024 
    'sysgen_dut.to_register5_ce' => {
1025 
      'hdlType' => 'std_logic',
1026 
      'width' => 1,
1027 
    },
1028 
    'sysgen_dut.to_register5_clk' => {
1029 
      'hdlType' => 'std_logic',
1030 
      'width' => 1,
1031 
    },
1032 
    'sysgen_dut.to_register5_clr' => {
1033 
      'hdlType' => 'std_logic',
1034 
      'width' => 1,
1035 
    },
1036 
    'sysgen_dut.to_register5_data_in' => {
1037 
      'hdlType' => 'std_logic',
1038 
      'width' => 1,
1039 
    },
1040 
    'sysgen_dut.to_register5_en' => {
1041 
      'hdlType' => 'std_logic',
1042 
      'width' => 1,
1043 
    },
1044 
    'sysgen_dut.to_register6_ce' => {
1045 
      'hdlType' => 'std_logic',
1046 
      'width' => 1,
1047 
    },
1048 
    'sysgen_dut.to_register6_clk' => {
1049 
      'hdlType' => 'std_logic',
1050 
      'width' => 1,
1051 
    },
1052 
    'sysgen_dut.to_register6_clr' => {
1053 
      'hdlType' => 'std_logic',
1054 
      'width' => 1,
1055 
    },
1056 
    'sysgen_dut.to_register6_data_in' => {
1057 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1058 
      'width' => 32,
1059 
    },
1060 
    'sysgen_dut.to_register6_en' => {
1061 
      'hdlType' => 'std_logic',
1062 
      'width' => 1,
1063 
    },
1064 
    'sysgen_dut.to_register7_ce' => {
1065 
      'hdlType' => 'std_logic',
1066 
      'width' => 1,
1067 
    },
1068 
    'sysgen_dut.to_register7_clk' => {
1069 
      'hdlType' => 'std_logic',
1070 
      'width' => 1,
1071 
    },
1072 
    'sysgen_dut.to_register7_clr' => {
1073 
      'hdlType' => 'std_logic',
1074 
      'width' => 1,
1075 
    },
1076 
    'sysgen_dut.to_register7_data_in' => {
1077 
      'hdlType' => 'std_logic',
1078 
      'width' => 1,
1079 
    },
1080 
    'sysgen_dut.to_register7_en' => {
1081 
      'hdlType' => 'std_logic',
1082 
      'width' => 1,
1083 
    },
1084 
    'sysgen_dut.to_register8_ce' => {
1085 
      'hdlType' => 'std_logic',
1086 
      'width' => 1,
1087 
    },
1088 
    'sysgen_dut.to_register8_clk' => {
1089 
      'hdlType' => 'std_logic',
1090 
      'width' => 1,
1091 
    },
1092 
    'sysgen_dut.to_register8_clr' => {
1093 
      'hdlType' => 'std_logic',
1094 
      'width' => 1,
1095 
    },
1096 
    'sysgen_dut.to_register8_data_in' => {
1097 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1098 
      'width' => 32,
1099 
    },
1100 
    'sysgen_dut.to_register8_en' => {
1101 
      'hdlType' => 'std_logic',
1102 
      'width' => 1,
1103 
    },
1104 
    'sysgen_dut.to_register9_ce' => {
1105 
      'hdlType' => 'std_logic',
1106 
      'width' => 1,
1107 
    },
1108 
    'sysgen_dut.to_register9_clk' => {
1109 
      'hdlType' => 'std_logic',
1110 
      'width' => 1,
1111 
    },
1112 
    'sysgen_dut.to_register9_clr' => {
1113 
      'hdlType' => 'std_logic',
1114 
      'width' => 1,
1115 
    },
1116 
    'sysgen_dut.to_register9_data_in' => {
1117 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1118 
      'width' => 32,
1119 
    },
1120 
    'sysgen_dut.to_register9_en' => {
1121 
      'hdlType' => 'std_logic',
1122 
      'width' => 1,
1123 
    },
1124 
    'sysgen_dut.to_register_ce' => {
1125 
      'hdlType' => 'std_logic',
1126 
      'width' => 1,
1127 
    },
1128 
    'sysgen_dut.to_register_clk' => {
1129 
      'hdlType' => 'std_logic',
1130 
      'width' => 1,
1131 
    },
1132 
    'sysgen_dut.to_register_clr' => {
1133 
      'hdlType' => 'std_logic',
1134 
      'width' => 1,
1135 
    },
1136 
    'sysgen_dut.to_register_data_in' => {
1137 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1138 
      'width' => 32,
1139 
    },
1140 
    'sysgen_dut.to_register_en' => {
1141 
      'hdlType' => 'std_logic',
1142 
      'width' => 1,
1143 
    },
1144 
    'sysgen_dut.user_int_1o' => {
1145 
      'hdlType' => 'std_logic',
1146 
      'width' => 1,
1147 
    },
1148 
    'sysgen_dut.user_int_2o' => {
1149 
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1150 
      'width' => 1,
1151 
    },
1152 
    'sysgen_dut.user_int_3o' => {
1153 
      'hdlType' => 'std_logic',
1154 
      'width' => 1,
1155 
    },
1156 
    'to_register.dout' => {
1157 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1158 
      'width' => 32,
1159 
    },
1160 
    'to_register1.dout' => {
1161 
      'hdlType' => 'std_logic',
1162 
      'width' => 1,
1163 
    },
1164 
    'to_register10.dout' => {
1165 
      'hdlType' => 'std_logic',
1166 
      'width' => 1,
1167 
    },
1168 
    'to_register11.dout' => {
1169 
      'hdlType' => 'std_logic',
1170 
      'width' => 1,
1171 
    },
1172 
    'to_register12.dout' => {
1173 
      'hdlType' => 'std_logic',
1174 
      'width' => 1,
1175 
    },
1176 
    'to_register13.dout' => {
1177 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1178 
      'width' => 32,
1179 
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1180 
    'to_register14.dout' => {
1181 
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1182 
      'width' => 1,
1183 
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1184 
    'to_register15.dout' => {
1185 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1186 
      'width' => 32,
1187 
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1188 
    'to_register16.dout' => {
1189 
      'hdlType' => 'std_logic',
1190 
      'width' => 1,
1191 
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1192 
    'to_register17.dout' => {
1193 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1194 
      'width' => 32,
1195 
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1196 
    'to_register18.dout' => {
1197 
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1198 
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1199 
    },
1200 
    'to_register19.dout' => {
1201 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1202 
      'width' => 32,
1203 
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1204 
    'to_register2.dout' => {
1205 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1206 
      'width' => 32,
1207 
    },
1208 
    'to_register20.dout' => {
1209 
      'hdlType' => 'std_logic',
1210 
      'width' => 1,
1211 
    },
1212 
    'to_register21.dout' => {
1213 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1214 
      'width' => 32,
1215 
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1216 
    'to_register22.dout' => {
1217 
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1218 
      'width' => 1,
1219 
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1220 
    'to_register23.dout' => {
1221 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1222 
      'width' => 32,
1223 
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1224 
    'to_register24.dout' => {
1225 
      'hdlType' => 'std_logic',
1226 
      'width' => 1,
1227 
    },
1228 
    'to_register25.dout' => {
1229 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1230 
      'width' => 32,
1231 
    },
1232 
    'to_register26.dout' => {
1233 
      'hdlType' => 'std_logic',
1234 
      'width' => 1,
1235 
    },
1236 
    'to_register27.dout' => {
1237 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1238 
      'width' => 32,
1239 
    },
1240 
    'to_register3.dout' => {
1241 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1242 
      'width' => 32,
1243 
    },
1244 
    'to_register4.dout' => {
1245 
      'hdlType' => 'std_logic',
1246 
      'width' => 1,
1247 
    },
1248 
    'to_register5.dout' => {
1249 
      'hdlType' => 'std_logic',
1250 
      'width' => 1,
1251 
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1252 
    'to_register6.dout' => {
1253 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1254 
      'width' => 32,
1255 
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1256 
    'to_register7.dout' => {
1257 
      'hdlType' => 'std_logic',
1258 
      'width' => 1,
1259 
    },
1260 
    'to_register8.dout' => {
1261 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1262 
      'width' => 32,
1263 
    },
1264 
    'to_register9.dout' => {
1265 
      'hdlType' => 'std_logic_vector(31 downto 0)',
1266 
      'width' => 32,
1267 
    },
1268 
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1269 
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1270 
    'bram_rd_addr' => {
1271 
      'connections' => { 'bram_rd_addr' => 'sysgen_dut.bram_rd_addr', },
1272 
      'entity' => {
1273 
        'attributes' => {
1274 
          'entityAlreadyNetlisted' => 1,
1275 
          'isGateway' => 1,
1276 
          'is_floating_block' => 1,
1277 
        },
1278 
        'entityName' => 'bram_rd_addr',
1279 
        'ports' => {
1280 
          'bram_rd_addr' => {
1281 
            'attributes' => {
1282 
              'bin_pt' => 0,
1283 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
1284 
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1285 
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1286 
              'must_be_hdl_vector' => 1,
1287 
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1288 
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1289 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr/BRAM_rd_addr',
1290 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr',
1291 
              'timingConstraint' => 'none',
1292 
              'type' => 'UFix_12_0',
1293 
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1294 
            'direction' => 'in',
1295 
            'hdlType' => 'std_logic_vector(11 downto 0)',
1296 
            'width' => 12,
1297 
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1298 
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1299 
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1300 
      'entityName' => 'bram_rd_addr',
1301 
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1302 
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1303 
      'connections' => { 'bram_rd_dout' => '.bram_rd_dout', },
1304 
      'entity' => {
1305 
        'attributes' => {
1306 
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1307 
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1308 
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1309 
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1310 
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1311 
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1312 
          'bram_rd_dout' => {
1313 
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1314 
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1315 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
1316 
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1317 
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1318 
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1319 
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1320 
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1321 
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1322 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_dout',
1323 
              'timingConstraint' => 'none',
1324 
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1325 
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1326 
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1327 
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1328 
            'width' => 64,
1329 
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1330 
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1331 
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1332 
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1333 
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1334 
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1335 
      'connections' => { 'bram_wr_addr' => 'sysgen_dut.bram_wr_addr', },
1336 
      'entity' => {
1337 
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1338 
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1339 
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1340 
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1341 
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1342 
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1343 
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1344 
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1345 
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1346 
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1347 
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1348 
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1349 
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1350 
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1351 
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1352 
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1353 
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1354 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_addr',
1355 
              'timingConstraint' => 'none',
1356 
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1357 
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1358 
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1359 
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1360 
            'width' => 12,
1361 
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1362 
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1363 
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1364 
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1365 
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1366 
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1367 
      'connections' => { 'bram_wr_din' => 'sysgen_dut.bram_wr_din', },
1368 
      'entity' => {
1369 
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1370 
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1371 
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1372 
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1373 
        },
1374 
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1375 
        'ports' => {
1376 
          'bram_wr_din' => {
1377 
            'attributes' => {
1378 
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1379 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
1380 
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1381 
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1382 
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1383 
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1384 
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1385 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_din/BRAM_wr_din',
1386 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_din',
1387 
              'timingConstraint' => 'none',
1388 
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1389 
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1390 
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1391 
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1392 
            'width' => 64,
1393 
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1394 
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1395 
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1396 
      'entityName' => 'bram_wr_din',
1397 
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1398 
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1399 
      'connections' => { 'bram_wr_en' => 'sysgen_dut.bram_wr_en', },
1400 
      'entity' => {
1401 
        'attributes' => {
1402 
          'entityAlreadyNetlisted' => 1,
1403 
          'isGateway' => 1,
1404 
          'is_floating_block' => 1,
1405 
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1406 
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1407 
        'ports' => {
1408 
          'bram_wr_en' => {
1409 
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1410 
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1411 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_en.dat',
1412 
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1413 
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1414 
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1415 
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1416 
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1417 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_en/BRAM_wr_en',
1418 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_en',
1419 
              'timingConstraint' => 'none',
1420 
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1421 
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1422 
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1423 
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1424 
            'width' => 8,
1425 
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1426 
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1427 
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1428 
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1429 
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1430 
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1431 
      'connections' => { 'fifo_rd_count' => '.fifo_rd_count', },
1432 
      'entity' => {
1433 
        'attributes' => {
1434 
          'entityAlreadyNetlisted' => 1,
1435 
          'isGateway' => 1,
1436 
          'is_floating_block' => 1,
1437 
        },
1438 
        'entityName' => 'fifo_rd_count',
1439 
        'ports' => {
1440 
          'fifo_rd_count' => {
1441 
            'attributes' => {
1442 
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1443 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_count.dat',
1444 
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1445 
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1446 
              'must_be_hdl_vector' => 1,
1447 
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1448 
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1449 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_count/FIFO_rd_count',
1450 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_count',
1451 
              'timingConstraint' => 'none',
1452 
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1453 
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1454 
            'direction' => 'out',
1455 
            'hdlType' => 'std_logic_vector(14 downto 0)',
1456 
            'width' => 15,
1457 
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1458 
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1459 
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1460 
      'entityName' => 'fifo_rd_count',
1461 
    },
1462 
    'fifo_rd_dout' => {
1463 
      'connections' => { 'fifo_rd_dout' => '.fifo_rd_dout', },
1464 
      'entity' => {
1465 
        'attributes' => {
1466 
          'entityAlreadyNetlisted' => 1,
1467 
          'isGateway' => 1,
1468 
          'is_floating_block' => 1,
1469 
        },
1470 
        'entityName' => 'fifo_rd_dout',
1471 
        'ports' => {
1472 
          'fifo_rd_dout' => {
1473 
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1474 
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1475 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_dout.dat',
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1477 
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              'must_be_hdl_vector' => 1,
1479 
              'period' => 1,
1480 
              'port_id' => 0,
1481 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_dout/FIFO_rd_dout',
1482 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_dout',
1483 
              'timingConstraint' => 'none',
1484 
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1485 
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1486 
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1487 
            'hdlType' => 'std_logic_vector(71 downto 0)',
1488 
            'width' => 72,
1489 
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1490 
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1491 
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1492 
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1493 
    },
1494 
    'fifo_rd_empty' => {
1495 
      'connections' => { 'fifo_rd_empty' => '.fifo_rd_empty', },
1496 
      'entity' => {
1497 
        'attributes' => {
1498 
          'entityAlreadyNetlisted' => 1,
1499 
          'isGateway' => 1,
1500 
          'is_floating_block' => 1,
1501 
        },
1502 
        'entityName' => 'fifo_rd_empty',
1503 
        'ports' => {
1504 
          'fifo_rd_empty' => {
1505 
            'attributes' => {
1506 
              'bin_pt' => 0,
1507 
              'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_empty.dat',
1508 
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1509 
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3390 
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3391 
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3392 
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3393 
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3394 
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3395 
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3396 
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3397 
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3398 
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3399 
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3400 
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3401 
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3402 
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3403 
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3404 
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3405 
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3406 
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3407 
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3408 
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3409 
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3410 
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3411 
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3412 
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3413 
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3414 
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3415 
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3416 
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3417 
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3418 
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3419 
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3420 
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3421 
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3422 
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3423 
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3424 
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3425 
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3426 
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3427 
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3428 
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3429 
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3430 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3431 
            'shared_memory_name' => 'register02tv',
3432 
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3433 
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3434 
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3435 
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3436 
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3437 
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3438 
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3439 
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3440 
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3441 
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3442 
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3443 
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3444 
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3445 
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3446 
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3447 
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3448 
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3449 
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3450 
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3451 
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3452 
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3453 
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3454 
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3455 
    },
3456 
    'from_register7' => {
3457 
      'connections' => { 'data_out' => 'from_register7.data_out', },
3458 
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3459 
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3460 
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3461 
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3462 
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3463 
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3464 
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3465 
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3466 
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3467 
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3468 
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3469 
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3470 
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3471 
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3472 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register7',
3473 
            'block_type' => 'fromreg',
3474 
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3475 
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3476 
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3477 
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3478 
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3479 
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3480 
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3481 
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3482 
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3483 
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3484 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3485 
            'shared_memory_name' => 'register03td',
3486 
          },
3487 
          'needs_vhdl_wrapper' => 0,
3488 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register7',
3489 
        },
3490 
        'entityName' => 'x_x120',
3491 
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3492 
          'data_out' => {
3493 
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3494 
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3495 
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3496 
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3497 
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3498 
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3499 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register7/data_out',
3500 
              'type' => 'UFix_32_0',
3501 
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3502 
            'direction' => 'out',
3503 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3504 
            'width' => 32,
3505 
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3506 
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3507 
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3508 
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3509 
    },
3510 
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3511 
      'connections' => { 'data_out' => 'from_register8.data_out', },
3512 
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3513 
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3514 
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3515 
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3516 
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3517 
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3518 
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3519 
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3520 
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3521 
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3522 
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3523 
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3524 
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3525 
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3526 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register8',
3527 
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3528 
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3529 
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3530 
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3531 
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3532 
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3533 
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3534 
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3535 
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3536 
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3537 
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3538 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3539 
            'shared_memory_name' => 'register03tv',
3540 
          },
3541 
          'needs_vhdl_wrapper' => 0,
3542 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register8',
3543 
        },
3544 
        'entityName' => 'x_x121',
3545 
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3546 
          'data_out' => {
3547 
            'attributes' => {
3548 
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3549 
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3550 
              'must_be_hdl_vector' => 1,
3551 
              'period' => 1,
3552 
              'port_id' => 0,
3553 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register8/data_out',
3554 
              'type' => 'UFix_1_0',
3555 
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3556 
            'direction' => 'out',
3557 
            'hdlType' => 'std_logic_vector(0 downto 0)',
3558 
            'width' => 1,
3559 
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3560 
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3561 
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3562 
      'entityName' => 'x_x121',
3563 
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3564 
    'from_register9' => {
3565 
      'connections' => { 'data_out' => 'from_register9.data_out', },
3566 
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3567 
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3568 
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3569 
          'generics' => [],
3570 
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3571 
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3572 
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3573 
            'Block_handle' => 2428.00048828125,
3574 
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3575 
            'MDL_handle' => 2083.00048828125,
3576 
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3577 
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3578 
            'block_config' => 'sysgen_blockset:fromreg_config',
3579 
            'block_handle' => 2428.00048828125,
3580 
            'block_name' => 'PCIe_UserLogic_00/USER_LOGIC/From Register9',
3581 
            'block_type' => 'fromreg',
3582 
            'dbl_ovrd' => 0,
3583 
            'gui_display_data_type' => 1,
3584 
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3585 
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3586 
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3587 
            'model_handle' => 2083.00048828125,
3588 
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3589 
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3590 
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3591 
            'preci_type' => 1,
3592 
            'sg_icon_stat' => '55,22,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]',
3593 
            'shared_memory_name' => 'register04td',
3594 
          },
3595 
          'needs_vhdl_wrapper' => 0,
3596 
          'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register9',
3597 
        },
3598 
        'entityName' => 'x_x122',
3599 
        'ports' => {
3600 
          'data_out' => {
3601 
            'attributes' => {
3602 
              'bin_pt' => 0,
3603 
              'is_floating_block' => 1,
3604 
              'must_be_hdl_vector' => 1,
3605 
              'period' => 1,
3606 
              'port_id' => 0,
3607 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register9/data_out',
3608 
              'type' => 'UFix_32_0',
3609 
            },
3610 
            'direction' => 'out',
3611 
            'hdlType' => 'std_logic_vector(31 downto 0)',
3612 
            'width' => 32,
3613 
          },
3614 
        },
3615 
      },
3616 
      'entityName' => 'x_x122',
3617 
    },
3618 
    'rst_i' => {
3619 
      'connections' => { 'rst_i' => '.rst_i', },
3620 
      'entity' => {
3621 
        'attributes' => {
3622 
          'entityAlreadyNetlisted' => 1,
3623 
          'isGateway' => 1,
3624 
          'is_floating_block' => 1,
3625 
        },
3626 
        'entityName' => 'rst_i',
3627 
        'ports' => {
3628 
          'rst_i' => {
3629 
            'attributes' => {
3630 
              'bin_pt' => 0,
3631 
              'inputFile' => 'pcie_userlogic_00_user_logic_rst_i.dat',
3632 
              'is_floating_block' => 1,
3633 
              'is_gateway_port' => 1,
3634 
              'must_be_hdl_vector' => 1,
3635 
              'period' => 1,
3636 
              'port_id' => 0,
3637 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/rst_i/rst_i',
3638 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/rst_i',
3639 
              'timingConstraint' => 'none',
3640 
              'type' => 'Bool',
3641 
            },
3642 
            'direction' => 'out',
3643 
            'hdlType' => 'std_logic',
3644 
            'width' => 1,
3645 
          },
3646 
        },
3647 
      },
3648 
      'entityName' => 'rst_i',
3649 
    },
3650 
    'rst_o' => {
3651 
      'connections' => { 'rst_o' => 'sysgen_dut.rst_o', },
3652 
      'entity' => {
3653 
        'attributes' => {
3654 
          'entityAlreadyNetlisted' => 1,
3655 
          'isGateway' => 1,
3656 
          'is_floating_block' => 1,
3657 
        },
3658 
        'entityName' => 'rst_o',
3659 
        'ports' => {
3660 
          'rst_o' => {
3661 
            'attributes' => {
3662 
              'bin_pt' => 0,
3663 
              'inputFile' => 'pcie_userlogic_00_user_logic_rst_o.dat',
3664 
              'is_floating_block' => 1,
3665 
              'is_gateway_port' => 1,
3666 
              'must_be_hdl_vector' => 1,
3667 
              'period' => 1,
3668 
              'port_id' => 0,
3669 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/rst_o/rst_o',
3670 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/rst_o',
3671 
              'timingConstraint' => 'none',
3672 
              'type' => 'Bool',
3673 
            },
3674 
            'direction' => 'in',
3675 
            'hdlType' => 'std_logic',
3676 
            'width' => 1,
3677 
          },
3678 
        },
3679 
      },
3680 
      'entityName' => 'rst_o',
3681 
    },
3682 
    'sysgen_dut' => {
3683 
      'connections' => {
3684 
        'bram_rd_addr' => 'sysgen_dut.bram_rd_addr',
3685 
        'bram_rd_dout' => '.bram_rd_dout',
3686 
        'bram_wr_addr' => 'sysgen_dut.bram_wr_addr',
3687 
        'bram_wr_din' => 'sysgen_dut.bram_wr_din',
3688 
        'bram_wr_en' => 'sysgen_dut.bram_wr_en',
3689 
        'clk' => '.clk',
3690 
        'fifo_rd_count' => '.fifo_rd_count',
3691 
        'fifo_rd_dout' => '.fifo_rd_dout',
3692 
        'fifo_rd_empty' => '.fifo_rd_empty',
3693 
        'fifo_rd_en' => 'sysgen_dut.fifo_rd_en',
3694 
        'fifo_rd_pempty' => '.fifo_rd_pempty',
3695 
        'fifo_rd_valid' => '.fifo_rd_valid',
3696 
        'fifo_wr_count' => '.fifo_wr_count',
3697 
        'fifo_wr_din' => 'sysgen_dut.fifo_wr_din',
3698 
        'fifo_wr_en' => 'sysgen_dut.fifo_wr_en',
3699 
        'fifo_wr_full' => '.fifo_wr_full',
3700 
        'fifo_wr_pfull' => '.fifo_wr_pfull',
3701 
        'from_register10_data_out' => 'from_register10.data_out',
3702 
        'from_register11_data_out' => 'from_register11.data_out',
3703 
        'from_register12_data_out' => 'from_register12.data_out',
3704 
        'from_register13_data_out' => 'from_register13.data_out',
3705 
        'from_register14_data_out' => 'from_register14.data_out',
3706 
        'from_register15_data_out' => 'from_register15.data_out',
3707 
        'from_register16_data_out' => 'from_register16.data_out',
3708 
        'from_register17_data_out' => 'from_register17.data_out',
3709 
        'from_register18_data_out' => 'from_register18.data_out',
3710 
        'from_register19_data_out' => 'from_register19.data_out',
3711 
        'from_register1_data_out' => 'from_register1.data_out',
3712 
        'from_register20_data_out' => 'from_register20.data_out',
3713 
        'from_register21_data_out' => 'from_register21.data_out',
3714 
        'from_register22_data_out' => 'from_register22.data_out',
3715 
        'from_register23_data_out' => 'from_register23.data_out',
3716 
        'from_register24_data_out' => 'from_register24.data_out',
3717 
        'from_register25_data_out' => 'from_register25.data_out',
3718 
        'from_register26_data_out' => 'from_register26.data_out',
3719 
        'from_register27_data_out' => 'from_register27.data_out',
3720 
        'from_register28_data_out' => 'from_register28.data_out',
3721 
        'from_register29_data_out' => 'from_register29.data_out',
3722 
        'from_register2_data_out' => 'from_register2.data_out',
3723 
        'from_register30_data_out' => 'from_register30.data_out',
3724 
        'from_register31_data_out' => 'from_register31.data_out',
3725 
        'from_register32_data_out' => 'from_register32.data_out',
3726 
        'from_register33_data_out' => 'from_register33.data_out',
3727 
        'from_register3_data_out' => 'from_register3.data_out',
3728 
        'from_register4_data_out' => 'from_register4.data_out',
3729 
        'from_register5_data_out' => 'from_register5.data_out',
3730 
        'from_register6_data_out' => 'from_register6.data_out',
3731 
        'from_register7_data_out' => 'from_register7.data_out',
3732 
        'from_register8_data_out' => 'from_register8.data_out',
3733 
        'from_register9_data_out' => 'from_register9.data_out',
3734 
        'from_register_data_out' => 'from_register.data_out',
3735 
        'rst_i' => '.rst_i',
3736 
        'rst_o' => 'sysgen_dut.rst_o',
3737 
        'to_register10_ce' => 'sysgen_dut.to_register10_ce',
3738 
        'to_register10_clk' => 'sysgen_dut.to_register10_clk',
3739 
        'to_register10_clr' => 'sysgen_dut.to_register10_clr',
3740 
        'to_register10_data_in' => 'sysgen_dut.to_register10_data_in',
3741 
        'to_register10_dout' => 'to_register10.dout',
3742 
        'to_register10_en' => 'sysgen_dut.to_register10_en',
3743 
        'to_register11_ce' => 'sysgen_dut.to_register11_ce',
3744 
        'to_register11_clk' => 'sysgen_dut.to_register11_clk',
3745 
        'to_register11_clr' => 'sysgen_dut.to_register11_clr',
3746 
        'to_register11_data_in' => 'sysgen_dut.to_register11_data_in',
3747 
        'to_register11_dout' => 'to_register11.dout',
3748 
        'to_register11_en' => 'sysgen_dut.to_register11_en',
3749 
        'to_register12_ce' => 'sysgen_dut.to_register12_ce',
3750 
        'to_register12_clk' => 'sysgen_dut.to_register12_clk',
3751 
        'to_register12_clr' => 'sysgen_dut.to_register12_clr',
3752 
        'to_register12_data_in' => 'sysgen_dut.to_register12_data_in',
3753 
        'to_register12_dout' => 'to_register12.dout',
3754 
        'to_register12_en' => 'sysgen_dut.to_register12_en',
3755 
        'to_register13_ce' => 'sysgen_dut.to_register13_ce',
3756 
        'to_register13_clk' => 'sysgen_dut.to_register13_clk',
3757 
        'to_register13_clr' => 'sysgen_dut.to_register13_clr',
3758 
        'to_register13_data_in' => 'sysgen_dut.to_register13_data_in',
3759 
        'to_register13_dout' => 'to_register13.dout',
3760 
        'to_register13_en' => 'sysgen_dut.to_register13_en',
3761 
        'to_register14_ce' => 'sysgen_dut.to_register14_ce',
3762 
        'to_register14_clk' => 'sysgen_dut.to_register14_clk',
3763 
        'to_register14_clr' => 'sysgen_dut.to_register14_clr',
3764 
        'to_register14_data_in' => 'sysgen_dut.to_register14_data_in',
3765 
        'to_register14_dout' => 'to_register14.dout',
3766 
        'to_register14_en' => 'sysgen_dut.to_register14_en',
3767 
        'to_register15_ce' => 'sysgen_dut.to_register15_ce',
3768 
        'to_register15_clk' => 'sysgen_dut.to_register15_clk',
3769 
        'to_register15_clr' => 'sysgen_dut.to_register15_clr',
3770 
        'to_register15_data_in' => 'sysgen_dut.to_register15_data_in',
3771 
        'to_register15_dout' => 'to_register15.dout',
3772 
        'to_register15_en' => 'sysgen_dut.to_register15_en',
3773 
        'to_register16_ce' => 'sysgen_dut.to_register16_ce',
3774 
        'to_register16_clk' => 'sysgen_dut.to_register16_clk',
3775 
        'to_register16_clr' => 'sysgen_dut.to_register16_clr',
3776 
        'to_register16_data_in' => 'sysgen_dut.to_register16_data_in',
3777 
        'to_register16_dout' => 'to_register16.dout',
3778 
        'to_register16_en' => 'sysgen_dut.to_register16_en',
3779 
        'to_register17_ce' => 'sysgen_dut.to_register17_ce',
3780 
        'to_register17_clk' => 'sysgen_dut.to_register17_clk',
3781 
        'to_register17_clr' => 'sysgen_dut.to_register17_clr',
3782 
        'to_register17_data_in' => 'sysgen_dut.to_register17_data_in',
3783 
        'to_register17_dout' => 'to_register17.dout',
3784 
        'to_register17_en' => 'sysgen_dut.to_register17_en',
3785 
        'to_register18_ce' => 'sysgen_dut.to_register18_ce',
3786 
        'to_register18_clk' => 'sysgen_dut.to_register18_clk',
3787 
        'to_register18_clr' => 'sysgen_dut.to_register18_clr',
3788 
        'to_register18_data_in' => 'sysgen_dut.to_register18_data_in',
3789 
        'to_register18_dout' => 'to_register18.dout',
3790 
        'to_register18_en' => 'sysgen_dut.to_register18_en',
3791 
        'to_register19_ce' => 'sysgen_dut.to_register19_ce',
3792 
        'to_register19_clk' => 'sysgen_dut.to_register19_clk',
3793 
        'to_register19_clr' => 'sysgen_dut.to_register19_clr',
3794 
        'to_register19_data_in' => 'sysgen_dut.to_register19_data_in',
3795 
        'to_register19_dout' => 'to_register19.dout',
3796 
        'to_register19_en' => 'sysgen_dut.to_register19_en',
3797 
        'to_register1_ce' => 'sysgen_dut.to_register1_ce',
3798 
        'to_register1_clk' => 'sysgen_dut.to_register1_clk',
3799 
        'to_register1_clr' => 'sysgen_dut.to_register1_clr',
3800 
        'to_register1_data_in' => 'sysgen_dut.to_register1_data_in',
3801 
        'to_register1_dout' => 'to_register1.dout',
3802 
        'to_register1_en' => 'sysgen_dut.to_register1_en',
3803 
        'to_register20_ce' => 'sysgen_dut.to_register20_ce',
3804 
        'to_register20_clk' => 'sysgen_dut.to_register20_clk',
3805 
        'to_register20_clr' => 'sysgen_dut.to_register20_clr',
3806 
        'to_register20_data_in' => 'sysgen_dut.to_register20_data_in',
3807 
        'to_register20_dout' => 'to_register20.dout',
3808 
        'to_register20_en' => 'sysgen_dut.to_register20_en',
3809 
        'to_register21_ce' => 'sysgen_dut.to_register21_ce',
3810 
        'to_register21_clk' => 'sysgen_dut.to_register21_clk',
3811 
        'to_register21_clr' => 'sysgen_dut.to_register21_clr',
3812 
        'to_register21_data_in' => 'sysgen_dut.to_register21_data_in',
3813 
        'to_register21_dout' => 'to_register21.dout',
3814 
        'to_register21_en' => 'sysgen_dut.to_register21_en',
3815 
        'to_register22_ce' => 'sysgen_dut.to_register22_ce',
3816 
        'to_register22_clk' => 'sysgen_dut.to_register22_clk',
3817 
        'to_register22_clr' => 'sysgen_dut.to_register22_clr',
3818 
        'to_register22_data_in' => 'sysgen_dut.to_register22_data_in',
3819 
        'to_register22_dout' => 'to_register22.dout',
3820 
        'to_register22_en' => 'sysgen_dut.to_register22_en',
3821 
        'to_register23_ce' => 'sysgen_dut.to_register23_ce',
3822 
        'to_register23_clk' => 'sysgen_dut.to_register23_clk',
3823 
        'to_register23_clr' => 'sysgen_dut.to_register23_clr',
3824 
        'to_register23_data_in' => 'sysgen_dut.to_register23_data_in',
3825 
        'to_register23_dout' => 'to_register23.dout',
3826 
        'to_register23_en' => 'sysgen_dut.to_register23_en',
3827 
        'to_register24_ce' => 'sysgen_dut.to_register24_ce',
3828 
        'to_register24_clk' => 'sysgen_dut.to_register24_clk',
3829 
        'to_register24_clr' => 'sysgen_dut.to_register24_clr',
3830 
        'to_register24_data_in' => 'sysgen_dut.to_register24_data_in',
3831 
        'to_register24_dout' => 'to_register24.dout',
3832 
        'to_register24_en' => 'sysgen_dut.to_register24_en',
3833 
        'to_register25_ce' => 'sysgen_dut.to_register25_ce',
3834 
        'to_register25_clk' => 'sysgen_dut.to_register25_clk',
3835 
        'to_register25_clr' => 'sysgen_dut.to_register25_clr',
3836 
        'to_register25_data_in' => 'sysgen_dut.to_register25_data_in',
3837 
        'to_register25_dout' => 'to_register25.dout',
3838 
        'to_register25_en' => 'sysgen_dut.to_register25_en',
3839 
        'to_register26_ce' => 'sysgen_dut.to_register26_ce',
3840 
        'to_register26_clk' => 'sysgen_dut.to_register26_clk',
3841 
        'to_register26_clr' => 'sysgen_dut.to_register26_clr',
3842 
        'to_register26_data_in' => 'sysgen_dut.to_register26_data_in',
3843 
        'to_register26_dout' => 'to_register26.dout',
3844 
        'to_register26_en' => 'sysgen_dut.to_register26_en',
3845 
        'to_register27_ce' => 'sysgen_dut.to_register27_ce',
3846 
        'to_register27_clk' => 'sysgen_dut.to_register27_clk',
3847 
        'to_register27_clr' => 'sysgen_dut.to_register27_clr',
3848 
        'to_register27_data_in' => 'sysgen_dut.to_register27_data_in',
3849 
        'to_register27_dout' => 'to_register27.dout',
3850 
        'to_register27_en' => 'sysgen_dut.to_register27_en',
3851 
        'to_register2_ce' => 'sysgen_dut.to_register2_ce',
3852 
        'to_register2_clk' => 'sysgen_dut.to_register2_clk',
3853 
        'to_register2_clr' => 'sysgen_dut.to_register2_clr',
3854 
        'to_register2_data_in' => 'sysgen_dut.to_register2_data_in',
3855 
        'to_register2_dout' => 'to_register2.dout',
3856 
        'to_register2_en' => 'sysgen_dut.to_register2_en',
3857 
        'to_register3_ce' => 'sysgen_dut.to_register3_ce',
3858 
        'to_register3_clk' => 'sysgen_dut.to_register3_clk',
3859 
        'to_register3_clr' => 'sysgen_dut.to_register3_clr',
3860 
        'to_register3_data_in' => 'sysgen_dut.to_register3_data_in',
3861 
        'to_register3_dout' => 'to_register3.dout',
3862 
        'to_register3_en' => 'sysgen_dut.to_register3_en',
3863 
        'to_register4_ce' => 'sysgen_dut.to_register4_ce',
3864 
        'to_register4_clk' => 'sysgen_dut.to_register4_clk',
3865 
        'to_register4_clr' => 'sysgen_dut.to_register4_clr',
3866 
        'to_register4_data_in' => 'sysgen_dut.to_register4_data_in',
3867 
        'to_register4_dout' => 'to_register4.dout',
3868 
        'to_register4_en' => 'sysgen_dut.to_register4_en',
3869 
        'to_register5_ce' => 'sysgen_dut.to_register5_ce',
3870 
        'to_register5_clk' => 'sysgen_dut.to_register5_clk',
3871 
        'to_register5_clr' => 'sysgen_dut.to_register5_clr',
3872 
        'to_register5_data_in' => 'sysgen_dut.to_register5_data_in',
3873 
        'to_register5_dout' => 'to_register5.dout',
3874 
        'to_register5_en' => 'sysgen_dut.to_register5_en',
3875 
        'to_register6_ce' => 'sysgen_dut.to_register6_ce',
3876 
        'to_register6_clk' => 'sysgen_dut.to_register6_clk',
3877 
        'to_register6_clr' => 'sysgen_dut.to_register6_clr',
3878 
        'to_register6_data_in' => 'sysgen_dut.to_register6_data_in',
3879 
        'to_register6_dout' => 'to_register6.dout',
3880 
        'to_register6_en' => 'sysgen_dut.to_register6_en',
3881 
        'to_register7_ce' => 'sysgen_dut.to_register7_ce',
3882 
        'to_register7_clk' => 'sysgen_dut.to_register7_clk',
3883 
        'to_register7_clr' => 'sysgen_dut.to_register7_clr',
3884 
        'to_register7_data_in' => 'sysgen_dut.to_register7_data_in',
3885 
        'to_register7_dout' => 'to_register7.dout',
3886 
        'to_register7_en' => 'sysgen_dut.to_register7_en',
3887 
        'to_register8_ce' => 'sysgen_dut.to_register8_ce',
3888 
        'to_register8_clk' => 'sysgen_dut.to_register8_clk',
3889 
        'to_register8_clr' => 'sysgen_dut.to_register8_clr',
3890 
        'to_register8_data_in' => 'sysgen_dut.to_register8_data_in',
3891 
        'to_register8_dout' => 'to_register8.dout',
3892 
        'to_register8_en' => 'sysgen_dut.to_register8_en',
3893 
        'to_register9_ce' => 'sysgen_dut.to_register9_ce',
3894 
        'to_register9_clk' => 'sysgen_dut.to_register9_clk',
3895 
        'to_register9_clr' => 'sysgen_dut.to_register9_clr',
3896 
        'to_register9_data_in' => 'sysgen_dut.to_register9_data_in',
3897 
        'to_register9_dout' => 'to_register9.dout',
3898 
        'to_register9_en' => 'sysgen_dut.to_register9_en',
3899 
        'to_register_ce' => 'sysgen_dut.to_register_ce',
3900 
        'to_register_clk' => 'sysgen_dut.to_register_clk',
3901 
        'to_register_clr' => 'sysgen_dut.to_register_clr',
3902 
        'to_register_data_in' => 'sysgen_dut.to_register_data_in',
3903 
        'to_register_dout' => 'to_register.dout',
3904 
        'to_register_en' => 'sysgen_dut.to_register_en',
3905 
        'user_int_1o' => 'sysgen_dut.user_int_1o',
3906 
        'user_int_2o' => 'sysgen_dut.user_int_2o',
3907 
        'user_int_3o' => 'sysgen_dut.user_int_3o',
3908 
      },
3909 
      'entity' => {
3910 
        'attributes' => {
3911 
          'entityAlreadyNetlisted' => 1,
3912 
          'hdlArchAttributes' => [],
3913 
          'hdlEntityAttributes' => [],
3914 
          'isClkWrapper' => 1,
3915 
        },
3916 
        'connections' => {
3917 
          'bram_rd_addr' => 'bram_rd_addr_net',
3918 
          'bram_rd_dout' => 'bram_rd_dout_net',
3919 
          'bram_wr_addr' => 'bram_wr_addr_net',
3920 
          'bram_wr_din' => 'bram_wr_din_net',
3921 
          'bram_wr_en' => 'bram_wr_en_net',
3922 
          'clk' => 'clkNet',
3923 
          'fifo_rd_count' => 'fifo_rd_count_net',
3924 
          'fifo_rd_dout' => 'fifo_rd_dout_net',
3925 
          'fifo_rd_empty' => 'fifo_rd_empty_net',
3926 
          'fifo_rd_en' => 'fifo_rd_en_net',
3927 
          'fifo_rd_pempty' => 'fifo_rd_pempty_net',
3928 
          'fifo_rd_valid' => 'fifo_rd_valid_net',
3929 
          'fifo_wr_count' => 'fifo_wr_count_net',
3930 
          'fifo_wr_din' => 'fifo_wr_din_net',
3931 
          'fifo_wr_en' => 'fifo_wr_en_net',
3932 
          'fifo_wr_full' => 'fifo_wr_full_net',
3933 
          'fifo_wr_pfull' => 'fifo_wr_pfull_net',
3934 
          'from_register10_data_out' => 'data_out_x1_net',
3935 
          'from_register11_data_out' => 'data_out_x2_net',
3936 
          'from_register12_data_out' => 'data_out_x3_net',
3937 
          'from_register13_data_out' => 'data_out_x4_net',
3938 
          'from_register14_data_out' => 'data_out_x5_net',
3939 
          'from_register15_data_out' => 'from_register15_data_out_net',
3940 
          'from_register16_data_out' => 'from_register16_data_out_net',
3941 
          'from_register17_data_out' => 'data_out_x8_net',
3942 
          'from_register18_data_out' => 'data_out_x9_net',
3943 
          'from_register19_data_out' => 'from_register19_data_out_net',
3944 
          'from_register1_data_out' => 'from_register1_data_out_net',
3945 
          'from_register20_data_out' => 'data_out_x12_net',
3946 
          'from_register21_data_out' => 'data_out_x13_net',
3947 
          'from_register22_data_out' => 'data_out_x14_net',
3948 
          'from_register23_data_out' => 'data_out_x15_net',
3949 
          'from_register24_data_out' => 'data_out_x16_net',
3950 
          'from_register25_data_out' => 'data_out_x17_net',
3951 
          'from_register26_data_out' => 'data_out_x18_net',
3952 
          'from_register27_data_out' => 'data_out_x19_net',
3953 
          'from_register28_data_out' => 'data_out_x20_net',
3954 
          'from_register29_data_out' => 'data_out_x21_net',
3955 
          'from_register2_data_out' => 'from_register2_data_out_net',
3956 
          'from_register30_data_out' => 'data_out_x23_net',
3957 
          'from_register31_data_out' => 'data_out_x24_net',
3958 
          'from_register32_data_out' => 'data_out_x25_net',
3959 
          'from_register33_data_out' => 'data_out_x26_net',
3960 
          'from_register3_data_out' => 'data_out_x22_net',
3961 
          'from_register4_data_out' => 'data_out_x27_net',
3962 
          'from_register5_data_out' => 'data_out_x28_net',
3963 
          'from_register6_data_out' => 'data_out_x29_net',
3964 
          'from_register7_data_out' => 'data_out_x30_net',
3965 
          'from_register8_data_out' => 'data_out_x31_net',
3966 
          'from_register9_data_out' => 'data_out_x32_net',
3967 
          'from_register_data_out' => 'from_register_data_out_net',
3968 
          'rst_i' => 'rst_i_net',
3969 
          'rst_o' => 'rst_o_net',
3970 
          'to_register10_ce' => 'ce_1_sg_x0',
3971 
          'to_register10_clk' => 'clk_1_sg_x0',
3972 
          'to_register10_clr' => [
3973 
            'constant',
3974 
            '\'0\'',
3975 
          ],
3976 
          'to_register10_data_in' => 'data_in_x1_net',
3977 
          'to_register10_dout' => 'to_register10_dout_net',
3978 
          'to_register10_en' => 'constant6_op_net_x2',
3979 
          'to_register11_ce' => 'ce_1_sg_x0',
3980 
          'to_register11_clk' => 'clk_1_sg_x0',
3981 
          'to_register11_clr' => [
3982 
            'constant',
3983 
            '\'0\'',
3984 
          ],
3985 
          'to_register11_data_in' => 'data_in_x2_net',
3986 
          'to_register11_dout' => 'to_register11_dout_net',
3987 
          'to_register11_en' => 'constant6_op_net_x3',
3988 
          'to_register12_ce' => 'ce_1_sg_x0',
3989 
          'to_register12_clk' => 'clk_1_sg_x0',
3990 
          'to_register12_clr' => [
3991 
            'constant',
3992 
            '\'0\'',
3993 
          ],
3994 
          'to_register12_data_in' => 'data_in_x3_net',
3995 
          'to_register12_dout' => 'to_register12_dout_net',
3996 
          'to_register12_en' => 'constant6_op_net_x4',
3997 
          'to_register13_ce' => 'ce_1_sg_x0',
3998 
          'to_register13_clk' => 'clk_1_sg_x0',
3999 
          'to_register13_clr' => [
4000 
            'constant',
4001 
            '\'0\'',
4002 
          ],
4003 
          'to_register13_data_in' => 'data_in_x4_net',
4004 
          'to_register13_dout' => 'to_register13_dout_net',
4005 
          'to_register13_en' => 'constant6_op_net_x5',
4006 
          'to_register14_ce' => 'ce_1_sg_x0',
4007 
          'to_register14_clk' => 'clk_1_sg_x0',
4008 
          'to_register14_clr' => [
4009 
            'constant',
4010 
            '\'0\'',
4011 
          ],
4012 
          'to_register14_data_in' => 'data_in_x5_net',
4013 
          'to_register14_dout' => 'to_register14_dout_net',
4014 
          'to_register14_en' => 'constant6_op_net_x6',
4015 
          'to_register15_ce' => 'ce_1_sg_x0',
4016 
          'to_register15_clk' => 'clk_1_sg_x0',
4017 
          'to_register15_clr' => [
4018 
            'constant',
4019 
            '\'0\'',
4020 
          ],
4021 
          'to_register15_data_in' => 'data_in_x6_net',
4022 
          'to_register15_dout' => 'to_register15_dout_net',
4023 
          'to_register15_en' => 'constant6_op_net_x7',
4024 
          'to_register16_ce' => 'ce_1_sg_x0',
4025 
          'to_register16_clk' => 'clk_1_sg_x0',
4026 
          'to_register16_clr' => [
4027 
            'constant',
4028 
            '\'0\'',
4029 
          ],
4030 
          'to_register16_data_in' => 'data_in_x7_net',
4031 
          'to_register16_dout' => 'to_register16_dout_net',
4032 
          'to_register16_en' => 'constant6_op_net_x8',
4033 
          'to_register17_ce' => 'ce_1_sg_x0',
4034 
          'to_register17_clk' => 'clk_1_sg_x0',
4035 
          'to_register17_clr' => [
4036 
            'constant',
4037 
            '\'0\'',
4038 
          ],
4039 
          'to_register17_data_in' => 'data_in_x8_net',
4040 
          'to_register17_dout' => 'to_register17_dout_net',
4041 
          'to_register17_en' => 'constant6_op_net_x9',
4042 
          'to_register18_ce' => 'ce_1_sg_x0',
4043 
          'to_register18_clk' => 'clk_1_sg_x0',
4044 
          'to_register18_clr' => [
4045 
            'constant',
4046 
            '\'0\'',
4047 
          ],
4048 
          'to_register18_data_in' => 'data_in_x9_net',
4049 
          'to_register18_dout' => 'to_register18_dout_net',
4050 
          'to_register18_en' => 'constant6_op_net_x10',
4051 
          'to_register19_ce' => 'ce_1_sg_x0',
4052 
          'to_register19_clk' => 'clk_1_sg_x0',
4053 
          'to_register19_clr' => [
4054 
            'constant',
4055 
            '\'0\'',
4056 
          ],
4057 
          'to_register19_data_in' => 'data_in_x10_net',
4058 
          'to_register19_dout' => 'to_register19_dout_net',
4059 
          'to_register19_en' => 'constant6_op_net_x11',
4060 
          'to_register1_ce' => 'ce_1_sg_x0',
4061 
          'to_register1_clk' => 'clk_1_sg_x0',
4062 
          'to_register1_clr' => [
4063 
            'constant',
4064 
            '\'0\'',
4065 
          ],
4066 
          'to_register1_data_in' => 'data_in_x0_net',
4067 
          'to_register1_dout' => 'to_register1_dout_net',
4068 
          'to_register1_en' => 'constant6_op_net_x1',
4069 
          'to_register20_ce' => 'ce_1_sg_x0',
4070 
          'to_register20_clk' => 'clk_1_sg_x0',
4071 
          'to_register20_clr' => [
4072 
            'constant',
4073 
            '\'0\'',
4074 
          ],
4075 
          'to_register20_data_in' => 'data_in_x12_net',
4076 
          'to_register20_dout' => 'to_register20_dout_net',
4077 
          'to_register20_en' => 'constant6_op_net_x13',
4078 
          'to_register21_ce' => 'ce_1_sg_x0',
4079 
          'to_register21_clk' => 'clk_1_sg_x0',
4080 
          'to_register21_clr' => [
4081 
            'constant',
4082 
            '\'0\'',
4083 
          ],
4084 
          'to_register21_data_in' => 'data_in_x13_net',
4085 
          'to_register21_dout' => 'to_register21_dout_net',
4086 
          'to_register21_en' => 'constant6_op_net_x14',
4087 
          'to_register22_ce' => 'ce_1_sg_x0',
4088 
          'to_register22_clk' => 'clk_1_sg_x0',
4089 
          'to_register22_clr' => [
4090 
            'constant',
4091 
            '\'0\'',
4092 
          ],
4093 
          'to_register22_data_in' => 'data_in_x14_net',
4094 
          'to_register22_dout' => 'to_register22_dout_net',
4095 
          'to_register22_en' => 'constant6_op_net_x15',
4096 
          'to_register23_ce' => 'ce_1_sg_x0',
4097 
          'to_register23_clk' => 'clk_1_sg_x0',
4098 
          'to_register23_clr' => [
4099 
            'constant',
4100 
            '\'0\'',
4101 
          ],
4102 
          'to_register23_data_in' => 'data_in_x15_net',
4103 
          'to_register23_dout' => 'to_register23_dout_net',
4104 
          'to_register23_en' => 'constant6_op_net_x16',
4105 
          'to_register24_ce' => 'ce_1_sg_x0',
4106 
          'to_register24_clk' => 'clk_1_sg_x0',
4107 
          'to_register24_clr' => [
4108 
            'constant',
4109 
            '\'0\'',
4110 
          ],
4111 
          'to_register24_data_in' => 'data_in_x16_net',
4112 
          'to_register24_dout' => 'to_register24_dout_net',
4113 
          'to_register24_en' => 'constant6_op_net_x17',
4114 
          'to_register25_ce' => 'ce_1_sg_x0',
4115 
          'to_register25_clk' => 'clk_1_sg_x0',
4116 
          'to_register25_clr' => [
4117 
            'constant',
4118 
            '\'0\'',
4119 
          ],
4120 
          'to_register25_data_in' => 'data_in_x17_net',
4121 
          'to_register25_dout' => 'to_register25_dout_net',
4122 
          'to_register25_en' => 'constant6_op_net_x18',
4123 
          'to_register26_ce' => 'ce_1_sg_x0',
4124 
          'to_register26_clk' => 'clk_1_sg_x0',
4125 
          'to_register26_clr' => [
4126 
            'constant',
4127 
            '\'0\'',
4128 
          ],
4129 
          'to_register26_data_in' => 'data_in_x18_net',
4130 
          'to_register26_dout' => 'to_register26_dout_net',
4131 
          'to_register26_en' => 'constant6_op_net_x19',
4132 
          'to_register27_ce' => 'ce_1_sg_x0',
4133 
          'to_register27_clk' => 'clk_1_sg_x0',
4134 
          'to_register27_clr' => [
4135 
            'constant',
4136 
            '\'0\'',
4137 
          ],
4138 
          'to_register27_data_in' => 'data_in_x19_net',
4139 
          'to_register27_dout' => 'to_register27_dout_net',
4140 
          'to_register27_en' => 'constant6_op_net_x20',
4141 
          'to_register2_ce' => 'ce_1_sg_x0',
4142 
          'to_register2_clk' => 'clk_1_sg_x0',
4143 
          'to_register2_clr' => [
4144 
            'constant',
4145 
            '\'0\'',
4146 
          ],
4147 
          'to_register2_data_in' => 'data_in_x11_net',
4148 
          'to_register2_dout' => 'to_register2_dout_net',
4149 
          'to_register2_en' => 'constant6_op_net_x12',
4150 
          'to_register3_ce' => 'ce_1_sg_x0',
4151 
          'to_register3_clk' => 'clk_1_sg_x0',
4152 
          'to_register3_clr' => [
4153 
            'constant',
4154 
            '\'0\'',
4155 
          ],
4156 
          'to_register3_data_in' => 'data_in_x20_net',
4157 
          'to_register3_dout' => 'to_register3_dout_net',
4158 
          'to_register3_en' => 'constant6_op_net_x21',
4159 
          'to_register4_ce' => 'ce_1_sg_x0',
4160 
          'to_register4_clk' => 'clk_1_sg_x0',
4161 
          'to_register4_clr' => [
4162 
            'constant',
4163 
            '\'0\'',
4164 
          ],
4165 
          'to_register4_data_in' => 'data_in_x21_net',
4166 
          'to_register4_dout' => 'to_register4_dout_net',
4167 
          'to_register4_en' => 'constant6_op_net_x22',
4168 
          'to_register5_ce' => 'ce_1_sg_x0',
4169 
          'to_register5_clk' => 'clk_1_sg_x0',
4170 
          'to_register5_clr' => [
4171 
            'constant',
4172 
            '\'0\'',
4173 
          ],
4174 
          'to_register5_data_in' => 'data_in_x22_net',
4175 
          'to_register5_dout' => 'to_register5_dout_net',
4176 
          'to_register5_en' => 'constant6_op_net_x23',
4177 
          'to_register6_ce' => 'ce_1_sg_x0',
4178 
          'to_register6_clk' => 'clk_1_sg_x0',
4179 
          'to_register6_clr' => [
4180 
            'constant',
4181 
            '\'0\'',
4182 
          ],
4183 
          'to_register6_data_in' => 'data_in_x23_net',
4184 
          'to_register6_dout' => 'to_register6_dout_net',
4185 
          'to_register6_en' => 'constant6_op_net_x24',
4186 
          'to_register7_ce' => 'ce_1_sg_x0',
4187 
          'to_register7_clk' => 'clk_1_sg_x0',
4188 
          'to_register7_clr' => [
4189 
            'constant',
4190 
            '\'0\'',
4191 
          ],
4192 
          'to_register7_data_in' => 'data_in_x24_net',
4193 
          'to_register7_dout' => 'to_register7_dout_net',
4194 
          'to_register7_en' => 'constant6_op_net_x25',
4195 
          'to_register8_ce' => 'ce_1_sg_x0',
4196 
          'to_register8_clk' => 'clk_1_sg_x0',
4197 
          'to_register8_clr' => [
4198 
            'constant',
4199 
            '\'0\'',
4200 
          ],
4201 
          'to_register8_data_in' => 'data_in_x25_net',
4202 
          'to_register8_dout' => 'to_register8_dout_net',
4203 
          'to_register8_en' => 'constant6_op_net_x26',
4204 
          'to_register9_ce' => 'ce_1_sg_x0',
4205 
          'to_register9_clk' => 'clk_1_sg_x0',
4206 
          'to_register9_clr' => [
4207 
            'constant',
4208 
            '\'0\'',
4209 
          ],
4210 
          'to_register9_data_in' => 'data_in_x26_net',
4211 
          'to_register9_dout' => 'to_register9_dout_net',
4212 
          'to_register9_en' => 'constant6_op_net_x27',
4213 
          'to_register_ce' => 'ce_1_sg_x0',
4214 
          'to_register_clk' => 'clk_1_sg_x0',
4215 
          'to_register_clr' => [
4216 
            'constant',
4217 
            '\'0\'',
4218 
          ],
4219 
          'to_register_data_in' => 'data_in_net',
4220 
          'to_register_dout' => 'to_register_dout_net',
4221 
          'to_register_en' => 'constant6_op_net_x0',
4222 
          'user_int_1o' => 'user_int_1o_net',
4223 
          'user_int_2o' => 'user_int_2o_net',
4224 
          'user_int_3o' => 'user_int_3o_net',
4225 
        },
4226 
        'entityName' => 'user_logic_cw',
4227 
        'nets' => {
4228 
          'bram_rd_addr_net' => {
4229 
            'attributes' => {
4230 
              'hdlNetAttributes' => [],
4231 
            },
4232 
            'hdlType' => 'std_logic_vector(11 downto 0)',
4233 
            'width' => 12,
4234 
          },
4235 
          'bram_rd_dout_net' => {
4236 
            'attributes' => {
4237 
              'hdlNetAttributes' => [],
4238 
            },
4239 
            'hdlType' => 'std_logic_vector(63 downto 0)',
4240 
            'width' => 64,
4241 
          },
4242 
          'bram_wr_addr_net' => {
4243 
            'attributes' => {
4244 
              'hdlNetAttributes' => [],
4245 
            },
4246 
            'hdlType' => 'std_logic_vector(11 downto 0)',
4247 
            'width' => 12,
4248 
          },
4249 
          'bram_wr_din_net' => {
4250 
            'attributes' => {
4251 
              'hdlNetAttributes' => [],
4252 
            },
4253 
            'hdlType' => 'std_logic_vector(63 downto 0)',
4254 
            'width' => 64,
4255 
          },
4256 
          'bram_wr_en_net' => {
4257 
            'attributes' => {
4258 
              'hdlNetAttributes' => [],
4259 
            },
4260 
            'hdlType' => 'std_logic_vector(7 downto 0)',
4261 
            'width' => 8,
4262 
          },
4263 
          'ce_1_sg_x0' => {
4264 
            'attributes' => {
4265 
              'hdlNetAttributes' => [
4266 
                [
4267 
                  'MAX_FANOUT',
4268 
                  'string',
4269 
                  '"REDUCE"',
4270 
                ],
4271 
              ],
4272 
            },
4273 
            'hdlType' => 'std_logic',
4274 
            'width' => 1,
4275 
          },
4276 
          'clkNet' => {
4277 
            'attributes' => {
4278 
              'hdlNetAttributes' => [],
4279 
            },
4280 
            'hdlType' => 'std_logic',
4281 
            'width' => 1,
4282 
          },
4283 
          'clk_1_sg_x0' => {
4284 
            'attributes' => {
4285 
              'hdlNetAttributes' => [],
4286 
            },
4287 
            'hdlType' => 'std_logic',
4288 
            'width' => 1,
4289 
          },
4290 
          'constant6_op_net_x0' => {
4291 
            'attributes' => {
4292 
              'hdlNetAttributes' => [],
4293 
            },
4294 
            'hdlType' => 'std_logic',
4295 
            'width' => 1,
4296 
          },
4297 
          'constant6_op_net_x1' => {
4298 
            'attributes' => {
4299 
              'hdlNetAttributes' => [],
4300 
            },
4301 
            'hdlType' => 'std_logic',
4302 
            'width' => 1,
4303 
          },
4304 
          'constant6_op_net_x10' => {
4305 
            'attributes' => {
4306 
              'hdlNetAttributes' => [],
4307 
            },
4308 
            'hdlType' => 'std_logic',
4309 
            'width' => 1,
4310 
          },
4311 
          'constant6_op_net_x11' => {
4312 
            'attributes' => {
4313 
              'hdlNetAttributes' => [],
4314 
            },
4315 
            'hdlType' => 'std_logic',
4316 
            'width' => 1,
4317 
          },
4318 
          'constant6_op_net_x12' => {
4319 
            'attributes' => {
4320 
              'hdlNetAttributes' => [],
4321 
            },
4322 
            'hdlType' => 'std_logic',
4323 
            'width' => 1,
4324 
          },
4325 
          'constant6_op_net_x13' => {
4326 
            'attributes' => {
4327 
              'hdlNetAttributes' => [],
4328 
            },
4329 
            'hdlType' => 'std_logic',
4330 
            'width' => 1,
4331 
          },
4332 
          'constant6_op_net_x14' => {
4333 
            'attributes' => {
4334 
              'hdlNetAttributes' => [],
4335 
            },
4336 
            'hdlType' => 'std_logic',
4337 
            'width' => 1,
4338 
          },
4339 
          'constant6_op_net_x15' => {
4340 
            'attributes' => {
4341 
              'hdlNetAttributes' => [],
4342 
            },
4343 
            'hdlType' => 'std_logic',
4344 
            'width' => 1,
4345 
          },
4346 
          'constant6_op_net_x16' => {
4347 
            'attributes' => {
4348 
              'hdlNetAttributes' => [],
4349 
            },
4350 
            'hdlType' => 'std_logic',
4351 
            'width' => 1,
4352 
          },
4353 
          'constant6_op_net_x17' => {
4354 
            'attributes' => {
4355 
              'hdlNetAttributes' => [],
4356 
            },
4357 
            'hdlType' => 'std_logic',
4358 
            'width' => 1,
4359 
          },
4360 
          'constant6_op_net_x18' => {
4361 
            'attributes' => {
4362 
              'hdlNetAttributes' => [],
4363 
            },
4364 
            'hdlType' => 'std_logic',
4365 
            'width' => 1,
4366 
          },
4367 
          'constant6_op_net_x19' => {
4368 
            'attributes' => {
4369 
              'hdlNetAttributes' => [],
4370 
            },
4371 
            'hdlType' => 'std_logic',
4372 
            'width' => 1,
4373 
          },
4374 
          'constant6_op_net_x2' => {
4375 
            'attributes' => {
4376 
              'hdlNetAttributes' => [],
4377 
            },
4378 
            'hdlType' => 'std_logic',
4379 
            'width' => 1,
4380 
          },
4381 
          'constant6_op_net_x20' => {
4382 
            'attributes' => {
4383 
              'hdlNetAttributes' => [],
4384 
            },
4385 
            'hdlType' => 'std_logic',
4386 
            'width' => 1,
4387 
          },
4388 
          'constant6_op_net_x21' => {
4389 
            'attributes' => {
4390 
              'hdlNetAttributes' => [],
4391 
            },
4392 
            'hdlType' => 'std_logic',
4393 
            'width' => 1,
4394 
          },
4395 
          'constant6_op_net_x22' => {
4396 
            'attributes' => {
4397 
              'hdlNetAttributes' => [],
4398 
            },
4399 
            'hdlType' => 'std_logic',
4400 
            'width' => 1,
4401 
          },
4402 
          'constant6_op_net_x23' => {
4403 
            'attributes' => {
4404 
              'hdlNetAttributes' => [],
4405 
            },
4406 
            'hdlType' => 'std_logic',
4407 
            'width' => 1,
4408 
          },
4409 
          'constant6_op_net_x24' => {
4410 
            'attributes' => {
4411 
              'hdlNetAttributes' => [],
4412 
            },
4413 
            'hdlType' => 'std_logic',
4414 
            'width' => 1,
4415 
          },
4416 
          'constant6_op_net_x25' => {
4417 
            'attributes' => {
4418 
              'hdlNetAttributes' => [],
4419 
            },
4420 
            'hdlType' => 'std_logic',
4421 
            'width' => 1,
4422 
          },
4423 
          'constant6_op_net_x26' => {
4424 
            'attributes' => {
4425 
              'hdlNetAttributes' => [],
4426 
            },
4427 
            'hdlType' => 'std_logic',
4428 
            'width' => 1,
4429 
          },
4430 
          'constant6_op_net_x27' => {
4431 
            'attributes' => {
4432 
              'hdlNetAttributes' => [],
4433 
            },
4434 
            'hdlType' => 'std_logic',
4435 
            'width' => 1,
4436 
          },
4437 
          'constant6_op_net_x3' => {
4438 
            'attributes' => {
4439 
              'hdlNetAttributes' => [],
4440 
            },
4441 
            'hdlType' => 'std_logic',
4442 
            'width' => 1,
4443 
          },
4444 
          'constant6_op_net_x4' => {
4445 
            'attributes' => {
4446 
              'hdlNetAttributes' => [],
4447 
            },
4448 
            'hdlType' => 'std_logic',
4449 
            'width' => 1,
4450 
          },
4451 
          'constant6_op_net_x5' => {
4452 
            'attributes' => {
4453 
              'hdlNetAttributes' => [],
4454 
            },
4455 
            'hdlType' => 'std_logic',
4456 
            'width' => 1,
4457 
          },
4458 
          'constant6_op_net_x6' => {
4459 
            'attributes' => {
4460 
              'hdlNetAttributes' => [],
4461 
            },
4462 
            'hdlType' => 'std_logic',
4463 
            'width' => 1,
4464 
          },
4465 
          'constant6_op_net_x7' => {
4466 
            'attributes' => {
4467 
              'hdlNetAttributes' => [],
4468 
            },
4469 
            'hdlType' => 'std_logic',
4470 
            'width' => 1,
4471 
          },
4472 
          'constant6_op_net_x8' => {
4473 
            'attributes' => {
4474 
              'hdlNetAttributes' => [],
4475 
            },
4476 
            'hdlType' => 'std_logic',
4477 
            'width' => 1,
4478 
          },
4479 
          'constant6_op_net_x9' => {
4480 
            'attributes' => {
4481 
              'hdlNetAttributes' => [],
4482 
            },
4483 
            'hdlType' => 'std_logic',
4484 
            'width' => 1,
4485 
          },
4486 
          'data_in_net' => {
4487 
            'attributes' => {
4488 
              'hdlNetAttributes' => [],
4489 
            },
4490 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4491 
            'width' => 32,
4492 
          },
4493 
          'data_in_x0_net' => {
4494 
            'attributes' => {
4495 
              'hdlNetAttributes' => [],
4496 
            },
4497 
            'hdlType' => 'std_logic',
4498 
            'width' => 1,
4499 
          },
4500 
          'data_in_x10_net' => {
4501 
            'attributes' => {
4502 
              'hdlNetAttributes' => [],
4503 
            },
4504 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4505 
            'width' => 32,
4506 
          },
4507 
          'data_in_x11_net' => {
4508 
            'attributes' => {
4509 
              'hdlNetAttributes' => [],
4510 
            },
4511 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4512 
            'width' => 32,
4513 
          },
4514 
          'data_in_x12_net' => {
4515 
            'attributes' => {
4516 
              'hdlNetAttributes' => [],
4517 
            },
4518 
            'hdlType' => 'std_logic',
4519 
            'width' => 1,
4520 
          },
4521 
          'data_in_x13_net' => {
4522 
            'attributes' => {
4523 
              'hdlNetAttributes' => [],
4524 
            },
4525 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4526 
            'width' => 32,
4527 
          },
4528 
          'data_in_x14_net' => {
4529 
            'attributes' => {
4530 
              'hdlNetAttributes' => [],
4531 
            },
4532 
            'hdlType' => 'std_logic',
4533 
            'width' => 1,
4534 
          },
4535 
          'data_in_x15_net' => {
4536 
            'attributes' => {
4537 
              'hdlNetAttributes' => [],
4538 
            },
4539 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4540 
            'width' => 32,
4541 
          },
4542 
          'data_in_x16_net' => {
4543 
            'attributes' => {
4544 
              'hdlNetAttributes' => [],
4545 
            },
4546 
            'hdlType' => 'std_logic',
4547 
            'width' => 1,
4548 
          },
4549 
          'data_in_x17_net' => {
4550 
            'attributes' => {
4551 
              'hdlNetAttributes' => [],
4552 
            },
4553 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4554 
            'width' => 32,
4555 
          },
4556 
          'data_in_x18_net' => {
4557 
            'attributes' => {
4558 
              'hdlNetAttributes' => [],
4559 
            },
4560 
            'hdlType' => 'std_logic',
4561 
            'width' => 1,
4562 
          },
4563 
          'data_in_x19_net' => {
4564 
            'attributes' => {
4565 
              'hdlNetAttributes' => [],
4566 
            },
4567 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4568 
            'width' => 32,
4569 
          },
4570 
          'data_in_x1_net' => {
4571 
            'attributes' => {
4572 
              'hdlNetAttributes' => [],
4573 
            },
4574 
            'hdlType' => 'std_logic',
4575 
            'width' => 1,
4576 
          },
4577 
          'data_in_x20_net' => {
4578 
            'attributes' => {
4579 
              'hdlNetAttributes' => [],
4580 
            },
4581 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4582 
            'width' => 32,
4583 
          },
4584 
          'data_in_x21_net' => {
4585 
            'attributes' => {
4586 
              'hdlNetAttributes' => [],
4587 
            },
4588 
            'hdlType' => 'std_logic',
4589 
            'width' => 1,
4590 
          },
4591 
          'data_in_x22_net' => {
4592 
            'attributes' => {
4593 
              'hdlNetAttributes' => [],
4594 
            },
4595 
            'hdlType' => 'std_logic',
4596 
            'width' => 1,
4597 
          },
4598 
          'data_in_x23_net' => {
4599 
            'attributes' => {
4600 
              'hdlNetAttributes' => [],
4601 
            },
4602 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4603 
            'width' => 32,
4604 
          },
4605 
          'data_in_x24_net' => {
4606 
            'attributes' => {
4607 
              'hdlNetAttributes' => [],
4608 
            },
4609 
            'hdlType' => 'std_logic',
4610 
            'width' => 1,
4611 
          },
4612 
          'data_in_x25_net' => {
4613 
            'attributes' => {
4614 
              'hdlNetAttributes' => [],
4615 
            },
4616 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4617 
            'width' => 32,
4618 
          },
4619 
          'data_in_x26_net' => {
4620 
            'attributes' => {
4621 
              'hdlNetAttributes' => [],
4622 
            },
4623 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4624 
            'width' => 32,
4625 
          },
4626 
          'data_in_x2_net' => {
4627 
            'attributes' => {
4628 
              'hdlNetAttributes' => [],
4629 
            },
4630 
            'hdlType' => 'std_logic',
4631 
            'width' => 1,
4632 
          },
4633 
          'data_in_x3_net' => {
4634 
            'attributes' => {
4635 
              'hdlNetAttributes' => [],
4636 
            },
4637 
            'hdlType' => 'std_logic',
4638 
            'width' => 1,
4639 
          },
4640 
          'data_in_x4_net' => {
4641 
            'attributes' => {
4642 
              'hdlNetAttributes' => [],
4643 
            },
4644 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4645 
            'width' => 32,
4646 
          },
4647 
          'data_in_x5_net' => {
4648 
            'attributes' => {
4649 
              'hdlNetAttributes' => [],
4650 
            },
4651 
            'hdlType' => 'std_logic',
4652 
            'width' => 1,
4653 
          },
4654 
          'data_in_x6_net' => {
4655 
            'attributes' => {
4656 
              'hdlNetAttributes' => [],
4657 
            },
4658 
            'hdlType' => 'std_logic_vector(31 downto 0)',
4659 
            'width' => 32,
4660 
          },
4661 
          'data_in_x7_net' => {
4662 
            'attributes' => {
4663 
              'hdlNetAttributes' => [],
4664 
            },
4665 
            'hdlType' => 'std_logic',
4666 
            'width' => 1,
4667 
          },
4668 
          'data_in_x8_net' => {
4669 
            'attributes' => {
4670 
              'hdlNetAttributes' => [],
4671 
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5300 
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5301 
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8384 
              'timingConstraint' => 'none',
8385 
              'type' => 'Bool',
8386 
            },
8387 
            'direction' => 'out',
8388 
            'hdlType' => 'std_logic',
8389 
            'width' => 1,
8390 
          },
8391 
          'user_int_2o' => {
8392 
            'attributes' => {
8393 
              'bin_pt' => 0,
8394 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
8395 
              'is_floating_block' => 1,
8396 
              'is_gateway_port' => 1,
8397 
              'must_be_hdl_vector' => 1,
8398 
              'period' => 1,
8399 
              'port_id' => 0,
8400 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
8401 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
8402 
              'timingConstraint' => 'none',
8403 
              'type' => 'Bool',
8404 
            },
8405 
            'direction' => 'out',
8406 
            'hdlType' => 'std_logic',
8407 
            'width' => 1,
8408 
          },
8409 
          'user_int_3o' => {
8410 
            'attributes' => {
8411 
              'bin_pt' => 0,
8412 
              'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
8413 
              'is_floating_block' => 1,
8414 
              'is_gateway_port' => 1,
8415 
              'must_be_hdl_vector' => 1,
8416 
              'period' => 1,
8417 
              'port_id' => 0,
8418 
              'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o/user_int_3o',
8419 
              'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o',
8420 
              'timingConstraint' => 'none',
8421 
              'type' => 'Bool',
8422 
            },
8423 
            'direction' => 'out',
8424 
            'hdlType' => 'std_logic',
8425 
            'width' => 1,
8426 
          },
8427 
        },
8428 
        'subblocks' => {
8429 
          'default_clock_driver_x0' => {
8430 
            'connections' => {
8431 
              'ce_1' => 'ce_1_sg_x0',
8432 
              'clk_1' => 'clk_1_sg_x0',
8433 
              'sysce' => [
8434 
                'constant',
8435 
                '\'1\'',
8436 
              ],
8437 
              'sysce_clr' => [
8438 
                'constant',
8439 
                '\'0\'',
8440 
              ],
8441 
              'sysclk' => 'clkNet',
8442 
            },
8443 
            'entity' => {
8444 
              'attributes' => {
8445 
                'domain' => 'default',
8446 
                'hdlArchAttributes' => [
8447 
                  [
8448 
                    'syn_noprune',
8449 
                    'boolean',
8450 
                    'true',
8451 
                  ],
8452 
                  [
8453 
                    'optimize_primitives',
8454 
                    'boolean',
8455 
                    'false',
8456 
                  ],
8457 
                  [
8458 
                    'dont_touch',
8459 
                    'boolean',
8460 
                    'true',
8461 
                  ],
8462 
                ],
8463 
                'hdlEntityAttributes' => [],
8464 
                'isClkDriver' => 1,
8465 
              },
8466 
              'entityName' => 'default_clock_driver',
8467 
              'ports' => {
8468 
                'ce_1' => {
8469 
                  'attributes' => {
8470 
                    'domain' => 'default',
8471 
                    'group' => 1,
8472 
                    'isCe' => 1,
8473 
                    'period' => 1,
8474 
                    'type' => 'logic',
8475 
                  },
8476 
                  'direction' => 'out',
8477 
                  'hdlType' => 'std_logic',
8478 
                  'width' => 1,
8479 
                },
8480 
                'clk_1' => {
8481 
                  'attributes' => {
8482 
                    'domain' => 'default',
8483 
                    'group' => 1,
8484 
                    'isClk' => 1,
8485 
                    'period' => 1,
8486 
                    'type' => 'logic',
8487 
                  },
8488 
                  'direction' => 'out',
8489 
                  'hdlType' => 'std_logic',
8490 
                  'width' => 1,
8491 
                },
8492 
                'sysce' => {
8493 
                  'attributes' => {
8494 
                    'group' => 6,
8495 
                    'isCe' => 1,
8496 
                    'period' => 1,
8497 
                  },
8498 
                  'direction' => 'in',
8499 
                  'hdlType' => 'std_logic',
8500 
                  'width' => 1,
8501 
                },
8502 
                'sysce_clr' => {
8503 
                  'attributes' => {
8504 
                    'group' => 6,
8505 
                    'isClr' => 1,
8506 
                    'period' => 1,
8507 
                  },
8508 
                  'direction' => 'in',
8509 
                  'hdlType' => 'std_logic',
8510 
                  'width' => 1,
8511 
                },
8512 
                'sysclk' => {
8513 
                  'attributes' => {
8514 
                    'group' => 6,
8515 
                    'isClk' => 1,
8516 
                    'period' => 1,
8517 
                  },
8518 
                  'direction' => 'in',
8519 
                  'hdlType' => 'std_logic',
8520 
                  'width' => 1,
8521 
                },
8522 
              },
8523 
            },
8524 
            'entityName' => 'default_clock_driver',
8525 
          },
8526 
          'persistentdff_inst' => {
8527 
            'connections' => {
8528 
              'clk' => 'clkNet',
8529 
              'd' => 'persistentdff_inst_q',
8530 
              'q' => 'persistentdff_inst_q',
8531 
            },
8532 
            'entity' => {
8533 
              'attributes' => {
8534 
                'entityAlreadyNetlisted' => 1,
8535 
                'hdlCompAttributes' => [
8536 
                  [
8537 
                    'syn_black_box',
8538 
                    'boolean',
8539 
                    'true',
8540 
                  ],
8541 
                  [
8542 
                    'box_type',
8543 
                    'string',
8544 
                    '"black_box"',
8545 
                  ],
8546 
                ],
8547 
                'is_persistent_dff' => 1,
8548 
                'needsComponentDeclaration' => 1,
8549 
              },
8550 
              'entityName' => 'xlpersistentdff',
8551 
              'ports' => {
8552 
                'clk' => {
8553 
                  'direction' => 'in',
8554 
                  'hdlType' => 'std_logic',
8555 
                  'width' => 1,
8556 
                },
8557 
                'd' => {
8558 
                  'direction' => 'in',
8559 
                  'hdlType' => 'std_logic',
8560 
                  'width' => 1,
8561 
                },
8562 
                'q' => {
8563 
                  'direction' => 'out',
8564 
                  'hdlType' => 'std_logic',
8565 
                  'width' => 1,
8566 
                },
8567 
              },
8568 
            },
8569 
            'entityName' => 'xlpersistentdff',
8570 
          },
8571 
          'user_logic_x0' => {
8572 
            'connections' => {
8573 
              'bram_rd_addr' => 'bram_rd_addr_net',
8574 
              'bram_rd_dout' => 'bram_rd_dout_net',
8575 
              'bram_wr_addr' => 'bram_wr_addr_net',
8576 
              'bram_wr_din' => 'bram_wr_din_net',
8577 
              'bram_wr_en' => 'bram_wr_en_net',
8578 
              'ce_1' => 'ce_1_sg_x0',
8579 
              'clk_1' => 'clk_1_sg_x0',
8580 
              'data_in' => 'data_in_net',
8581 
              'data_in_x0' => 'data_in_x0_net',
8582 
              'data_in_x1' => 'data_in_x1_net',
8583 
              'data_in_x10' => 'data_in_x10_net',
8584 
              'data_in_x11' => 'data_in_x11_net',
8585 
              'data_in_x12' => 'data_in_x12_net',
8586 
              'data_in_x13' => 'data_in_x13_net',
8587 
              'data_in_x14' => 'data_in_x14_net',
8588 
              'data_in_x15' => 'data_in_x15_net',
8589 
              'data_in_x16' => 'data_in_x16_net',
8590 
              'data_in_x17' => 'data_in_x17_net',
8591 
              'data_in_x18' => 'data_in_x18_net',
8592 
              'data_in_x19' => 'data_in_x19_net',
8593 
              'data_in_x2' => 'data_in_x2_net',
8594 
              'data_in_x20' => 'data_in_x20_net',
8595 
              'data_in_x21' => 'data_in_x21_net',
8596 
              'data_in_x22' => 'data_in_x22_net',
8597 
              'data_in_x23' => 'data_in_x23_net',
8598 
              'data_in_x24' => 'data_in_x24_net',
8599 
              'data_in_x25' => 'data_in_x25_net',
8600 
              'data_in_x26' => 'data_in_x26_net',
8601 
              'data_in_x3' => 'data_in_x3_net',
8602 
              'data_in_x4' => 'data_in_x4_net',
8603 
              'data_in_x5' => 'data_in_x5_net',
8604 
              'data_in_x6' => 'data_in_x6_net',
8605 
              'data_in_x7' => 'data_in_x7_net',
8606 
              'data_in_x8' => 'data_in_x8_net',
8607 
              'data_in_x9' => 'data_in_x9_net',
8608 
              'data_out_x1' => 'data_out_x1_net',
8609 
              'data_out_x12' => 'data_out_x12_net',
8610 
              'data_out_x13' => 'data_out_x13_net',
8611 
              'data_out_x14' => 'data_out_x14_net',
8612 
              'data_out_x15' => 'data_out_x15_net',
8613 
              'data_out_x16' => 'data_out_x16_net',
8614 
              'data_out_x17' => 'data_out_x17_net',
8615 
              'data_out_x18' => 'data_out_x18_net',
8616 
              'data_out_x19' => 'data_out_x19_net',
8617 
              'data_out_x2' => 'data_out_x2_net',
8618 
              'data_out_x20' => 'data_out_x20_net',
8619 
              'data_out_x21' => 'data_out_x21_net',
8620 
              'data_out_x22' => 'data_out_x22_net',
8621 
              'data_out_x23' => 'data_out_x23_net',
8622 
              'data_out_x24' => 'data_out_x24_net',
8623 
              'data_out_x25' => 'data_out_x25_net',
8624 
              'data_out_x26' => 'data_out_x26_net',
8625 
              'data_out_x27' => 'data_out_x27_net',
8626 
              'data_out_x28' => 'data_out_x28_net',
8627 
              'data_out_x29' => 'data_out_x29_net',
8628 
              'data_out_x3' => 'data_out_x3_net',
8629 
              'data_out_x30' => 'data_out_x30_net',
8630 
              'data_out_x31' => 'data_out_x31_net',
8631 
              'data_out_x32' => 'data_out_x32_net',
8632 
              'data_out_x4' => 'data_out_x4_net',
8633 
              'data_out_x5' => 'data_out_x5_net',
8634 
              'data_out_x8' => 'data_out_x8_net',
8635 
              'data_out_x9' => 'data_out_x9_net',
8636 
              'en' => 'constant6_op_net_x0',
8637 
              'en_x0' => 'constant6_op_net_x1',
8638 
              'en_x1' => 'constant6_op_net_x2',
8639 
              'en_x10' => 'constant6_op_net_x11',
8640 
              'en_x11' => 'constant6_op_net_x12',
8641 
              'en_x12' => 'constant6_op_net_x13',
8642 
              'en_x13' => 'constant6_op_net_x14',
8643 
              'en_x14' => 'constant6_op_net_x15',
8644 
              'en_x15' => 'constant6_op_net_x16',
8645 
              'en_x16' => 'constant6_op_net_x17',
8646 
              'en_x17' => 'constant6_op_net_x18',
8647 
              'en_x18' => 'constant6_op_net_x19',
8648 
              'en_x19' => 'constant6_op_net_x20',
8649 
              'en_x2' => 'constant6_op_net_x3',
8650 
              'en_x20' => 'constant6_op_net_x21',
8651 
              'en_x21' => 'constant6_op_net_x22',
8652 
              'en_x22' => 'constant6_op_net_x23',
8653 
              'en_x23' => 'constant6_op_net_x24',
8654 
              'en_x24' => 'constant6_op_net_x25',
8655 
              'en_x25' => 'constant6_op_net_x26',
8656 
              'en_x26' => 'constant6_op_net_x27',
8657 
              'en_x3' => 'constant6_op_net_x4',
8658 
              'en_x4' => 'constant6_op_net_x5',
8659 
              'en_x5' => 'constant6_op_net_x6',
8660 
              'en_x6' => 'constant6_op_net_x7',
8661 
              'en_x7' => 'constant6_op_net_x8',
8662 
              'en_x8' => 'constant6_op_net_x9',
8663 
              'en_x9' => 'constant6_op_net_x10',
8664 
              'fifo_rd_count_x0' => 'fifo_rd_count_net',
8665 
              'fifo_rd_dout' => 'fifo_rd_dout_net',
8666 
              'fifo_rd_empty' => 'fifo_rd_empty_net',
8667 
              'fifo_rd_en_x1' => 'fifo_rd_en_net',
8668 
              'fifo_rd_pempty_x0' => 'fifo_rd_pempty_net',
8669 
              'fifo_rd_valid' => 'fifo_rd_valid_net',
8670 
              'fifo_wr_count_x0' => 'fifo_wr_count_net',
8671 
              'fifo_wr_din' => 'fifo_wr_din_net',
8672 
              'fifo_wr_en_x0' => 'fifo_wr_en_net',
8673 
              'fifo_wr_full_x0' => 'fifo_wr_full_net',
8674 
              'fifo_wr_pfull_x0' => 'fifo_wr_pfull_net',
8675 
              'rst_i' => 'rst_i_net',
8676 
              'rst_o' => 'rst_o_net',
8677 
              'user_int_1o' => 'user_int_1o_net',
8678 
              'user_int_2o' => 'user_int_2o_net',
8679 
              'user_int_3o' => 'user_int_3o_net',
8680 
            },
8681 
            'entity' => {
8682 
              'attributes' => {
8683 
                'entityAlreadyNetlisted' => 1,
8684 
                'hdlKind' => 'vhdl',
8685 
                'isDesign' => 1,
8686 
                'simulinkName' => 'USER_LOGIC',
8687 
              },
8688 
              'entityName' => 'user_logic',
8689 
              'ports' => {
8690 
                'bram_rd_addr' => {
8691 
                  'attributes' => {
8692 
                    'bin_pt' => 0,
8693 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
8694 
                    'is_floating_block' => 1,
8695 
                    'is_gateway_port' => 1,
8696 
                    'must_be_hdl_vector' => 1,
8697 
                    'period' => 1,
8698 
                    'port_id' => 15,
8699 
                    'simulinkName' => 'USER_LOGIC/BRAM_rd_addr',
8700 
                    'source_block' => 'USER_LOGIC',
8701 
                    'timingConstraint' => 'none',
8702 
                    'type' => 'UFix_12_0',
8703 
                  },
8704 
                  'direction' => 'out',
8705 
                  'hdlType' => 'std_logic_vector(11 downto 0)',
8706 
                  'width' => 12,
8707 
                },
8708 
                'bram_rd_dout' => {
8709 
                  'attributes' => {
8710 
                    'bin_pt' => 0,
8711 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
8712 
                    'is_floating_block' => 1,
8713 
                    'is_gateway_port' => 1,
8714 
                    'must_be_hdl_vector' => 1,
8715 
                    'period' => 1,
8716 
                    'port_id' => 0,
8717 
                    'simulinkName' => 'USER_LOGIC/BRAM_rd_dout',
8718 
                    'source_block' => 'USER_LOGIC',
8719 
                    'timingConstraint' => 'none',
8720 
                    'type' => 'UFix_64_0',
8721 
                  },
8722 
                  'direction' => 'in',
8723 
                  'hdlType' => 'std_logic_vector(63 downto 0)',
8724 
                  'width' => 64,
8725 
                },
8726 
                'bram_wr_addr' => {
8727 
                  'attributes' => {
8728 
                    'bin_pt' => 0,
8729 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
8730 
                    'is_floating_block' => 1,
8731 
                    'is_gateway_port' => 1,
8732 
                    'must_be_hdl_vector' => 1,
8733 
                    'period' => 1,
8734 
                    'port_id' => 16,
8735 
                    'simulinkName' => 'USER_LOGIC/BRAM_wr_addr',
8736 
                    'source_block' => 'USER_LOGIC',
8737 
                    'timingConstraint' => 'none',
8738 
                    'type' => 'UFix_12_0',
8739 
                  },
8740 
                  'direction' => 'out',
8741 
                  'hdlType' => 'std_logic_vector(11 downto 0)',
8742 
                  'width' => 12,
8743 
                },
8744 
                'bram_wr_din' => {
8745 
                  'attributes' => {
8746 
                    'bin_pt' => 0,
8747 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
8748 
                    'is_floating_block' => 1,
8749 
                    'is_gateway_port' => 1,
8750 
                    'must_be_hdl_vector' => 1,
8751 
                    'period' => 1,
8752 
                    'port_id' => 18,
8753 
                    'simulinkName' => 'USER_LOGIC/BRAM_wr_din',
8754 
                    'source_block' => 'USER_LOGIC',
8755 
                    'timingConstraint' => 'none',
8756 
                    'type' => 'UFix_64_0',
8757 
                  },
8758 
                  'direction' => 'out',
8759 
                  'hdlType' => 'std_logic_vector(63 downto 0)',
8760 
                  'width' => 64,
8761 
                },
8762 
                'bram_wr_en' => {
8763 
                  'attributes' => {
8764 
                    'bin_pt' => 0,
8765 
                    'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_en.dat',
8766 
                    'is_floating_block' => 1,
8767 
                    'is_gateway_port' => 1,
8768 
                    'must_be_hdl_vector' => 1,
8769 
                    'period' => 1,
8770 
                    'port_id' => 23,
8771 
                    'simulinkName' => 'USER_LOGIC/BRAM_wr_en',
8772 
                    'source_block' => 'USER_LOGIC',
8773 
                    'timingConstraint' => 'none',
8774 
                    'type' => 'UFix_8_0',
8775 
                  },
8776 
                  'direction' => 'out',
8777 
                  'hdlType' => 'std_logic_vector(7 downto 0)',
8778 
                  'width' => 8,
8779 
                },
8780 
                'ce_1' => {
8781 
                  'attributes' => {
8782 
                    'domain' => '',
8783 
                    'group' => 1,
8784 
                    'isCe' => 1,
8785 
                    'is_subsys_port' => 1,
8786 
                    'period' => 1,
8787 
                    'subsys_port_index' => 0,
8788 
                    'type' => 'logic',
8789 
                  },
8790 
                  'direction' => 'in',
8791 
                  'hdlType' => 'std_logic',
8792 
                  'width' => 1,
8793 
                },
8794 
                'clk_1' => {
8795 
                  'attributes' => {
8796 
                    'domain' => '',
8797 
                    'group' => 1,
8798 
                    'isClk' => 1,
8799 
                    'is_subsys_port' => 1,
8800 
                    'period' => 1,
8801 
                    'subsys_port_index' => 0,
8802 
                    'type' => 'logic',
8803 
                  },
8804 
                  'direction' => 'in',
8805 
                  'hdlType' => 'std_logic',
8806 
                  'width' => 1,
8807 
                },
8808 
                'data_in' => {
8809 
                  'attributes' => {
8810 
                    'bin_pt' => 0,
8811 
                    'is_floating_block' => 1,
8812 
                    'must_be_hdl_vector' => 1,
8813 
                    'period' => 1,
8814 
                    'port_id' => 17,
8815 
                    'simulinkName' => 'USER_LOGIC/tx_en_in2',
8816 
                    'type' => 'UFix_32_0',
8817 
                  },
8818 
                  'direction' => 'out',
8819 
                  'hdlType' => 'std_logic_vector(31 downto 0)',
8820 
                  'width' => 32,
8821 
                },
8822 
                'data_in_x0' => {
8823 
                  'attributes' => {
8824 
                    'bin_pt' => 0,
8825 
                    'is_floating_block' => 1,
8826 
                    'must_be_hdl_vector' => 1,
8827 
                    'period' => 1,
8828 
                    'port_id' => 1,
8829 
                    'simulinkName' => 'USER_LOGIC/tx_en_in1',
8830 
                    'type' => 'Bool',
8831 
                  },
8832 
                  'direction' => 'out',
8833 
                  'hdlType' => 'std_logic',
8834 
                  'width' => 1,
8835 
                },
8836 
                'data_in_x1' => {
8837 
                  'attributes' => {
8838 
                    'bin_pt' => 0,
8839 
                    'is_floating_block' => 1,
8840 
                    'must_be_hdl_vector' => 1,
8841 
                    'period' => 1,
8842 
                    'port_id' => 36,
8843 
                    'simulinkName' => 'USER_LOGIC/tx_en_in96',
8844 
                    'type' => 'Bool',
8845 
                  },
8846 
                  'direction' => 'out',
8847 
                  'hdlType' => 'std_logic',
8848 
                  'width' => 1,
8849 
                },
8850 
                'data_in_x10' => {
8851 
                  'attributes' => {
8852 
                    'bin_pt' => 0,
8853 
                    'is_floating_block' => 1,
8854 
                    'must_be_hdl_vector' => 1,
8855 
                    'period' => 1,
8856 
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14002 
            'hdlType' => 'std_logic',
14003 
            'width' => 1,
14004 
          },
14005 
        },
14006 
      },
14007 
      'entityName' => 'user_int_3o',
14008 
    },
14009 
  },
14010 
}

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