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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [v6_pcie_v1_7_x4/] [example_design/] [PIO_64_RX_ENGINE.v] - Blame information for rev 13

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//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project    : Virtex-6 Integrated Block for PCI Express
// File       : PIO_64_RX_ENGINE.v
// Version    : 1.7
//--
//-- Description: 64 bit Local-Link Receive Unit.
//--
//--------------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
`define TCQ 1
 
`define PIO_64_RX_MEM_RD32_FMT_TYPE 7'b00_00000
`define PIO_64_RX_MEM_WR32_FMT_TYPE 7'b10_00000
`define PIO_64_RX_MEM_RD64_FMT_TYPE 7'b01_00000
`define PIO_64_RX_MEM_WR64_FMT_TYPE 7'b11_00000
`define PIO_64_RX_IO_RD32_FMT_TYPE  7'b00_00010
`define PIO_64_RX_IO_WR32_FMT_TYPE  7'b10_00010
 
`define PIO_64_RX_RST_STATE         8'b00000000
`define PIO_64_RX_MEM_RD32_DW1DW2   8'b00000001
`define PIO_64_RX_MEM_WR32_DW1DW2   8'b00000100
`define PIO_64_RX_MEM_RD64_DW1DW2   8'b01000001
`define PIO_64_RX_MEM_RD64_DW3      8'b01000011
`define PIO_64_RX_MEM_WR64_DW1DW2   8'b01000100
`define PIO_64_RX_MEM_WR64_DW3      8'b01010000
`define PIO_64_RX_WAIT_STATE        8'b10000000
 
 
 
module PIO_64_RX_ENGINE (
                        clk,
                        rst_n,
 
                        /*
                         * Receive local link interface from PCIe core
                         */
 
                        trn_rd,
                        trn_rrem_n,
                        trn_rsof_n,
                        trn_reof_n,
                        trn_rsrc_rdy_n,
                        trn_rsrc_dsc_n,
                        trn_rbar_hit_n,
                        trn_rdst_rdy_n,
 
 
 
                        /*
                         * Memory Read data handshake with Completion
                         * transmit unit. Transmit unit reponds to
                         * req_compl assertion and responds with compl_done
                         * assertion when a Completion w/ data is transmitted.
                         */
 
                        req_compl_o,
                        compl_done_i,
 
                        req_tc_o,                  // Memory Read TC
                        req_td_o,                  // Memory Read TD
                        req_ep_o,                  // Memory Read EP
                        req_attr_o,                // Memory Read Attribute
                        req_len_o,                 // Memory Read Length (1DW)
                        req_rid_o,                 // Memory Read Requestor ID
                        req_tag_o,                 // Memory Read Tag
                        req_be_o,                  // Memory Read Byte Enables
                        req_addr_o,                // Memory Read Address
 
                         /*
                         * Memory interface used to save 1 DW data received
                         * on Memory Write 32 TLP. Data extracted from
                         * inbound TLP is presented to the Endpoint memory
                         * unit. Endpoint memory unit reacts to wr_en_o
                         * assertion and asserts wr_busy_i when it is
                         * processing written information.
                         */
 
                        wr_addr_o,                 // Memory Write Address
                        wr_be_o,                   // Memory Write Byte Enable
                        wr_data_o,                 // Memory Write Data
                        wr_en_o,                   // Memory Write Enable
                        wr_busy_i                  // Memory Write Busy
 
 
 
                       );
 
    input              clk;
    input              rst_n;
 
    input [63:0]       trn_rd;
    input [7:0]        trn_rrem_n;
    input              trn_rsof_n;
    input              trn_reof_n;
    input              trn_rsrc_rdy_n;
    input              trn_rsrc_dsc_n;
    input [6:0]        trn_rbar_hit_n;
    output             trn_rdst_rdy_n;
 
    output             req_compl_o;
    input              compl_done_i;
 
    output [2:0]       req_tc_o;
    output             req_td_o;
    output             req_ep_o;
    output [1:0]       req_attr_o;
    output [9:0]       req_len_o;
    output [15:0]      req_rid_o;
    output [7:0]       req_tag_o;
    output [7:0]       req_be_o;
    output [12:0]      req_addr_o;
 
 
    output [10:0]      wr_addr_o;
    output [7:0]       wr_be_o;
    output [31:0]      wr_data_o;
    output             wr_en_o;
    input              wr_busy_i;
 
 
    // Local Registers
 
    reg                trn_rdst_rdy_n;
 
    reg                req_compl_o;
 
    reg [2:0]          req_tc_o;
    reg                req_td_o;
    reg                req_ep_o;
    reg [1:0]          req_attr_o;
    reg [9:0]          req_len_o;
    reg [15:0]         req_rid_o;
    reg [7:0]          req_tag_o;
    reg [7:0]          req_be_o;
    reg [12:0]         req_addr_o;
 
    reg [10:0]         wr_addr_o;
    reg [7:0]          wr_be_o;
    reg [31:0]         wr_data_o;
    reg                wr_en_o;
 
    reg [7:0]          state;
    reg [7:0]          tlp_type;
 
    wire               io_bar_hit_n;
    wire               mem32_bar_hit_n;
    wire               mem64_bar_hit_n;
    wire               erom_bar_hit_n;
 
    reg [1:0]          region_select;
 
 
    always @ ( posedge clk ) begin
 
        if (!rst_n ) begin
 
          trn_rdst_rdy_n <= #`TCQ 1'b0;
 
          req_compl_o    <= #`TCQ 1'b0;
 
          req_tc_o       <= #`TCQ 2'b0;
          req_td_o       <= #`TCQ 1'b0;
          req_ep_o       <= #`TCQ 1'b0;
          req_attr_o     <= #`TCQ 2'b0;
          req_len_o      <= #`TCQ 10'b0;
          req_rid_o      <= #`TCQ 16'b0;
          req_tag_o      <= #`TCQ 8'b0;
          req_be_o       <= #`TCQ 8'b0;
          req_addr_o     <= #`TCQ 13'b0;
 
          wr_be_o        <= #`TCQ 8'b0;
          wr_addr_o      <= #`TCQ 11'b0;
          wr_data_o      <= #`TCQ 31'b0;
          wr_en_o        <= #`TCQ 1'b0;
 
          state          <= #`TCQ `PIO_64_RX_RST_STATE;
          tlp_type       <= #`TCQ 7'b0;
 
        end else begin
 
          wr_en_o        <= #`TCQ 1'b0;
          req_compl_o    <= #`TCQ 1'b0;
 
          case (state)
 
            `PIO_64_RX_RST_STATE : begin
 
              trn_rdst_rdy_n <= #`TCQ 1'b0;
 
              if ((!trn_rsof_n) &&
                  (!trn_rsrc_rdy_n) &&
                  (!trn_rdst_rdy_n)) begin
 
                case (trn_rd[62:56])
 
                  `PIO_64_RX_MEM_RD32_FMT_TYPE : begin
 
                    tlp_type     <= #`TCQ trn_rd[63:56];
                    req_len_o    <= #`TCQ trn_rd[41:32];
                    trn_rdst_rdy_n <= #`TCQ 1'b1;
 
 
                    if (trn_rd[41:32] == 10'b1) begin
 
                      req_tc_o     <= #`TCQ trn_rd[54:52];
                      req_td_o     <= #`TCQ trn_rd[47];
                      req_ep_o     <= #`TCQ trn_rd[46];
                      req_attr_o   <= #`TCQ trn_rd[45:44];
                      req_len_o    <= #`TCQ trn_rd[41:32];
                      req_rid_o    <= #`TCQ trn_rd[31:16];
                      req_tag_o    <= #`TCQ trn_rd[15:08];
                      req_be_o     <= #`TCQ trn_rd[07:00];
                      state        <= #`TCQ `PIO_64_RX_MEM_RD32_DW1DW2;
 
                    end else begin
 
                      state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
                    end
 
                  end
 
                  `PIO_64_RX_MEM_WR32_FMT_TYPE : begin
 
                    tlp_type     <= #`TCQ trn_rd[63:56];
                    req_len_o    <= #`TCQ trn_rd[41:32];
                    trn_rdst_rdy_n <= #`TCQ 1'b1;
 
                    if (trn_rd[41:32] == 10'b1) begin
 
                      wr_be_o      <= #`TCQ trn_rd[07:00];
                      state        <= #`TCQ `PIO_64_RX_MEM_WR32_DW1DW2;
 
                    end else begin
 
                      state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
                    end
 
                  end
 
                  `PIO_64_RX_MEM_RD64_FMT_TYPE : begin
 
                    tlp_type     <= #`TCQ trn_rd[63:56];
                    req_len_o    <= #`TCQ trn_rd[41:32];
                    trn_rdst_rdy_n <= #`TCQ 1'b1;
 
 
                    if (trn_rd[41:32] == 10'b1) begin
 
                      req_tc_o     <= #`TCQ trn_rd[54:52];
                      req_td_o     <= #`TCQ trn_rd[47];
                      req_ep_o     <= #`TCQ trn_rd[46];
                      req_attr_o   <= #`TCQ trn_rd[45:44];
                      req_len_o    <= #`TCQ trn_rd[41:32];
                      req_rid_o    <= #`TCQ trn_rd[31:16];
                      req_tag_o    <= #`TCQ trn_rd[15:08];
                      req_be_o     <= #`TCQ trn_rd[07:00];
                      state        <= #`TCQ `PIO_64_RX_MEM_RD64_DW1DW2;
 
                    end else begin
 
                      state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
                    end
 
                  end
 
                  `PIO_64_RX_MEM_WR64_FMT_TYPE : begin
 
                    tlp_type     <= #`TCQ trn_rd[63:56];
                    req_len_o    <= #`TCQ trn_rd[41:32];
 
                    if (trn_rd[41:32] == 10'b1) begin
 
                      wr_be_o      <= #`TCQ trn_rd[07:00];
                      state        <= #`TCQ `PIO_64_RX_MEM_WR64_DW1DW2;
 
                    end else begin
 
                      state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
                    end
 
                  end
 
 
                  `PIO_64_RX_IO_RD32_FMT_TYPE : begin
 
                    tlp_type     <= #`TCQ trn_rd[63:56];
                    req_len_o    <= #`TCQ trn_rd[41:32];
                    trn_rdst_rdy_n <= #`TCQ 1'b1;
 
 
                    if (trn_rd[41:32] == 10'b1) begin
 
                      req_tc_o     <= #`TCQ trn_rd[54:52];
                      req_td_o     <= #`TCQ trn_rd[47];
                      req_ep_o     <= #`TCQ trn_rd[46];
                      req_attr_o   <= #`TCQ trn_rd[45:44];
                      req_len_o    <= #`TCQ trn_rd[41:32];
                      req_rid_o    <= #`TCQ trn_rd[31:16];
                      req_tag_o    <= #`TCQ trn_rd[15:08];
                      req_be_o     <= #`TCQ trn_rd[07:00];
                      state        <= #`TCQ `PIO_64_RX_MEM_RD32_DW1DW2;
 
                    end else begin
 
                      state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
                    end
 
                  end
 
                  `PIO_64_RX_IO_WR32_FMT_TYPE : begin
 
                    tlp_type     <= #`TCQ trn_rd[63:56];
                    req_len_o    <= #`TCQ trn_rd[41:32];
                    trn_rdst_rdy_n <= #`TCQ 1'b1;
 
                    if (trn_rd[41:32] == 10'b1) begin
 
                      wr_be_o      <= #`TCQ trn_rd[07:00];
                      state        <= #`TCQ `PIO_64_RX_MEM_WR32_DW1DW2;
 
                    end else begin
 
                      state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
                    end
 
                  end
 
 
                  default : begin // other TLPs
 
                    state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
                  end
 
                endcase
 
              end else
                state <= #`TCQ `PIO_64_RX_RST_STATE;
 
            end
 
            `PIO_64_RX_MEM_RD32_DW1DW2 : begin
 
              if (!trn_rsrc_rdy_n) begin
 
                trn_rdst_rdy_n <= #`TCQ 1'b1;
                req_addr_o   <= #`TCQ {region_select[1:0],trn_rd[42:34], 2'b00};
                req_compl_o  <= #`TCQ 1'b1;
                state        <= #`TCQ `PIO_64_RX_WAIT_STATE;
 
              end else
                state        <= #`TCQ `PIO_64_RX_MEM_RD32_DW1DW2;
 
            end
 
 
            `PIO_64_RX_MEM_WR32_DW1DW2 : begin
 
              if (!trn_rsrc_rdy_n) begin
 
                wr_data_o      <= #`TCQ trn_rd[31:0];
                wr_en_o        <= #`TCQ 1'b1;
                trn_rdst_rdy_n <= #`TCQ 1'b1;
                wr_addr_o      <= #`TCQ {region_select[1:0],trn_rd[42:34]};
                state          <= #`TCQ  `PIO_64_RX_WAIT_STATE;
 
              end else
                state          <= #`TCQ `PIO_64_RX_MEM_WR32_DW1DW2;
 
            end
 
 
            `PIO_64_RX_MEM_RD64_DW1DW2 : begin
 
              if (!trn_rsrc_rdy_n) begin
 
                req_addr_o   <= #`TCQ {region_select[1:0],trn_rd[10:2], 2'b00};
                req_compl_o  <= #`TCQ 1'b1;
                trn_rdst_rdy_n <= #`TCQ 1'b1;
                state        <= #`TCQ `PIO_64_RX_WAIT_STATE;
 
              end else
                state        <= #`TCQ `PIO_64_RX_MEM_RD64_DW1DW2;
 
            end
 
 
 
            `PIO_64_RX_MEM_WR64_DW1DW2 : begin
 
              if (!trn_rsrc_rdy_n) begin
 
                trn_rdst_rdy_n <= #`TCQ 1'b1;
                wr_addr_o      <= #`TCQ {region_select[1:0],trn_rd[10:2]};
                state          <= #`TCQ  `PIO_64_RX_MEM_WR64_DW3;
 
              end else
                state          <= #`TCQ `PIO_64_RX_MEM_WR64_DW1DW2;
 
            end
 
 
            `PIO_64_RX_MEM_WR64_DW3 : begin
 
              if (!trn_rsrc_rdy_n) begin
 
                wr_data_o      <= #`TCQ trn_rd[63:32];
                wr_en_o        <= #`TCQ 1'b1;
                trn_rdst_rdy_n <= #`TCQ 1'b1;
                state        <= #`TCQ `PIO_64_RX_WAIT_STATE;
 
              end else
                 state        <= #`TCQ `PIO_64_RX_MEM_WR64_DW3;
 
            end
 
 
 
            `PIO_64_RX_WAIT_STATE : begin
 
              wr_en_o      <= #`TCQ 1'b0;
              req_compl_o  <= #`TCQ 1'b0;
 
              if ((tlp_type == `PIO_64_RX_MEM_WR32_FMT_TYPE) &&
                  (!wr_busy_i)) begin
 
                trn_rdst_rdy_n <= #`TCQ 1'b0;
                state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
             end else if ((tlp_type == `PIO_64_RX_IO_WR32_FMT_TYPE) &&
                  (!wr_busy_i)) begin
 
                trn_rdst_rdy_n <= #`TCQ 1'b0;
                state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
              end else if ((tlp_type == `PIO_64_RX_MEM_WR64_FMT_TYPE) &&
                  (!wr_busy_i)) begin
 
                trn_rdst_rdy_n <= #`TCQ 1'b0;
                state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
              end else if ((tlp_type == `PIO_64_RX_MEM_RD32_FMT_TYPE) &&
                           (compl_done_i)) begin
 
                trn_rdst_rdy_n <= #`TCQ 1'b0;
                state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
              end else if ((tlp_type == `PIO_64_RX_IO_RD32_FMT_TYPE) &&
                           (compl_done_i)) begin
 
                trn_rdst_rdy_n <= #`TCQ 1'b0;
                state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
              end else if ((tlp_type == `PIO_64_RX_MEM_RD64_FMT_TYPE) &&
                           (compl_done_i)) begin
 
                trn_rdst_rdy_n <= #`TCQ 1'b0;
                state        <= #`TCQ `PIO_64_RX_RST_STATE;
 
              end else
                state        <= #`TCQ `PIO_64_RX_WAIT_STATE;
 
            end
 
          endcase
 
        end
 
    end
 
 
     assign mem64_bar_hit_n = 1'b1;
    assign io_bar_hit_n = 1'b1;
    assign mem32_bar_hit_n = trn_rbar_hit_n[0];
    assign erom_bar_hit_n  = trn_rbar_hit_n[6];
 
 
  always @*
  begin
     case ({io_bar_hit_n, mem32_bar_hit_n, mem64_bar_hit_n, erom_bar_hit_n})
 
        4'b0111 : begin
             region_select <= #`TCQ 2'b00;    // Select IO region
        end
 
        4'b1011 : begin
             region_select <= #`TCQ 2'b01;    // Select Mem32 region
        end
 
        4'b1101 : begin
             region_select <= #`TCQ 2'b10;    // Select Mem64 region
        end
 
        4'b1110 : begin
             region_select <= #`TCQ 2'b11;    // Select EROM region
        end
 
        default : begin
             region_select <= #`TCQ 2'b00;    // Error selection will select IO region
        end
 
     endcase
 
  end
 
 
  // synthesis translate_off
  reg  [8*20:1] state_ascii;
  always @(state)
  begin
    if      (state==`PIO_64_RX_RST_STATE)         state_ascii <= #`TCQ "RX_RST_STATE";
    else if (state==`PIO_64_RX_MEM_RD32_DW1DW2)   state_ascii <= #`TCQ "RX_MEM_RD32_DW1DW2";
    else if (state==`PIO_64_RX_MEM_WR32_DW1DW2)   state_ascii <= #`TCQ "RX_MEM_WR32_DW1DW2";
    else if (state==`PIO_64_RX_MEM_RD64_DW1DW2)   state_ascii <= #`TCQ "RX_MEM_RD64_DW1DW2";
    else if (state==`PIO_64_RX_MEM_RD64_DW3)      state_ascii <= #`TCQ "RX_MEM_RD64_DW3";
    else if (state==`PIO_64_RX_MEM_WR64_DW1DW2)   state_ascii <= #`TCQ "RX_MEM_WR64_DW1DW2";
    else if (state==`PIO_64_RX_MEM_WR64_DW3)      state_ascii <= #`TCQ "RX_MEM_WR64_DW3";
    else if (state==`PIO_64_RX_WAIT_STATE)        state_ascii <= #`TCQ "RX_WAIT_STATE";
    else                                          state_ascii <= #`TCQ "PIO 64 STATE ERR";
 
  end
  // synthesis translate_on
 
 
 
 
 
 
endmodule // PIO_64_RX_ENGINE
 

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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [ipcore_dir_ISE13.3/] [v6_pcie_v1_7_x4/] [example_design/] [PIO_64_RX_ENGINE.v] - Blame information for rev 13

Line No.	Rev	Author	Line
1	13	barabba	`//-----------------------------------------------------------------------------`
2			`//`
3			`// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.`
4			`//`
5			`// This file contains confidential and proprietary information`
6			`// of Xilinx, Inc. and is protected under U.S. and`
7			`// international copyright and other intellectual property`
8			`// laws.`
9			`//`
10			`// DISCLAIMER`
11			`// This disclaimer is not a license and does not grant any`
12			`// rights to the materials distributed herewith. Except as`
13			`// otherwise provided in a valid license issued to you by`
14			`// Xilinx, and to the maximum extent permitted by applicable`
15			`// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND`
16			`// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES`
17			`// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING`
18			`// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-`
19			`// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and`
20			`// (2) Xilinx shall not be liable (whether in contract or tort,`
21			`// including negligence, or under any other theory of`
22			`// liability) for any loss or damage of any kind or nature`
23			`// related to, arising under or in connection with these`
24			`// materials, including for any direct, or any indirect,`
25			`// special, incidental, or consequential loss or damage`
26			`// (including loss of data, profits, goodwill, or any type of`
27			`// loss or damage suffered as a result of any action brought`
28			`// by a third party) even if such damage or loss was`
29			`// reasonably foreseeable or Xilinx had been advised of the`
30			`// possibility of the same.`
31			`//`
32			`// CRITICAL APPLICATIONS`
33			`// Xilinx products are not designed or intended to be fail-`
34			`// safe, or for use in any application requiring fail-safe`
35			`// performance, such as life-support or safety devices or`
36			`// systems, Class III medical devices, nuclear facilities,`
37			`// applications related to the deployment of airbags, or any`
38			`// other applications that could lead to death, personal`
39			`// injury, or severe property or environmental damage`
40			`// (individually and collectively, "Critical`
41			`// Applications"). Customer assumes the sole risk and`
42			`// liability of any use of Xilinx products in Critical`
43			`// Applications, subject only to applicable laws and`
44			`// regulations governing limitations on product liability.`
45			`//`
46			`// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS`
47			`// PART OF THIS FILE AT ALL TIMES.`
48			`//`
49			`//-----------------------------------------------------------------------------`
50			`// Project : Virtex-6 Integrated Block for PCI Express`
51			`// File : PIO_64_RX_ENGINE.v`
52			`// Version : 1.7`
53			`//--`
54			`//-- Description: 64 bit Local-Link Receive Unit.`
55			`//--`
56			`//--------------------------------------------------------------------------------`
57
58			`timescale 1ns/1ns
59
60			`define TCQ 1
61
62			`define PIO_64_RX_MEM_RD32_FMT_TYPE 7'b00_00000
63			`define PIO_64_RX_MEM_WR32_FMT_TYPE 7'b10_00000
64			`define PIO_64_RX_MEM_RD64_FMT_TYPE 7'b01_00000
65			`define PIO_64_RX_MEM_WR64_FMT_TYPE 7'b11_00000
66			`define PIO_64_RX_IO_RD32_FMT_TYPE 7'b00_00010
67			`define PIO_64_RX_IO_WR32_FMT_TYPE 7'b10_00010
68
69			`define PIO_64_RX_RST_STATE 8'b00000000
70			`define PIO_64_RX_MEM_RD32_DW1DW2 8'b00000001
71			`define PIO_64_RX_MEM_WR32_DW1DW2 8'b00000100
72			`define PIO_64_RX_MEM_RD64_DW1DW2 8'b01000001
73			`define PIO_64_RX_MEM_RD64_DW3 8'b01000011
74			`define PIO_64_RX_MEM_WR64_DW1DW2 8'b01000100
75			`define PIO_64_RX_MEM_WR64_DW3 8'b01010000
76			`define PIO_64_RX_WAIT_STATE 8'b10000000
77
78
79
80			`module PIO_64_RX_ENGINE (`
81			`clk,`
82			`rst_n,`
83
84			`/*`
85			`* Receive local link interface from PCIe core`
86			`*/`
87
88			`trn_rd,`
89			`trn_rrem_n,`
90			`trn_rsof_n,`
91			`trn_reof_n,`
92			`trn_rsrc_rdy_n,`
93			`trn_rsrc_dsc_n,`
94			`trn_rbar_hit_n,`
95			`trn_rdst_rdy_n,`
96
97
98
99			`/*`
100			`* Memory Read data handshake with Completion`
101			`* transmit unit. Transmit unit reponds to`
102			`* req_compl assertion and responds with compl_done`
103			`* assertion when a Completion w/ data is transmitted.`
104			`*/`
105
106			`req_compl_o,`
107			`compl_done_i,`
108
109			`req_tc_o, // Memory Read TC`
110			`req_td_o, // Memory Read TD`
111			`req_ep_o, // Memory Read EP`
112			`req_attr_o, // Memory Read Attribute`
113			`req_len_o, // Memory Read Length (1DW)`
114			`req_rid_o, // Memory Read Requestor ID`
115			`req_tag_o, // Memory Read Tag`
116			`req_be_o, // Memory Read Byte Enables`
117			`req_addr_o, // Memory Read Address`
118
119			`/*`
120			`* Memory interface used to save 1 DW data received`
121			`* on Memory Write 32 TLP. Data extracted from`
122			`* inbound TLP is presented to the Endpoint memory`
123			`* unit. Endpoint memory unit reacts to wr_en_o`
124			`* assertion and asserts wr_busy_i when it is`
125			`* processing written information.`
126			`*/`
127
128			`wr_addr_o, // Memory Write Address`
129			`wr_be_o, // Memory Write Byte Enable`
130			`wr_data_o, // Memory Write Data`
131			`wr_en_o, // Memory Write Enable`
132			`wr_busy_i // Memory Write Busy`
133
134
135
136			`);`
137
138			`input clk;`
139			`input rst_n;`
140
141			`input [63:0] trn_rd;`
142			`input [7:0] trn_rrem_n;`
143			`input trn_rsof_n;`
144			`input trn_reof_n;`
145			`input trn_rsrc_rdy_n;`
146			`input trn_rsrc_dsc_n;`
147			`input [6:0] trn_rbar_hit_n;`
148			`output trn_rdst_rdy_n;`
149
150			`output req_compl_o;`
151			`input compl_done_i;`
152
153			`output [2:0] req_tc_o;`
154			`output req_td_o;`
155			`output req_ep_o;`
156			`output [1:0] req_attr_o;`
157			`output [9:0] req_len_o;`
158			`output [15:0] req_rid_o;`
159			`output [7:0] req_tag_o;`
160			`output [7:0] req_be_o;`
161			`output [12:0] req_addr_o;`
162
163
164			`output [10:0] wr_addr_o;`
165			`output [7:0] wr_be_o;`
166			`output [31:0] wr_data_o;`
167			`output wr_en_o;`
168			`input wr_busy_i;`
169
170
171			`// Local Registers`
172
173			`reg trn_rdst_rdy_n;`
174
175			`reg req_compl_o;`
176
177			`reg [2:0] req_tc_o;`
178			`reg req_td_o;`
179			`reg req_ep_o;`
180			`reg [1:0] req_attr_o;`
181			`reg [9:0] req_len_o;`
182			`reg [15:0] req_rid_o;`
183			`reg [7:0] req_tag_o;`
184			`reg [7:0] req_be_o;`
185			`reg [12:0] req_addr_o;`
186
187			`reg [10:0] wr_addr_o;`
188			`reg [7:0] wr_be_o;`
189			`reg [31:0] wr_data_o;`
190			`reg wr_en_o;`
191
192			`reg [7:0] state;`
193			`reg [7:0] tlp_type;`
194
195			`wire io_bar_hit_n;`
196			`wire mem32_bar_hit_n;`
197			`wire mem64_bar_hit_n;`
198			`wire erom_bar_hit_n;`
199
200			`reg [1:0] region_select;`
201
202
203			`always @ ( posedge clk ) begin`
204
205			`if (!rst_n ) begin`
206
207			trn_rdst_rdy_n <= #`TCQ 1'b0;
208
209			req_compl_o <= #`TCQ 1'b0;
210
211			req_tc_o <= #`TCQ 2'b0;
212			req_td_o <= #`TCQ 1'b0;
213			req_ep_o <= #`TCQ 1'b0;
214			req_attr_o <= #`TCQ 2'b0;
215			req_len_o <= #`TCQ 10'b0;
216			req_rid_o <= #`TCQ 16'b0;
217			req_tag_o <= #`TCQ 8'b0;
218			req_be_o <= #`TCQ 8'b0;
219			req_addr_o <= #`TCQ 13'b0;
220
221			wr_be_o <= #`TCQ 8'b0;
222			wr_addr_o <= #`TCQ 11'b0;
223			wr_data_o <= #`TCQ 31'b0;
224			wr_en_o <= #`TCQ 1'b0;
225
226			state <= #`TCQ `PIO_64_RX_RST_STATE;
227			tlp_type <= #`TCQ 7'b0;
228
229			`end else begin`
230
231			wr_en_o <= #`TCQ 1'b0;
232			req_compl_o <= #`TCQ 1'b0;
233
234			`case (state)`
235
236			`PIO_64_RX_RST_STATE : begin
237
238			trn_rdst_rdy_n <= #`TCQ 1'b0;
239
240			`if ((!trn_rsof_n) &&`
241			`(!trn_rsrc_rdy_n) &&`
242			`(!trn_rdst_rdy_n)) begin`
243
244			`case (trn_rd[62:56])`
245
246			`PIO_64_RX_MEM_RD32_FMT_TYPE : begin
247
248			tlp_type <= #`TCQ trn_rd[63:56];
249			req_len_o <= #`TCQ trn_rd[41:32];
250			trn_rdst_rdy_n <= #`TCQ 1'b1;
251
252
253			`if (trn_rd[41:32] == 10'b1) begin`
254
255			req_tc_o <= #`TCQ trn_rd[54:52];
256			req_td_o <= #`TCQ trn_rd[47];
257			req_ep_o <= #`TCQ trn_rd[46];
258			req_attr_o <= #`TCQ trn_rd[45:44];
259			req_len_o <= #`TCQ trn_rd[41:32];
260			req_rid_o <= #`TCQ trn_rd[31:16];
261			req_tag_o <= #`TCQ trn_rd[15:08];
262			req_be_o <= #`TCQ trn_rd[07:00];
263			state <= #`TCQ `PIO_64_RX_MEM_RD32_DW1DW2;
264
265			`end else begin`
266
267			state <= #`TCQ `PIO_64_RX_RST_STATE;
268
269			`end`
270
271			`end`
272
273			`PIO_64_RX_MEM_WR32_FMT_TYPE : begin
274
275			tlp_type <= #`TCQ trn_rd[63:56];
276			req_len_o <= #`TCQ trn_rd[41:32];
277			trn_rdst_rdy_n <= #`TCQ 1'b1;
278
279			`if (trn_rd[41:32] == 10'b1) begin`
280
281			wr_be_o <= #`TCQ trn_rd[07:00];
282			state <= #`TCQ `PIO_64_RX_MEM_WR32_DW1DW2;
283
284			`end else begin`
285
286			state <= #`TCQ `PIO_64_RX_RST_STATE;
287
288			`end`
289
290			`end`
291
292			`PIO_64_RX_MEM_RD64_FMT_TYPE : begin
293
294			tlp_type <= #`TCQ trn_rd[63:56];
295			req_len_o <= #`TCQ trn_rd[41:32];
296			trn_rdst_rdy_n <= #`TCQ 1'b1;
297
298
299			`if (trn_rd[41:32] == 10'b1) begin`
300
301			req_tc_o <= #`TCQ trn_rd[54:52];
302			req_td_o <= #`TCQ trn_rd[47];
303			req_ep_o <= #`TCQ trn_rd[46];
304			req_attr_o <= #`TCQ trn_rd[45:44];
305			req_len_o <= #`TCQ trn_rd[41:32];
306			req_rid_o <= #`TCQ trn_rd[31:16];
307			req_tag_o <= #`TCQ trn_rd[15:08];
308			req_be_o <= #`TCQ trn_rd[07:00];
309			state <= #`TCQ `PIO_64_RX_MEM_RD64_DW1DW2;
310
311			`end else begin`
312
313			state <= #`TCQ `PIO_64_RX_RST_STATE;
314
315			`end`
316
317			`end`
318
319			`PIO_64_RX_MEM_WR64_FMT_TYPE : begin
320
321			tlp_type <= #`TCQ trn_rd[63:56];
322			req_len_o <= #`TCQ trn_rd[41:32];
323
324			`if (trn_rd[41:32] == 10'b1) begin`
325
326			wr_be_o <= #`TCQ trn_rd[07:00];
327			state <= #`TCQ `PIO_64_RX_MEM_WR64_DW1DW2;
328
329			`end else begin`
330
331			state <= #`TCQ `PIO_64_RX_RST_STATE;
332
333			`end`
334
335			`end`
336
337
338			`PIO_64_RX_IO_RD32_FMT_TYPE : begin
339
340			tlp_type <= #`TCQ trn_rd[63:56];
341			req_len_o <= #`TCQ trn_rd[41:32];
342			trn_rdst_rdy_n <= #`TCQ 1'b1;
343
344
345			`if (trn_rd[41:32] == 10'b1) begin`
346
347			req_tc_o <= #`TCQ trn_rd[54:52];
348			req_td_o <= #`TCQ trn_rd[47];
349			req_ep_o <= #`TCQ trn_rd[46];
350			req_attr_o <= #`TCQ trn_rd[45:44];
351			req_len_o <= #`TCQ trn_rd[41:32];
352			req_rid_o <= #`TCQ trn_rd[31:16];
353			req_tag_o <= #`TCQ trn_rd[15:08];
354			req_be_o <= #`TCQ trn_rd[07:00];
355			state <= #`TCQ `PIO_64_RX_MEM_RD32_DW1DW2;
356
357			`end else begin`
358
359			state <= #`TCQ `PIO_64_RX_RST_STATE;
360
361			`end`
362
363			`end`
364
365			`PIO_64_RX_IO_WR32_FMT_TYPE : begin
366
367			tlp_type <= #`TCQ trn_rd[63:56];
368			req_len_o <= #`TCQ trn_rd[41:32];
369			trn_rdst_rdy_n <= #`TCQ 1'b1;
370
371			`if (trn_rd[41:32] == 10'b1) begin`
372
373			wr_be_o <= #`TCQ trn_rd[07:00];
374			state <= #`TCQ `PIO_64_RX_MEM_WR32_DW1DW2;
375
376			`end else begin`
377
378			state <= #`TCQ `PIO_64_RX_RST_STATE;
379
380			`end`
381
382			`end`
383
384
385			`default : begin // other TLPs`
386
387			state <= #`TCQ `PIO_64_RX_RST_STATE;
388
389			`end`
390
391			`endcase`
392
393			`end else`
394			state <= #`TCQ `PIO_64_RX_RST_STATE;
395
396			`end`
397
398			`PIO_64_RX_MEM_RD32_DW1DW2 : begin
399
400			`if (!trn_rsrc_rdy_n) begin`
401
402			trn_rdst_rdy_n <= #`TCQ 1'b1;
403			req_addr_o <= #`TCQ {region_select[1:0],trn_rd[42:34], 2'b00};
404			req_compl_o <= #`TCQ 1'b1;
405			state <= #`TCQ `PIO_64_RX_WAIT_STATE;
406
407			`end else`
408			state <= #`TCQ `PIO_64_RX_MEM_RD32_DW1DW2;
409
410			`end`
411
412
413			`PIO_64_RX_MEM_WR32_DW1DW2 : begin
414
415			`if (!trn_rsrc_rdy_n) begin`
416
417			wr_data_o <= #`TCQ trn_rd[31:0];
418			wr_en_o <= #`TCQ 1'b1;
419			trn_rdst_rdy_n <= #`TCQ 1'b1;
420			wr_addr_o <= #`TCQ {region_select[1:0],trn_rd[42:34]};
421			state <= #`TCQ `PIO_64_RX_WAIT_STATE;
422
423			`end else`
424			state <= #`TCQ `PIO_64_RX_MEM_WR32_DW1DW2;
425
426			`end`
427
428
429			`PIO_64_RX_MEM_RD64_DW1DW2 : begin
430
431			`if (!trn_rsrc_rdy_n) begin`
432
433			req_addr_o <= #`TCQ {region_select[1:0],trn_rd[10:2], 2'b00};
434			req_compl_o <= #`TCQ 1'b1;
435			trn_rdst_rdy_n <= #`TCQ 1'b1;
436			state <= #`TCQ `PIO_64_RX_WAIT_STATE;
437
438			`end else`
439			state <= #`TCQ `PIO_64_RX_MEM_RD64_DW1DW2;
440
441			`end`
442
443
444
445			`PIO_64_RX_MEM_WR64_DW1DW2 : begin
446
447			`if (!trn_rsrc_rdy_n) begin`
448
449			trn_rdst_rdy_n <= #`TCQ 1'b1;
450			wr_addr_o <= #`TCQ {region_select[1:0],trn_rd[10:2]};
451			state <= #`TCQ `PIO_64_RX_MEM_WR64_DW3;
452
453			`end else`
454			state <= #`TCQ `PIO_64_RX_MEM_WR64_DW1DW2;
455
456			`end`
457
458
459			`PIO_64_RX_MEM_WR64_DW3 : begin
460
461			`if (!trn_rsrc_rdy_n) begin`
462
463			wr_data_o <= #`TCQ trn_rd[63:32];
464			wr_en_o <= #`TCQ 1'b1;
465			trn_rdst_rdy_n <= #`TCQ 1'b1;
466			state <= #`TCQ `PIO_64_RX_WAIT_STATE;
467
468			`end else`
469			state <= #`TCQ `PIO_64_RX_MEM_WR64_DW3;
470
471			`end`
472
473
474
475			`PIO_64_RX_WAIT_STATE : begin
476
477			wr_en_o <= #`TCQ 1'b0;
478			req_compl_o <= #`TCQ 1'b0;
479
480			if ((tlp_type == `PIO_64_RX_MEM_WR32_FMT_TYPE) &&
481			`(!wr_busy_i)) begin`
482
483			trn_rdst_rdy_n <= #`TCQ 1'b0;
484			state <= #`TCQ `PIO_64_RX_RST_STATE;
485
486			end else if ((tlp_type == `PIO_64_RX_IO_WR32_FMT_TYPE) &&
487			`(!wr_busy_i)) begin`
488
489			trn_rdst_rdy_n <= #`TCQ 1'b0;
490			state <= #`TCQ `PIO_64_RX_RST_STATE;
491
492			end else if ((tlp_type == `PIO_64_RX_MEM_WR64_FMT_TYPE) &&
493			`(!wr_busy_i)) begin`
494
495			trn_rdst_rdy_n <= #`TCQ 1'b0;
496			state <= #`TCQ `PIO_64_RX_RST_STATE;
497
498			end else if ((tlp_type == `PIO_64_RX_MEM_RD32_FMT_TYPE) &&
499			`(compl_done_i)) begin`
500
501			trn_rdst_rdy_n <= #`TCQ 1'b0;
502			state <= #`TCQ `PIO_64_RX_RST_STATE;
503
504			end else if ((tlp_type == `PIO_64_RX_IO_RD32_FMT_TYPE) &&
505			`(compl_done_i)) begin`
506
507			trn_rdst_rdy_n <= #`TCQ 1'b0;
508			state <= #`TCQ `PIO_64_RX_RST_STATE;
509
510			end else if ((tlp_type == `PIO_64_RX_MEM_RD64_FMT_TYPE) &&
511			`(compl_done_i)) begin`
512
513			trn_rdst_rdy_n <= #`TCQ 1'b0;
514			state <= #`TCQ `PIO_64_RX_RST_STATE;
515
516			`end else`
517			state <= #`TCQ `PIO_64_RX_WAIT_STATE;
518
519			`end`
520
521			`endcase`
522
523			`end`
524
525			`end`
526
527
528			`assign mem64_bar_hit_n = 1'b1;`
529			`assign io_bar_hit_n = 1'b1;`
530			`assign mem32_bar_hit_n = trn_rbar_hit_n[0];`
531			`assign erom_bar_hit_n = trn_rbar_hit_n[6];`
532
533
534			`always @*`
535			`begin`
536			`case ({io_bar_hit_n, mem32_bar_hit_n, mem64_bar_hit_n, erom_bar_hit_n})`
537
538			`4'b0111 : begin`
539			region_select <= #`TCQ 2'b00; // Select IO region
540			`end`
541
542			`4'b1011 : begin`
543			region_select <= #`TCQ 2'b01; // Select Mem32 region
544			`end`
545
546			`4'b1101 : begin`
547			region_select <= #`TCQ 2'b10; // Select Mem64 region
548			`end`
549
550			`4'b1110 : begin`
551			region_select <= #`TCQ 2'b11; // Select EROM region
552			`end`
553
554			`default : begin`
555			region_select <= #`TCQ 2'b00; // Error selection will select IO region
556			`end`
557
558			`endcase`
559
560			`end`
561
562
563			`// synthesis translate_off`
564			`reg [8*20:1] state_ascii;`
565			`always @(state)`
566			`begin`
567			if (state==`PIO_64_RX_RST_STATE) state_ascii <= #`TCQ "RX_RST_STATE";
568			else if (state==`PIO_64_RX_MEM_RD32_DW1DW2) state_ascii <= #`TCQ "RX_MEM_RD32_DW1DW2";
569			else if (state==`PIO_64_RX_MEM_WR32_DW1DW2) state_ascii <= #`TCQ "RX_MEM_WR32_DW1DW2";
570			else if (state==`PIO_64_RX_MEM_RD64_DW1DW2) state_ascii <= #`TCQ "RX_MEM_RD64_DW1DW2";
571			else if (state==`PIO_64_RX_MEM_RD64_DW3) state_ascii <= #`TCQ "RX_MEM_RD64_DW3";
572			else if (state==`PIO_64_RX_MEM_WR64_DW1DW2) state_ascii <= #`TCQ "RX_MEM_WR64_DW1DW2";
573			else if (state==`PIO_64_RX_MEM_WR64_DW3) state_ascii <= #`TCQ "RX_MEM_WR64_DW3";
574			else if (state==`PIO_64_RX_WAIT_STATE) state_ascii <= #`TCQ "RX_WAIT_STATE";
575			else state_ascii <= #`TCQ "PIO 64 STATE ERR";
576
577			`end`
578			`// synthesis translate_on`
579
580
581
582
583
584
585			`endmodule // PIO_64_RX_ENGINE`
586