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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  FFT/IFFT 128 points transform                              ////
////                                                             ////
////  Authors: Anatoliy Sergienko, Volodya Lepeha                ////
////  Company: Unicore Systems http://unicore.co.ua              ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2010 Unicore Systems LTD                 ////
//// www.unicore.co.ua                                           ////
//// o.uzenkov@unicore.co.ua                                     ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// THIS SOFTWARE IS PROVIDED "AS IS"                           ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~           
// DESCRIPTION  :        First stage of FFT 128 processor
// FUNCTION:              8-point FFT
// FILES:                                       FFT8_3.v - 1-st stage, contains
//                    MPUC707.v - multiplier to the factor 0.707.
//  PROPERTIES: 1) Fully pipelined
//                                                      2) Each clock cycle complex datum is entered
//                           and complex result is outputted
//                                                       3) Has 8-clock cycle period starting with the START impulse
//                          and continuing forever
//                                                      4) rounding     is not used
//                                                      5)Algorithm is from the book "H.J.Nussbaumer FFT and convolution algorithms".
//                                                      6)IFFT is performed by substituting the output result order to the reversed one
//                                                              (by exchanging - to + and + to -)
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Algorithm:
//  procedure FFT8(
//               D: in MEMOC8;  -- input array
//               DO:out MEMOC8)  -- output ARRAY
//              is   
//              variable t1,t2,t3,t4,t5,t6,t7,t8,m0,m1,m2,m3,m4,m5,m6,m7: complex;
//              variable s1,s2,s3,s4: complex;
//      begin                                              
//              t1:=D(0) + D(4);
//              m3:=D(0) - D(4);
//              t2:=D(6) + D(2);
//          m6:=CBASE_j*(D(6)-D(2));
//              t3:=D(1) + D(5);
//              t4:=D(1) - D(5);
//              t5:=D(3) + D(7);
//              t6:=D(3) - D(7);
//              t8:=t5 + t3;
//              m5:=CBASE_j*(t5-t3);
//              t7:=t1 + t2;
//              m2:=t1 - t2;
//              m0:=t7 + t8;
//              m1:=t7 - t8;      
//              m4:=SQRT(0.5)*(t4 - t6);
//              m7:=-CBASE_j*SQRT(0.5)*(t4 + t6);          
//              s1:=m3 + m4;
//              s2:=m3 - m4;
//              s3:=m6 + m7;
//              s4:=m6 - m7;
//              DO(0):=m0;
//              DO(4):=m1;
//              DO(1):=s1 + s3;
//              DO(7):=s1 - s3;
//              DO(2):=m2 + m5;
//              DO(6):=m2 - m5;
//              DO(5):=s2 + s4;
//              DO(3):=s2 - s4;
//      end procedure;  
//                                                                                              
// Note that MPUC707 is multiplied a complex data for 2 clk cycles
//_____________________________________________________________ 
 
`timescale 1ps / 1ps
`include "FFT128_CONFIG.inc"
 
module FFT8 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY );
        `FFT128paramnb
 
        input ED ;
        wire ED ;
        input RST ;
        wire RST ;
        input CLK ;
        wire CLK ;
        input [nb-1:0] DII ;
        wire [nb-1:0] DII ;
        input START ;
        wire START ;
        input [nb-1:0] DIR ;
        wire [nb-1:0] DIR ;
 
        output [nb+2:0] DOI ;
        wire [nb+2:0] DOI ;
        output [nb+2:0] DOR ;
        wire [nb+2:0] DOR ;
        output RDY ;
        reg RDY ;
 
        reg [2:0] ct; //main phase counter
        reg [4:0] ctd; //delay counter
 
        always @(   posedge CLK) begin  //Control counter
                        //
                        if (RST)        begin
                                        ct<=0;
                                        ctd<=16;
                                RDY<=0;  end
                        else if (START)   begin
                                        ct<=0;
                                        ctd<=0;
                                RDY<=0;   end
                        else if (ED) begin
                                        RDY<=0;
                                        ct<=ct+1;
                                        if (ctd !=5'b10000)
                                                ctd<=ctd+1;
                                        if (ctd==15 )
                                                RDY<=1;
                                end
 
                end
 
        reg signed      [nb-1: 0] dr,d1r,d2r,d3r,d4r,di,d1i,d2i,d3i,d4i;
        always @(posedge CLK)     // input register file
                begin
                        if (ED)         begin
                                        dr<=DIR;
                                        d1r<=dr;
                                        d2r<=d1r;
                                        d3r<=d2r;
                                        d4r<=d3r;
                                        di<=DII;
                                        d1i<=di;
                                        d2i<=d1i;
                                        d3i<=d2i;
                                        d4i<=d3i;
                                end
                end
 
        reg signed      [nb:0]   s1r,s2r,s1d1r,s1d2r,s1d3r,s2d1r,s2d2r,s2d3r,m3r;
        reg signed      [nb:0]   s1i,s2i,s1d1i,s1d2i,s1d3i,s2d1i,s2d2i,s2d3i,m3i;
        always @(posedge CLK)   begin              // S1,S2 =t1-t6,m3 and delayed
                        if (ED && ((ct==5) || (ct==6) || (ct==7) || (ct==0))) begin
                                        s1r<=d4r + dr ;
                                        s1i<=d4i + di ;
                                        s2r<=d4r - dr ;
                                        s2i<= d4i - di;
                                end
                        if      (ED)   begin
                                        s1d1r<=s1r;
                                        s1d2r<=s1d1r;
                                        s1d1i<=s1i;
                                        s1d2i<=s1d1i;
                                        if (ct==0 || ct==1)       begin    //## note for vhdl
                                                        s1d3r<=s1d2r;
                                                        s1d3i<=s1d2i;
                                                end
                                        if (ct==6 || ct==7 || ct==0) begin
                                                        s2d1r<=s2r;
                                                        s2d2r<=s2d1r;
                                                        s2d1i<=s2i;
                                                        s2d2i<=s2d1i;
                                                end
                                        if (ct==0) begin
                                                        s2d3r<=s2d2r;
                                                        s2d3i<=s2d2i;
                                        end
                                        if (ct==7) begin
                                                        m3r<=s2d3r;
                                                        m3i<=s2d3i;
                                                end
                                end
                end
 
 
        reg signed [nb+1:0]      s3r,s4r,s3d1r,s3d2r,s3d3r,s3d4r,s3d5r,s3d6r,s3d7r;
        reg signed [nb+1:0]      s3i,s4i,s3d1i,s3d2i,s3d3i,s3d4i,s3d5i,s3d6i,s3d7i;
        always @(posedge CLK)   begin             //ALU S3:     
                        if (ED)
                                case (ct)
                                        0: begin s3r<=  s1d2r+s1r;                  //t7
                                                s3i<= s1d2i+ s1i ;end
                                        1: begin s3r<=  s1d3r - s1d1r;           //m2
                                                s3i<= s1d3i - s1d1i; end
                                        2: begin s3r<= s1d3r +s1r;               //t8
                                                s3i<= s1d3i+ s1i ; end
                                        3: begin s3r<=  s1d3r - s1r;             //
                                                s3i<= s1d3i - s1i ; end
                                endcase
 
                        s3d1r<=s3r;             s3d1i<=s3i;
                        s3d2r<=s3d1r;           s3d2i<=s3d1i;
                        s3d3r<=s3d2r;           s3d3i<=s3d2i;
                        if (ct==4 || ct==5 || ct==6|| ct==7) begin
                                        s3d4r<=s3d3r;           s3d4i<=s3d3i;
                                        s3d5r<=s3d4r;           s3d5i<=s3d4i;     //t8
                                end
                        if ( ct==6|| ct==7) begin
                                        s3d6r<=s3d5r;           s3d6i<=s3d5i;           //m2
                                        s3d7r<=s3d6r;           s3d7i<=s3d6i;      //t7
                                end
                end
 
 
        always @ (posedge CLK)  begin             // S4 
                        if (ED) begin
                                        if (ct==1) begin
                                                        s4r<= s2d2r + s2r;
                                                s4i<= s2d2i + s2i; end
                                        else if (ct==2) begin
                                                        s4r<=s2d2r - s2r;
                                                        s4i<= s2d2i - s2i;
                                                end
                                end
                end
 
        wire ds,mpyj;
        assign  ds = (ct==2 || ct==4 );
        assign mpyj = (ct==2);   // the multiplication by 0707 is followed by *J
        wire signed [nb+1:0] m4m7r,m4m7i;
 
        MPUC707 #(nb+2) UM707(.CLK(CLK),.ED(ED), .DS(ds), .MPYJ(mpyj) ,
        .DR(s4r),.DI(s4i),
        .DOR(m4m7r) ,.DOI(m4m7i)  );
 
        reg signed [nb+1:0]      sjr,sji, m7r,m7i;
        always @ (posedge CLK)  begin              //multiply by J 
                        if (ED) begin
                                if (ct==6) begin
                                                        m7r<=m4m7r;                              //m7
                                                        m7i<=m4m7i;
                                end
                                case  (ct)
                                                6: begin sjr<= s2d1i;                   //m6
                                                        sji<=0 - s2d1r; end
                                                1: begin sjr<= s3d4i;                                   //m5
                                                        sji<=0 - s3d4r;    end
                                        endcase
 
                                end
                end
 
                reg     signed [nb+2:0]  s7r,s7i,rs3r,rs3i;
                always @ (posedge CLK)               //         S7:
                if (ED)
                        case (ct)
                                0:begin s7r<= sjr + m7r;
                                        s7i<= sji + m7i;  end
                         1:begin s7r<= sjr - m7r;
                                 s7i<= sji - m7i;
                                 rs3r<=s7r;
                                  rs3i<=s7i; end
                         endcase
 
        reg     signed [nb+2:0]  s5r,rs1r;
        reg     signed [nb+2:0]  s5i,rs1i;
        always @ (posedge CLK)               //         S5:
                if (ED)
                        case (ct)
                                0:begin s5r<= m3r + m4m7r;
                                        s5i<= m3i + m4m7i;  end
                         1:begin s5r<= m3r - m4m7r;
                                 s5i<= m3i - m4m7i;
                                 rs1r<=s5r;
                                  rs1i<=s5i; end
                         endcase
 
        reg     signed [nb+3:0]  s6r,s6i ;
        `ifdef FFT128paramifft
        always @ (posedge CLK)  begin            //  S6-- result adder
                        if (ED)
                                case  (ct)
                                        0: begin s6r<=s3d7r +s3d5r ;       // --  D0
                                                s6i<=s3d7i +s3d5i ;end     //--  D0
                                        1:  begin
                                                        s6r<=s5r - s7r ;                     //--        D1
                                                s6i<=s5i - s7i ; end
                                        2:   begin
                                                        s6r<=s3d6r -sjr ;                //--    D2
                                                s6i<=s3d6i -sji ;          end
                                        3:   begin
                                                        s6r<=s5r + s7r ;                       // --     D3
                                                s6i<= s5i + s7i ;end
 
                                        4:begin s6r<=s3d7r - s3d5r ;        //--         D4
                                                s6i<=s3d7i - s3d5i ; end
                                        5:   begin
                                                        s6r<=s5r - s7r ;                      //--       D5
                                                s6i<=s5i - s7i ; end
 
                                        6:  begin
                                                        s6r<= s3d6r + sjr ;             //       D6
                                                s6i<=s3d6i + sji ;      end
 
                                        7:   begin
                                                        s6r<= rs1r + rs3r ;              //      D0
                                                s6i<=  rs1i + rs3i ;    end
 
                                endcase
                end
 
        `else
        always @ (posedge CLK)  begin            //  S6-- result adder
                        if (ED)
                                case  (ct)
                                        0: begin s6r<=s3d7r +s3d5r ;       // --  D0
                                                s6i<=s3d7i +s3d5i ;end     //--  D0
                                        1:  begin
                                                        s6r<=s5r + s7r ;                     //--        D1
                                                s6i<=s5i + s7i ; end
                                        2:   begin
                                                        s6r<=s3d6r +sjr ;                //--    D2
                                                s6i<=s3d6i +sji ;          end
                                        3:   begin
                                                        s6r<=s5r - s7r ;                       // --     D3
                                                s6i<= s5i - s7i ;end
 
                                        4:begin s6r<=s3d7r - s3d5r ;        //--         D4
                                                s6i<=s3d7i - s3d5i ; end
                                        5:   begin
                                                        s6r<=s5r + s7r ;                      //--       D5
                                                s6i<=s5i + s7i ; end
 
                                        6:  begin
                                                        s6r<= s3d6r - sjr ;             //       D6
                                                s6i<=s3d6i - sji ;      end
 
                                        7:   begin
                                                        s6r<= rs1r - rs3r ;              //      D0
                                                s6i<=  rs1i - rs3i ;    end
 
                                endcase
                end
        `endif
 
        assign #1       DOR=s6r[nb+2:0];
        assign #1       DOI= s6i[nb+2:0];
 
endmodule

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Subversion Repositories pipelined_fft_128

[/] [pipelined_fft_128/] [trunk/] [SRC/] [fft8_3.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	unicore	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// FFT/IFFT 128 points transform ////`
4			`//// ////`
5			`//// Authors: Anatoliy Sergienko, Volodya Lepeha ////`
6			`//// Company: Unicore Systems http://unicore.co.ua ////`
7			`//// ////`
8			`//// Downloaded from: http://www.opencores.org ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2006-2010 Unicore Systems LTD ////`
13			`//// www.unicore.co.ua ////`
14			`//// o.uzenkov@unicore.co.ua ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer.////`
20			`//// ////`
21			`//// THIS SOFTWARE IS PROVIDED "AS IS" ////`
22			`//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////`
23			`//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////`
24			`//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////`
25			`//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////`
26			`//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////`
27			`//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////`
29			`//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////`
30			`//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////`
31			`//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////`
32			`//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////`
33			`//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////`
35			`//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////`
36			`//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39			`//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
40			`// DESCRIPTION : First stage of FFT 128 processor`
41			`// FUNCTION: 8-point FFT`
42			`// FILES: FFT8_3.v - 1-st stage, contains`
43			`// MPUC707.v - multiplier to the factor 0.707.`
44			`// PROPERTIES: 1) Fully pipelined`
45			`// 2) Each clock cycle complex datum is entered`
46			`// and complex result is outputted`
47			`// 3) Has 8-clock cycle period starting with the START impulse`
48			`// and continuing forever`
49			`// 4) rounding is not used`
50			`// 5)Algorithm is from the book "H.J.Nussbaumer FFT and convolution algorithms".`
51			`// 6)IFFT is performed by substituting the output result order to the reversed one`
52			`// (by exchanging - to + and + to -)`
53			`//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
54			`//Algorithm:`
55			`// procedure FFT8(`
56			`// D: in MEMOC8; -- input array`
57			`// DO:out MEMOC8) -- output ARRAY`
58			`// is`
59			`// variable t1,t2,t3,t4,t5,t6,t7,t8,m0,m1,m2,m3,m4,m5,m6,m7: complex;`
60			`// variable s1,s2,s3,s4: complex;`
61			`// begin`
62			`// t1:=D(0) + D(4);`
63			`// m3:=D(0) - D(4);`
64			`// t2:=D(6) + D(2);`
65			`// m6:=CBASE_j*(D(6)-D(2));`
66			`// t3:=D(1) + D(5);`
67			`// t4:=D(1) - D(5);`
68			`// t5:=D(3) + D(7);`
69			`// t6:=D(3) - D(7);`
70			`// t8:=t5 + t3;`
71			`// m5:=CBASE_j*(t5-t3);`
72			`// t7:=t1 + t2;`
73			`// m2:=t1 - t2;`
74			`// m0:=t7 + t8;`
75			`// m1:=t7 - t8;`
76			`// m4:=SQRT(0.5)*(t4 - t6);`
77			`// m7:=-CBASE_jSQRT(0.5)(t4 + t6);`
78			`// s1:=m3 + m4;`
79			`// s2:=m3 - m4;`
80			`// s3:=m6 + m7;`
81			`// s4:=m6 - m7;`
82			`// DO(0):=m0;`
83			`// DO(4):=m1;`
84			`// DO(1):=s1 + s3;`
85			`// DO(7):=s1 - s3;`
86			`// DO(2):=m2 + m5;`
87			`// DO(6):=m2 - m5;`
88			`// DO(5):=s2 + s4;`
89			`// DO(3):=s2 - s4;`
90			`// end procedure;`
91			`//`
92			`// Note that MPUC707 is multiplied a complex data for 2 clk cycles`
93			`//_____________________________________________________________`
94
95			`timescale 1ps / 1ps
96			`include "FFT128_CONFIG.inc"
97
98			`module FFT8 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY );`
99			`FFT128paramnb
100
101			`input ED ;`
102			`wire ED ;`
103			`input RST ;`
104			`wire RST ;`
105			`input CLK ;`
106			`wire CLK ;`
107			`input [nb-1:0] DII ;`
108			`wire [nb-1:0] DII ;`
109			`input START ;`
110			`wire START ;`
111			`input [nb-1:0] DIR ;`
112			`wire [nb-1:0] DIR ;`
113
114			`output [nb+2:0] DOI ;`
115			`wire [nb+2:0] DOI ;`
116			`output [nb+2:0] DOR ;`
117			`wire [nb+2:0] DOR ;`
118			`output RDY ;`
119			`reg RDY ;`
120
121			`reg [2:0] ct; //main phase counter`
122			`reg [4:0] ctd; //delay counter`
123
124			`always @( posedge CLK) begin //Control counter`
125			`//`
126			`if (RST) begin`
127			`ct<=0;`
128			`ctd<=16;`
129			`RDY<=0; end`
130			`else if (START) begin`
131			`ct<=0;`
132			`ctd<=0;`
133			`RDY<=0; end`
134			`else if (ED) begin`
135			`RDY<=0;`
136			`ct<=ct+1;`
137			`if (ctd !=5'b10000)`
138			`ctd<=ctd+1;`
139			`if (ctd==15 )`
140			`RDY<=1;`
141			`end`
142
143			`end`
144
145			`reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,di,d1i,d2i,d3i,d4i;`
146			`always @(posedge CLK) // input register file`
147			`begin`
148			`if (ED) begin`
149			`dr<=DIR;`
150			`d1r<=dr;`
151			`d2r<=d1r;`
152			`d3r<=d2r;`
153			`d4r<=d3r;`
154			`di<=DII;`
155			`d1i<=di;`
156			`d2i<=d1i;`
157			`d3i<=d2i;`
158			`d4i<=d3i;`
159			`end`
160			`end`
161
162			`reg signed [nb:0] s1r,s2r,s1d1r,s1d2r,s1d3r,s2d1r,s2d2r,s2d3r,m3r;`
163			`reg signed [nb:0] s1i,s2i,s1d1i,s1d2i,s1d3i,s2d1i,s2d2i,s2d3i,m3i;`
164			`always @(posedge CLK) begin // S1,S2 =t1-t6,m3 and delayed`
165			`if (ED && ((ct==5) \|\| (ct==6) \|\| (ct==7) \|\| (ct==0))) begin`
166			`s1r<=d4r + dr ;`
167			`s1i<=d4i + di ;`
168			`s2r<=d4r - dr ;`
169			`s2i<= d4i - di;`
170			`end`
171			`if (ED) begin`
172			`s1d1r<=s1r;`
173			`s1d2r<=s1d1r;`
174			`s1d1i<=s1i;`
175			`s1d2i<=s1d1i;`
176			`if (ct==0 \|\| ct==1) begin //## note for vhdl`
177			`s1d3r<=s1d2r;`
178			`s1d3i<=s1d2i;`
179			`end`
180			`if (ct==6 \|\| ct==7 \|\| ct==0) begin`
181			`s2d1r<=s2r;`
182			`s2d2r<=s2d1r;`
183			`s2d1i<=s2i;`
184			`s2d2i<=s2d1i;`
185			`end`
186			`if (ct==0) begin`
187			`s2d3r<=s2d2r;`
188			`s2d3i<=s2d2i;`
189			`end`
190			`if (ct==7) begin`
191			`m3r<=s2d3r;`
192			`m3i<=s2d3i;`
193			`end`
194			`end`
195			`end`
196
197
198			`reg signed [nb+1:0] s3r,s4r,s3d1r,s3d2r,s3d3r,s3d4r,s3d5r,s3d6r,s3d7r;`
199			`reg signed [nb+1:0] s3i,s4i,s3d1i,s3d2i,s3d3i,s3d4i,s3d5i,s3d6i,s3d7i;`
200			`always @(posedge CLK) begin //ALU S3:`
201			`if (ED)`
202			`case (ct)`
203			`0: begin s3r<= s1d2r+s1r; //t7`
204			`s3i<= s1d2i+ s1i ;end`
205			`1: begin s3r<= s1d3r - s1d1r; //m2`
206			`s3i<= s1d3i - s1d1i; end`
207			`2: begin s3r<= s1d3r +s1r; //t8`
208			`s3i<= s1d3i+ s1i ; end`
209			`3: begin s3r<= s1d3r - s1r; //`
210			`s3i<= s1d3i - s1i ; end`
211			`endcase`
212
213			`s3d1r<=s3r; s3d1i<=s3i;`
214			`s3d2r<=s3d1r; s3d2i<=s3d1i;`
215			`s3d3r<=s3d2r; s3d3i<=s3d2i;`
216			`if (ct==4 \|\| ct==5 \|\| ct==6\|\| ct==7) begin`
217			`s3d4r<=s3d3r; s3d4i<=s3d3i;`
218			`s3d5r<=s3d4r; s3d5i<=s3d4i; //t8`
219			`end`
220			`if ( ct==6\|\| ct==7) begin`
221			`s3d6r<=s3d5r; s3d6i<=s3d5i; //m2`
222			`s3d7r<=s3d6r; s3d7i<=s3d6i; //t7`
223			`end`
224			`end`
225
226
227			`always @ (posedge CLK) begin // S4`
228			`if (ED) begin`
229			`if (ct==1) begin`
230			`s4r<= s2d2r + s2r;`
231			`s4i<= s2d2i + s2i; end`
232			`else if (ct==2) begin`
233			`s4r<=s2d2r - s2r;`
234			`s4i<= s2d2i - s2i;`
235			`end`
236			`end`
237			`end`
238
239			`wire ds,mpyj;`
240			`assign ds = (ct==2 \|\| ct==4 );`
241			`assign mpyj = (ct==2); // the multiplication by 0707 is followed by *J`
242			`wire signed [nb+1:0] m4m7r,m4m7i;`
243
244			`MPUC707 #(nb+2) UM707(.CLK(CLK),.ED(ED), .DS(ds), .MPYJ(mpyj) ,`
245			`.DR(s4r),.DI(s4i),`
246			`.DOR(m4m7r) ,.DOI(m4m7i) );`
247
248			`reg signed [nb+1:0] sjr,sji, m7r,m7i;`
249			`always @ (posedge CLK) begin //multiply by J`
250			`if (ED) begin`
251			`if (ct==6) begin`
252			`m7r<=m4m7r; //m7`
253			`m7i<=m4m7i;`
254			`end`
255			`case (ct)`
256			`6: begin sjr<= s2d1i; //m6`
257			`sji<=0 - s2d1r; end`
258			`1: begin sjr<= s3d4i; //m5`
259			`sji<=0 - s3d4r; end`
260			`endcase`
261
262			`end`
263			`end`
264
265			`reg signed [nb+2:0] s7r,s7i,rs3r,rs3i;`
266			`always @ (posedge CLK) // S7:`
267			`if (ED)`
268			`case (ct)`
269			`0:begin s7r<= sjr + m7r;`
270			`s7i<= sji + m7i; end`
271			`1:begin s7r<= sjr - m7r;`
272			`s7i<= sji - m7i;`
273			`rs3r<=s7r;`
274			`rs3i<=s7i; end`
275			`endcase`
276
277			`reg signed [nb+2:0] s5r,rs1r;`
278			`reg signed [nb+2:0] s5i,rs1i;`
279			`always @ (posedge CLK) // S5:`
280			`if (ED)`
281			`case (ct)`
282			`0:begin s5r<= m3r + m4m7r;`
283			`s5i<= m3i + m4m7i; end`
284			`1:begin s5r<= m3r - m4m7r;`
285			`s5i<= m3i - m4m7i;`
286			`rs1r<=s5r;`
287			`rs1i<=s5i; end`
288			`endcase`
289
290			`reg signed [nb+3:0] s6r,s6i ;`
291			`ifdef FFT128paramifft
292			`always @ (posedge CLK) begin // S6-- result adder`
293			`if (ED)`
294			`case (ct)`
295			`0: begin s6r<=s3d7r +s3d5r ; // -- D0`
296			`s6i<=s3d7i +s3d5i ;end //-- D0`
297			`1: begin`
298			`s6r<=s5r - s7r ; //-- D1`
299			`s6i<=s5i - s7i ; end`
300			`2: begin`
301			`s6r<=s3d6r -sjr ; //-- D2`
302			`s6i<=s3d6i -sji ; end`
303			`3: begin`
304			`s6r<=s5r + s7r ; // -- D3`
305			`s6i<= s5i + s7i ;end`
306
307			`4:begin s6r<=s3d7r - s3d5r ; //-- D4`
308			`s6i<=s3d7i - s3d5i ; end`
309			`5: begin`
310			`s6r<=s5r - s7r ; //-- D5`
311			`s6i<=s5i - s7i ; end`
312
313			`6: begin`
314			`s6r<= s3d6r + sjr ; // D6`
315			`s6i<=s3d6i + sji ; end`
316
317			`7: begin`
318			`s6r<= rs1r + rs3r ; // D0`
319			`s6i<= rs1i + rs3i ; end`
320
321			`endcase`
322			`end`
323
324			`else
325			`always @ (posedge CLK) begin // S6-- result adder`
326			`if (ED)`
327			`case (ct)`
328			`0: begin s6r<=s3d7r +s3d5r ; // -- D0`
329			`s6i<=s3d7i +s3d5i ;end //-- D0`
330			`1: begin`
331			`s6r<=s5r + s7r ; //-- D1`
332			`s6i<=s5i + s7i ; end`
333			`2: begin`
334			`s6r<=s3d6r +sjr ; //-- D2`
335			`s6i<=s3d6i +sji ; end`
336			`3: begin`
337			`s6r<=s5r - s7r ; // -- D3`
338			`s6i<= s5i - s7i ;end`
339
340			`4:begin s6r<=s3d7r - s3d5r ; //-- D4`
341			`s6i<=s3d7i - s3d5i ; end`
342			`5: begin`
343			`s6r<=s5r + s7r ; //-- D5`
344			`s6i<=s5i + s7i ; end`
345
346			`6: begin`
347			`s6r<= s3d6r - sjr ; // D6`
348			`s6i<=s3d6i - sji ; end`
349
350			`7: begin`
351			`s6r<= rs1r - rs3r ; // D0`
352			`s6i<= rs1i - rs3i ; end`
353
354			`endcase`
355			`end`
356			`endif
357
358			`assign #1 DOR=s6r[nb+2:0];`
359			`assign #1 DOI= s6i[nb+2:0];`
360
361			`endmodule`