OpenCores
URL https://opencores.org/ocsvn/pipelined_fft_128/pipelined_fft_128/trunk

Subversion Repositories pipelined_fft_128

[/] [pipelined_fft_128/] [trunk/] [SRC/] [mpuc1307.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 unicore
/////////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  FFT/IFFT 128 points transform                              ////
4
////                                                             ////
5
////  Authors: Anatoliy Sergienko, Volodya Lepeha                ////
6
////  Company: Unicore Systems http://unicore.co.ua              ////
7
////                                                             ////
8
////  Downloaded from: http://www.opencores.org                  ////
9
////                                                             ////
10
/////////////////////////////////////////////////////////////////////
11
////                                                             ////
12
//// Copyright (C) 2006-2010 Unicore Systems LTD                 ////
13
//// www.unicore.co.ua                                           ////
14
//// o.uzenkov@unicore.co.ua                                     ////
15
////                                                             ////
16
//// This source file may be used and distributed without        ////
17
//// restriction provided that this copyright statement is not   ////
18
//// removed from the file and that any derivative work contains ////
19
//// the original copyright notice and the associated disclaimer.////
20
////                                                             ////
21
//// THIS SOFTWARE IS PROVIDED "AS IS"                           ////
22
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ////
23
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ////
24
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ////
25
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ////
26
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ////
27
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ////
28
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ////
29
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ////
30
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ////
31
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ////
32
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ////
33
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ////
34
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ////
35
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ////
36
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ////
37
////                                                             ////
38
/////////////////////////////////////////////////////////////////////
39
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~           
40
// DESCRIPTION  :        Complex Multiplier by 0.7071
41
// FUNCTION:               Constant multiplier   to cos(PI/8)+cos(3*PI/8) =1.307
42
// FILES:                        MPUŃ1307.v
43
//  PROPERTIES: 1) Is based on shifts right and add
44
//                                                      2) for short input bit width 1.307 is approximated as 1_0100_111       =         1_0101_00T                             
45
//                                                      3) for medium bit width 1.3066 is approximated as 1_0100_1110_0111_11= 1_0101_00T0_1000_0T                     
46
//                                                      4) for long  bit width 1.30656 is approximated as 1_0100_1110_0111_1011=1_0101_00T0_1000_0T0T                          
47
//                                                  5) hardware is 3 or 5, or 6 adders   +1
48
//                                                  6) MPYJ switches multiply by j                               
49
//                                                      6) A complex data is multiplied for 2 cycles, latent delay=4
50
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
51
`include "FFT128_CONFIG.inc"
52
 
53
module MPUC1307 ( CLK,DS ,ED, MPYJ,DR,DI ,DOR ,DOI,  );
54
        `FFT128paramnb
55
 
56
        input CLK ;
57
        wire CLK ;
58
        input DS ;
59
        wire DS ;
60
        input ED;                                       //data strobe
61
        input MPYJ ;                            //the result is multiplied by -j
62
        wire MPYJ ;
63
        input [nb-1:0] DR ;
64
        wire signed [nb-1:0] DR ;
65
        input [nb-1:0] DI ;
66
        wire signed [nb-1:0] DI ;
67
 
68
        output [nb:0] DOR ;
69
        reg [nb:0] DOR ;
70
        output [nb:0] DOI ;
71
        reg [nb:0] DOI ;
72
 
73
        reg signed [nb+2 :0] dx5;
74
        reg signed [nb-1 :0] dx7;
75
        reg signed [nb-1 :0] dii;
76
        reg signed      [nb : 0] dt;
77
        wire signed [nb+3 : 0]  dx5p;
78
        wire  signed  [nb+3 : 0] dot;
79
        reg edd,edd2, edd3;                     //delayed data enable impulse        
80
        reg mpyjd,mpyjd2,mpyjd3;
81
        reg [nb:0] doo ;
82
        reg [nb:0] droo ;
83
 
84
        always @(posedge CLK)
85
                begin
86
                        if (ED) begin
87
                                        edd<=DS;
88
                                        edd2<=edd;
89
                                        edd3<=edd2;
90
                                        mpyjd<=MPYJ;
91
                                        mpyjd2<=mpyjd;
92
                                        mpyjd3<=mpyjd2;                                  //1_0100_1110_0111_1011
93
                                        if (DS)  begin                                          //       1_0101_00T0_1000_0T0T           
94
                                                        dx5<=DR+(DR <<2);        //multiply by 5 
95
                                                        dx7<=DR-(DR>>>3);        //multiply by 7, shifted right to 2 
96
                                                        dt<=DR;
97
                                                        dii<=DI;
98
                                                end
99
                                        else     begin
100
                                                        dx5<=dii+(dii <<2);      //multiply by 5
101
                                                        dx7<=dii-(dii>>>3);      //multiply by 7, shifted right to 3 
102
                                                        dt<=dii;
103
                                                end
104
                                        doo<=dot >>>3;
105
                                        droo<=doo;
106
                                        if (edd3)
107
                                                if (mpyjd3) begin
108
                                                                DOR<=doo;
109
                                                        DOI<= - droo; end
110
                                                else begin
111
                                                                DOR<=droo;
112
                                                        DOI<=  doo; end
113
                                end
114
                end
115
 
116
        assign  dx5p=(dx5<<1)+(dx7>>>1);                // multiply by 1_0101_00T               
117
 
118
        `ifdef FFT128bitwidth_coef_high
119
        assign   dot=   (dx5p+(dt>>>6) -(dx5>>>13));// multiply by 1_0101_00T0_1000_0T0T                      
120
        `else
121
        assign    dot=  dx5p+(dt>>>6);
122
        `endif
123
 
124
 
125
 
126
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.