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[/] [pipelined_fft_128/] [trunk/] [SRC/] [mpuc707.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  FFT/IFFT 128 points transform                              ////
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////                                                             ////
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////  Authors: Anatoliy Sergienko, Volodya Lepeha                ////
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////  Company: Unicore Systems http://unicore.co.ua              ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2006-2010 Unicore Systems LTD                 ////
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//// www.unicore.co.ua                                           ////
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//// o.uzenkov@unicore.co.ua                                     ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// THIS SOFTWARE IS PROVIDED "AS IS"                           ////
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//// AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ////
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//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ////
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//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ////
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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ////
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//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ////
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//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ////
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//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ////
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//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ////
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//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ////
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//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ////
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//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ////
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//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ////
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//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~           
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// DESCRIPTION  :        Complex Multiplier by 0.7071
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// FUNCTION:               Constant multiplier
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// FILES:                        MPU707.v
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//  PROPERTIES: 1) Is based on shifts right and add
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//                                                      2) for short input bit width 0.7071 is approximated as 10110101                            then rounding        is not used
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//                                                      3) for long input bit width 0.7071 is approximated as 10110101000000101        
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//                                                  4) hardware is 4 or 5 adders 
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//                                                  5) MPYJ switches multiply by j                               
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//                                                      6) A complex data is multiplied for 2 cycles
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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`include "FFT128_CONFIG.inc"
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module MPUC707 ( CLK,ED, DS, MPYJ,DR,DI ,DOR ,DOI,  );
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        `FFT128paramnb
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//      MPUC707 #(nb+2) UM707(.CLK(CLK),.ED(ED), .DS(es), .MPYJ(mpyj) ,
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        input CLK ;
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        wire CLK ;
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        input DS ;                                      //data strobe
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        wire DS ;
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        input ED;                                        //slowdown
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        input MPYJ ;                            //the result is multiplied by -j
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        wire MPYJ ;
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        input [nb-1:0] DR ;
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        wire signed [nb-1:0] DR ;
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        input [nb-1:0] DI ;
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        wire signed [nb-1:0] DI ;
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        output [nb-1:0] DOR ;
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        reg [nb-1:0] DOR ;
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        output [nb-1:0] DOI ;
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        reg [nb-1:0] DOI ;
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        reg signed [nb+1 :0] dx5;
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        reg signed      [nb : 0] dt;
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        reg signed      [nb-1 : 0] dii;
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        wire signed [nb+2 : 0]  dx5p;
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        wire  signed  [nb+3 : 0] dot;
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        reg edd,edd2, edd3;                     //delayed data enable impulse        
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        reg mpyjd,mpyjd2,mpyjd3;
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        reg [nb-1:0] doo ;
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        reg [nb-1:0] droo ;
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        always @(posedge CLK)
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                begin
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                        if (ED) begin
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                                        edd<=DS;
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                                        edd2<=edd;
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                                        edd3<=edd2;
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                                        mpyjd<=MPYJ;
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                                        mpyjd2<=mpyjd;
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                                        mpyjd3<=mpyjd2;
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                                        if (DS)  begin
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                                                        dx5<=DR+(DR <<2);        //multiply by 5 
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                                                        dt<=DR;
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                                                        dii<=DI;
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                                                end
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                                        else     begin
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                                                        dx5<=dii+(dii <<2);      //multiply by 5
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                                                        dt<=dii;
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                                                end
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                                        doo<=(dot >>>4) ;
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                                        droo<=doo;
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                                        if (edd3)
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                                                if (mpyjd3) begin
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                                                                DOR<=doo;
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                                                        DOI<= - droo; end
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                                                else begin
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                                                                DOR<=droo;
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                                                        DOI<=  doo; end
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                                end
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                end
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        assign  dx5p=(dx5<<1)+(dx5>>>2);                // multiply by 101101                   
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        `ifdef FFT128bitwidth_coef_high
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        assign   dot=   dx5p+(dt>>>4)+(dx5>>>12);//     (dt>>>9);   // multiply by 10110101000000101          
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        `else
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        assign    dot=          dx5p+(dt>>>4)   ;  // multiply by 10110101         
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        `endif
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endmodule

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