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`define MAX(a,b) ( (a)>(b)? (a):(b) )
`define ABS(a) ( (a)>0? (a):(-(a)) )
 
//============================= XOR VARIATION ===================================
 
//module Ibniz_generator7z ( clk, rst, ena, T_in, X_in, Y_in, V_out );
//
//input clk;
//input rst;
//input ena;
//input wire signed [31:0] T_in;
//input wire signed [31:0] X_in;
//input wire signed [31:0] Y_in;
//output reg [31:0] V_out;
//
//wire [31:0] XxY= ( X_in+ (X_in <<T_in[28:24] ) )^ ( Y_in + T_in[26:10] ) ;
//wire [31:0] V0= XxY+ (T_in>>7);
//
//always@(posedge clk or posedge rst)
//begin
//      if ( rst )
//      begin
//      end
//      else if ( ena )
//      begin
//      //      **
////            XY <=((XX_in * YY_in)>>>16);
////            V_out<= ( XY * (TT_in))>>>16;
//      //      ^x7r+Md8r& (xor exch ror(7) +   )
//              V_out= V0 + ((V0<<(T_in[29:25])) & 32'hFFFF0000 );
//      end
//end
//endmodule
 
module Ibniz_Stars ( clk, rst, ena, T_in, X_in, Y_in, V_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] X_in;
input wire signed [31:0] Y_in;
output reg [31:0] V_out;
 
reg [31:0] R1;
reg [31:0] R2;
reg [31:0] R3;
reg [31:0] G1;
reg [31:0] G2;
reg [31:0] G3;
 
always@(posedge clk or posedge rst)
begin
        if ( rst )
        begin
        end
        else if ( ena )
        begin
                R1 <= (((X_in+T_in[31:12])>>>7)) * 11713 + ((Y_in>>>8)+(Y_in)) * 5422133;
                R2 <= R1 * 7 + (R1>>8)*1817 ;
                R3 <= { R2[7:0],R2[15:8],R2[23:16], R2[7:0] ^ R2[15:8] ^ R2[23:16] ^ R2[31:24] };
        //      **
                V_out <= R3[7:0] ? 0 : R3[8] ? -1 : R3;
        end
end
endmodule
 
//============================= ATAN2 ===================================
module Ibniz_generator0 ( clk, rst, ena, T_in, _X_in, _Y_in, V_out, dbg_out );
 
input clk;
input rst;
input ena;
input wire signed [31:0] T_in;
input wire signed [31:0] _X_in;
input wire signed [31:0] _Y_in;
output reg [31:0] V_out;
output reg signed [63:0] dbg_out;
 
wire signed [31:0] X_in=  _X_in/2;
wire signed [31:0] Y_in=  _Y_in/2;
 
always@(posedge clk or posedge rst)
begin
        if ( rst )
        begin
        end
        else if ( ena )
        begin
                //      &*
//              V_out= ((d_out<<<4)+(T_in>>>6))^(s_out>>6);
                V_out=
//                                      `ABS(_X_in) > 32'hF800 ? 0: 
                                                                                                        V0;// + ((V0<<(T_in[29:25])) & 32'hFFFF0000 );
        end
end
 
//wire [31:0] V0= ((d_out-(T_in>>>14)) *20) ^((div_out>>>12)+(T_in>>>8));//((a_out[23:16]==Y_in[15:8])? -1:0);
 
wire [31:0] V0;
 
wire signed [31:0] T_sin;
PseudoSin ( clk, rst, ena, T_in>>>7, T_sin, _ );
 
 
Psin_Texture ( clk, rst, ena, T_in, ((d_out-(T_sin>>>7)-(T_in>>>13)) *20), ((div_out>>>12)+(T_sin)+(T_in>>>5)), V0 );
//Psin_Texture ( clk, rst, ena, T_in, ((d_out-(T_in>>>13)) *20), ((div_out>>>12)+(T_in>>>7)), V0 );
 
wire signed [31:0] s_out;
wire signed [31:0] a_out;
wire signed [31:0] a_outm;
wire signed [31:0] d_out;
wire signed [31:0] XX= ( (X_in) *(X_in) )>>12;
wire signed [31:0] YY= ( Y_in*Y_in)>>12;
wire signed [31:0] XXYY= XX+YY;
 
atan2_pipelined atan( clk, X_in, Y_in, a_out, _ );
 
defparam atan.IS_IBNIZ= 1;
//div_pipelined mydiv( clk, a_out<<12, pix2, d_out );
id_pipelined id( clk, a_out, d_out );
defparam id.DELAY= 16;
sqrt_pipelined sqrt1( clk, XXYY, s_out, _ );
 
wire signed [31:0] sin_a;
wire signed [31:0] cos_a;
wire signed [31:0] sin_q;
wire signed [31:0] div_out;
 
div_pipelined div1( clk, 48'h400000000000, XXYY, div_out );
defparam div1.BITS= 48;
 
endmodule
 
 
 
//============================= CIRCLES ===================================
//module Ibniz_generator7y ( clk, rst, ena, T_in, X_in, Y_in, V_out, dbg_out );
//
//input clk;
//input rst;
//input ena;
//input wire signed [31:0] T_in;
//input wire signed [35:0] X_in;
//input wire signed [35:0] Y_in;
//output reg [31:0] V_out;
//output reg signed [63:0] dbg_out;
//
//always@(posedge clk or posedge rst)
//begin
//      if ( rst )
//      begin
//      end
//      else if ( ena )
//      begin
//              //      &*
//              V_out= s_out*(T_in>>16);
//      end
//end
//
//wire signed [31:0] s_out;
//wire signed [31:0] d_out;
//sqrt_pipelined sqrt1( clk, (X_in*X_in+Y_in*Y_in)>>>16, s_out, d_out );
//
//wire signed [31:0] XXX = X_in<<16;
//wire signed [31:0] XXX2 = (X_in-16*128);
//wire signed [31:0] YYY = Y_in<<16;
//wire signed [31:0] YYY_p = (YYY-256);
//wire signed [31:0] g_out = (YYY==0 || XXX==0 || X_in==32'h8000 || Y_in==(-32'h8000) ) ? -16'sh1 : 
//                                                                                                      ((YYY >= s_out /*&& YYY_p<-s_out*/) ? 32'h33338000 : 32'h0)
////                                                                             +(  (YYY >= d_out /*&& YYY_p<-d_out*/) ? 32'hCC008000 : 32'h0)
////                                                                             +(  (YYY >= -c_out && YYY_p<-c_out) ? 32'h88888000 : 32'h0)
//                                                                                              ;
//
//endmodule
 
//
 

Line No.	Rev	Author	Line
1	5	leshabiruk
2			`define MAX(a,b) ( (a)>(b)? (a):(b) )
3			`define ABS(a) ( (a)>0? (a):(-(a)) )
4
5			`//============================= XOR VARIATION ===================================`
6
7			`//module Ibniz_generator7z ( clk, rst, ena, T_in, X_in, Y_in, V_out );`
8			`//`
9			`//input clk;`
10			`//input rst;`
11			`//input ena;`
12			`//input wire signed [31:0] T_in;`
13			`//input wire signed [31:0] X_in;`
14			`//input wire signed [31:0] Y_in;`
15			`//output reg [31:0] V_out;`
16			`//`
17			`//wire [31:0] XxY= ( X_in+ (X_in <<T_in[28:24] ) )^ ( Y_in + T_in[26:10] ) ;`
18			`//wire [31:0] V0= XxY+ (T_in>>7);`
19			`//`
20			`//always@(posedge clk or posedge rst)`
21			`//begin`
22			`// if ( rst )`
23			`// begin`
24			`// end`
25			`// else if ( ena )`
26			`// begin`
27			`// // **`
28			`//// XY <=((XX_in * YY_in)>>>16);`
29			`//// V_out<= ( XY * (TT_in))>>>16;`
30			`// // ^x7r+Md8r& (xor exch ror(7) + )`
31			`// V_out= V0 + ((V0<<(T_in[29:25])) & 32'hFFFF0000 );`
32			`// end`
33			`//end`
34			`//endmodule`
35
36			`module Ibniz_Stars ( clk, rst, ena, T_in, X_in, Y_in, V_out );`
37
38			`input clk;`
39			`input rst;`
40			`input ena;`
41			`input wire signed [31:0] T_in;`
42			`input wire signed [31:0] X_in;`
43			`input wire signed [31:0] Y_in;`
44			`output reg [31:0] V_out;`
45
46			`reg [31:0] R1;`
47			`reg [31:0] R2;`
48			`reg [31:0] R3;`
49			`reg [31:0] G1;`
50			`reg [31:0] G2;`
51			`reg [31:0] G3;`
52
53			`always@(posedge clk or posedge rst)`
54			`begin`
55			`if ( rst )`
56			`begin`
57			`end`
58			`else if ( ena )`
59			`begin`
60			`R1 <= (((X_in+T_in[31:12])>>>7)) * 11713 + ((Y_in>>>8)+(Y_in)) * 5422133;`
61			`R2 <= R1 * 7 + (R1>>8)*1817 ;`
62			`R3 <= { R2[7:0],R2[15:8],R2[23:16], R2[7:0] ^ R2[15:8] ^ R2[23:16] ^ R2[31:24] };`
63			`// **`
64			`V_out <= R3[7:0] ? 0 : R3[8] ? -1 : R3;`
65			`end`
66			`end`
67			`endmodule`
68
69			`//============================= ATAN2 ===================================`
70			`module Ibniz_generator0 ( clk, rst, ena, T_in, _X_in, _Y_in, V_out, dbg_out );`
71
72			`input clk;`
73			`input rst;`
74			`input ena;`
75			`input wire signed [31:0] T_in;`
76			`input wire signed [31:0] _X_in;`
77			`input wire signed [31:0] _Y_in;`
78			`output reg [31:0] V_out;`
79			`output reg signed [63:0] dbg_out;`
80
81			`wire signed [31:0] X_in= _X_in/2;`
82			`wire signed [31:0] Y_in= _Y_in/2;`
83
84			`always@(posedge clk or posedge rst)`
85			`begin`
86			`if ( rst )`
87			`begin`
88			`end`
89			`else if ( ena )`
90			`begin`
91			`// &*`
92			`// V_out= ((d_out<<<4)+(T_in>>>6))^(s_out>>6);`
93			`V_out=`
94			// `ABS(_X_in) > 32'hF800 ? 0:
95			`V0;// + ((V0<<(T_in[29:25])) & 32'hFFFF0000 );`
96			`end`
97			`end`
98
99			`//wire [31:0] V0= ((d_out-(T_in>>>14)) *20) ^((div_out>>>12)+(T_in>>>8));//((a_out[23:16]==Y_in[15:8])? -1:0);`
100
101			`wire [31:0] V0;`
102
103			`wire signed [31:0] T_sin;`
104			`PseudoSin ( clk, rst, ena, T_in>>>7, T_sin, _ );`
105
106
107			`Psin_Texture ( clk, rst, ena, T_in, ((d_out-(T_sin>>>7)-(T_in>>>13)) *20), ((div_out>>>12)+(T_sin)+(T_in>>>5)), V0 );`
108			`//Psin_Texture ( clk, rst, ena, T_in, ((d_out-(T_in>>>13)) *20), ((div_out>>>12)+(T_in>>>7)), V0 );`
109
110			`wire signed [31:0] s_out;`
111			`wire signed [31:0] a_out;`
112			`wire signed [31:0] a_outm;`
113			`wire signed [31:0] d_out;`
114			`wire signed [31:0] XX= ( (X_in) *(X_in) )>>12;`
115			`wire signed [31:0] YY= ( Y_in*Y_in)>>12;`
116			`wire signed [31:0] XXYY= XX+YY;`
117
118			`atan2_pipelined atan( clk, X_in, Y_in, a_out, _ );`
119
120			`defparam atan.IS_IBNIZ= 1;`
121			`//div_pipelined mydiv( clk, a_out<<12, pix2, d_out );`
122			`id_pipelined id( clk, a_out, d_out );`
123			`defparam id.DELAY= 16;`
124			`sqrt_pipelined sqrt1( clk, XXYY, s_out, _ );`
125
126			`wire signed [31:0] sin_a;`
127			`wire signed [31:0] cos_a;`
128			`wire signed [31:0] sin_q;`
129			`wire signed [31:0] div_out;`
130
131			`div_pipelined div1( clk, 48'h400000000000, XXYY, div_out );`
132			`defparam div1.BITS= 48;`
133
134			`endmodule`
135
136
137
138			`//============================= CIRCLES ===================================`
139			`//module Ibniz_generator7y ( clk, rst, ena, T_in, X_in, Y_in, V_out, dbg_out );`
140			`//`
141			`//input clk;`
142			`//input rst;`
143			`//input ena;`
144			`//input wire signed [31:0] T_in;`
145			`//input wire signed [35:0] X_in;`
146			`//input wire signed [35:0] Y_in;`
147			`//output reg [31:0] V_out;`
148			`//output reg signed [63:0] dbg_out;`
149			`//`
150			`//always@(posedge clk or posedge rst)`
151			`//begin`
152			`// if ( rst )`
153			`// begin`
154			`// end`
155			`// else if ( ena )`
156			`// begin`
157			`// // &*`
158			`// V_out= s_out*(T_in>>16);`
159			`// end`
160			`//end`
161			`//`
162			`//wire signed [31:0] s_out;`
163			`//wire signed [31:0] d_out;`
164			`//sqrt_pipelined sqrt1( clk, (X_inX_in+Y_inY_in)>>>16, s_out, d_out );`
165			`//`
166			`//wire signed [31:0] XXX = X_in<<16;`
167			`//wire signed [31:0] XXX2 = (X_in-16*128);`
168			`//wire signed [31:0] YYY = Y_in<<16;`
169			`//wire signed [31:0] YYY_p = (YYY-256);`
170			`//wire signed [31:0] g_out = (YYY==0 \|\| XXX==0 \|\| X_in==32'h8000 \|\| Y_in==(-32'h8000) ) ? -16'sh1 :`
171			`// ((YYY >= s_out /&& YYY_p<-s_out/) ? 32'h33338000 : 32'h0)`
172			`//// +( (YYY >= d_out /&& YYY_p<-d_out/) ? 32'hCC008000 : 32'h0)`
173			`//// +( (YYY >= -c_out && YYY_p<-c_out) ? 32'h88888000 : 32'h0)`
174			`// ;`
175			`//`
176			`//endmodule`
177
178			`//`
179

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[/] [pipelined_fixed_point_elementary_functions/] [trunk/] [ibniz/] [ibniz_units_old.v] - Blame information for rev 5