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[/] [plasma_fpu/] [trunk/] [test/] [scripts/] [plasma_memory.tcl] - Blame information for rev 2

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1 2 __alexs__
# --------------------------------------------------------------------------
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# >>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<
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# --------------------------------------------------------------------------
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# TITLE:       Plasma MEMORY ACCESS SCRIPT
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# AUTHOR:      Alex Schoenberger (Alex.Schoenberger@ies.tu-darmstadt.de)
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# COMMENT:     This project is based on Plasma CPU core by Steve Rhoads
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# www.ies.tu-darmstadt.de
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# TU Darmstadt
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# Institute for Integrated Systems
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# Merckstr. 25
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# 64283 Darmstadt - GERMANY
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# --------------------------------------------------------------------------
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# PROJECT:       Plasma CPU core with FPU
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# FILENAME:      plasma_memory.tcl
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# --------------------------------------------------------------------------
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# COPYRIGHT: 
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#  This project is distributed by GPLv2.0
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#  Software placed into the public domain by the author.
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#  Software 'as is' without warranty.  Author liable for nothing.
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# --------------------------------------------------------------------------
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# DESCRIPTION:
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#    read and write memory
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#
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# --------------------------------------------------------------------------
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# Revision History
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# --------------------------------------------------------------------------
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# Revision   Date    Author     CHANGES
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# 1.0      4/2014    AS         initial
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# --------------------------------------------------------------------------
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# #################################################################################################
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# _    ____ ____ ___     _  _ ____ _  _ ____ ____ _   _ 
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# |    |  | |__| |  \    |\/| |___ |\/| |  | |__/  \_/  
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# |___ |__| |  | |__/    |  | |___ |  | |__| |  \   |   
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#
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# write content of a extern file to memory
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#
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proc load_memory { } {
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  #
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  # generic memory model
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  #
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  mem load -infile memory_in.mem -format hex -filltype value -filldata 8'h00  /tb_plasma/u2_memory/ram
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}
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# #################################################################################################
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# ____ ___ ____ ____ ____    _  _ ____ _  _ ____ ____ _   _
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# [__   |  |  | |__/ |___    |\/| |___ |\/| |  | |__/  \_/
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# ___]  |  |__| |  \ |___    |  | |___ |  | |__| |  \   |
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#
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# write content of memory to extern file
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#
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proc store_memory { } {
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  # 0x8D_0000
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  set OUTPUT_START_ADDR      9240576
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  # 0x8D_0000 + 0xD_0000 = 0x9A_0000
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  set OUTPUT_END_ADDR       10092544
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  #
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  # generic memory model
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  #
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  mem save -format hex -wordsperline 32 -st $OUTPUT_START_ADDR -end $OUTPUT_END_ADDR -outfile memory_out.mem /tb_plasma/u2_memory/ram
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}
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# #################################################################################################
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# _ _  _ _ ___ _ ____ _    _ ____ ____ ___ _ ____ _  _
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# | |\ | |  |  | |__| |    | [__  |__|  |  | |  | |\ |
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# | | \| |  |  | |  | |___ | ___] |  |  |  | |__| | \|
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#
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# triggered on "init" signal
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#
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when { init = 1 } {
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  echo "Memory initialisation start"
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  load_memory
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  echo "Memory initialisation done"
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}
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# #################################################################################################
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# ____ _ _  _ _  _ _    ____ ___ _ ____ _  _    ____ _  _ _ ___
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# [__  | |\/| |  | |    |__|  |  | |  | |\ |    |___  \/  |  |
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# ___] | |  | |__| |___ |  |  |  | |__| | \|    |___ _/\_ |  |
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#
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when { sim_finish = 1 } {
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    stop
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    store_memory
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    exit -f
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}

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