URL
https://opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk
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feddischso |
Device_Family = virtex5
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Device = xc5vlx50
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Package = ff676
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Speedgrade = -2
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# Path to the vhdl and implementation directory
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PLB2WB_Bridge_VHDL_DIR = ../../systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/vhdl/
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PLB2WB_Bridge_NGC_DIR = ../../systems/EDK_Libs/WishboneIPLib/pcores/plb2wb_bridge_v1_00_a/hdl/ise/work/
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Address_Buffer_Size = 16 # valid values: 16, 32, ... 4194304
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Read_Buffer_Size = 16 # valid values: 16, 32, ... 4194304
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Write_Buffer_Size = 16 # valid values: 16, 32, ... 4194304
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Stat2WB_Buffer_Size = 16 # valid values: 16, 32, ... 4194304
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Stat2PLB_Buffer_Size = 16 # valid values: 16, 32, ... 4194304
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WB_Clk_Frequency = 66 # MHz
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PLB_Clk_Frequency = 100 # MHz
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################################
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# Do not change below unless
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# you know what you are doing
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Address_Buffer_minDWidth = 42 # 32 bit address, 4 bit BE, 4 bit size, 1 RNW, minimum 1 bit master-id
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Read_Buffer_DWidth = 33 # 32 bit datum and 1 bit error
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Write_Buffer_DWidth = 32
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Stat2PLB_Buffer_minDWidth = 100 # 32 bit address, 32 bit datum, 3 bit status info, 1-4 bit master-id, 32 bit irq-info
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Stat2WB_Buffer_DWidth = 1
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