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[/] [plb2wbbridge/] [trunk/] [systems/] [EDK_Libs/] [WishboneIPLib/] [pcores/] [testram_v1_00_a/] [hdl/] [vhdl/] [testram.vhd] - Blame information for rev 2

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----------------------------------------------------------------------
----                                                              ----
----  PLB2WB-Bridge                                               ----
----                                                              ----
----  This file is part of the PLB-to-WB-Bridge project           ----
----  http://opencores.org/project,plb2wbbridge                   ----
----                                                              ----
----  Description                                                 ----
----  Implementation of a PLB-to-WB-Bridge according to           ----
----  PLB-to-WB Bridge specification document.                    ----
----                                                              ----
----  To Do:                                                      ----
----   Nothing                                                    ----
----                                                              ----
----  Author(s):                                                  ----
----      - Christian Haettich                                    ----
----        feddischson@opencores.org                             ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2010 Authors                                   ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE.  See the GNU Lesser General Public License for more ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
 
use ieee.std_logic_textio.all;
use std.textio.all;
 
 
 
entity testram is
 
   generic(
      MEM_FILE_NAME     : string  := "onchip_ram.bin";
      WB_ADR_W          : integer := 32;
      WB_DAT_W          : integer := 32;
      RAM_ADR_W         : integer := 15;
 
      RD_DELAY          : natural := 1;
      WR_DELAY          : natural := 1;
      WITH_ERR_OR_RTY   : std_logic_vector( 1 downto 0 ) := "00";   -- "00" = none, "01" = err, "10" = rty", "11" = none
      ERR_RTY_INTERVAL  : integer := 0
   );
   port(
 
      wb_clk_i    : in  std_logic;
      wb_rst_i    : in  std_logic;
      wb_adr_i    : in  std_logic_vector( WB_ADR_W-1 downto 0 );
      wb_stb_i    : in  std_logic;
      wb_cyc_i    : in  std_logic;
      wb_we_i     : in  std_logic;
      wb_sel_i    : in  std_logic_vector( (WB_ADR_W/8)-1 downto 0 );
      wb_dat_i    : in  std_logic_vector( WB_DAT_W-1 downto 0 );
      wb_dat_o    : out std_logic_vector( WB_DAT_W-1 downto 0 );
      wb_ack_o    : out std_logic;
      wb_err_o    : out std_logic;
      wb_rty_o    : out std_logic
   );
 
end entity testram;
 
 
 
architecture IMP of testram is
 
   type ram_type is array( integer range <> ) of std_logic_vector( WB_DAT_W-1 downto 0 );
 
   procedure load_ram(signal data_word : inout ram_type ) is
--    file ram_file  : text open read_mode is MEM_FILE_NAME;
 
      type CHRF is file of character;
      file char_file : CHRF;
 
 
      variable cbuf        : character;
      variable lbuf        : line;
      variable byte_index  : integer := 0;
      variable line_index  : integer := 0;
      variable data  : std_logic_vector( WB_DAT_W-1 downto 0 );
   begin
      file_open( char_file, MEM_FILE_NAME, read_mode );
 
 
 
 
      while not endfile( char_file ) and line_index < ( 2**RAM_ADR_W ) loop
 
         for i in 0 to ( WB_DAT_W/8)-1 loop
            read( char_file, cbuf );
            data_word( line_index )( (i+1)*8-1 downto i*8 ) <= std_logic_vector( to_unsigned( character'pos(cbuf), 8 ) );
            if endfile( char_file ) then
               exit;
            end if;
         end loop;
         line_index := line_index+1;
 
      end loop;
 
      while line_index < (2**RAM_ADR_W) loop
         data_word( line_index ) <= (others => '0' );
         line_index := line_index + 1;
      end loop;
 
 
   end procedure;
 
 
 
   function log_2( x : positive ) return natural is
 
   begin
      if x <= 1 then
         return 0;
      else
         return 1 + log_2( x/2 );
      end if;
 
   end function;
 
 
   --
   --  Returns the maximum of x and y. If x and y are less than 2, 2 is returned.
   --
   function get_delay_count_vsize( x,y : natural ) return positive is
      variable temp : natural;
   begin
      if x > y then
         temp := x;
      else
         temp := y;
      end if;
 
      if temp < 2 then
         temp := 2;
      end if;
      return temp;
   end function;
 
 
 
   function vec_size ( x : natural ) return natural is
      variable temp, i : natural;
   begin
 
      temp := 0;
      i    := 0;
      while temp <= x loop
         i     := i + 1;
         temp  := 2**i;
      end loop;
      return i;
 
   end function vec_size;
 
 
   constant test_a : natural := vec_size( RD_DELAY );
   constant test_b : natural := vec_size( WR_DELAY );
 
   constant DELAY_COUNT_SIZE  : natural := get_delay_count_vsize( vec_size( RD_DELAY ), vec_size( WR_DELAY ) );
   constant DELAY_COUNT_ZERO  : std_logic_vector( DELAY_COUNT_SIZE-1 downto 0 ) := ( others => '0' );
 
 
   constant ERR_RTY_COUNT_SIZE : natural := vec_size( ERR_RTY_INTERVAL );
   constant ERR_RTY_COUNT_ZERO : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 ) := ( others => '0' );
 
   --
   -- RAM_ADR_LB (low bit) and RAM_ADR_HB (high bit):
   -- => used select the address lines, which we use to address the ram
   --
   --   eg. WB_ADR_W = 64 and RAM_ADR_W = 5:
   --   
   --    We don't want to use the lower 3 bit, because one ram-line contains 8 byte
   --    RAM_ADR_LB = 3
   --    RAM_ADR_HB = 7
   --
   --       ==>> 7 downto 3  = 5 address line, which address 2**5 * 8 byte = 32 * 8 byte
   --
   constant RAM_ADR_LB        : integer := log_2( WB_ADR_W/8);
   constant RAM_ADR_HB        : integer := RAM_ADR_LB + RAM_ADR_W - 1;
 
 
   signal ram              : ram_type(2**RAM_ADR_W -1 downto 0);
   signal w_ack, r_ack     : std_logic                                              := '0';
   signal w_err, r_err     : std_logic                                              := '0';
   signal w_rty, r_rty     : std_logic                                              := '0';
   signal r_delay_count    : std_logic_vector( DELAY_COUNT_SIZE -1 downto 0 )       := ( others => '0' );
   signal w_delay_count    : std_logic_vector( DELAY_COUNT_SIZE -1 downto 0 )       := ( others => '0' );
   signal ram_adr          : std_logic_vector( RAM_ADR_W-1 downto 0 )               := ( others => '0' );
   signal ram_line         : std_logic_vector( WB_DAT_W-1 downto 0 )                := ( others => '0' );
 
   signal   err_rty_count_r   : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 );
   signal   err_rty_count_w   : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 );
   constant err_rty_zero      : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 ) := ( others => '0' );
 
 
 
begin
 
 
   with wb_rst_i select
      ram_adr <= wb_adr_i( RAM_ADR_HB downto RAM_ADR_LB )   when '0',
               ( others => '0' )                            when others;
 
   gen_read_ack1 : if RD_DELAY > 1 generate
 
            -- generate read ack after a delay
            read_ack_p1 : process( wb_clk_i, wb_rst_i ) begin
               if wb_rst_i = '1' then
 
                  r_rty <= '0';
                  r_ack <= '0';
                  r_err <= '0';
                  r_delay_count     <= std_logic_vector( to_unsigned( RD_DELAY, DELAY_COUNT_SIZE ) );
                  err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
 
               elsif wb_clk_i'event and wb_clk_i = '1' then
 
                  r_delay_count <= std_logic_vector( to_unsigned( RD_DELAY, DELAY_COUNT_SIZE ) );
 
                  if wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0'
                     and  not ( r_ack = '1' or r_rty = '1' or r_err = '1' ) then
 
                     r_delay_count     <= r_delay_count -1;
 
                     if r_delay_count = DELAY_COUNT_ZERO then
 
                        r_delay_count     <= std_logic_vector( to_unsigned( RD_DELAY, DELAY_COUNT_SIZE ) );
                        if err_rty_count_r = ERR_RTY_COUNT_ZERO then
                           err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
                        else
                           err_rty_count_r <= err_rty_count_r - 1;
                        end if;
                     end if;
                  end if;
 
 
 
                  if r_delay_count = DELAY_COUNT_ZERO and wb_cyc_i = '1' and wb_stb_i = '1' then
                     err_rty_count_r <= err_rty_count_r - 1;
 
                     if ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
                        r_rty <= '1';
                        r_ack <= '0';
                        r_err <= '0';
                     elsif ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
                        r_rty <= '0';
                        r_ack <= '0';
                        r_err <= '1';
                     else
                        r_rty <= '0';
                        r_ack <= '1';
                        r_err <= '0';
                     end if;
 
                  else
                     r_rty <= '0';
                     r_ack <= '0';
                     r_err <= '0';
                  end if;
 
               end if;
            end process;
 
   end generate;
 
   gen_read_ack2 : if RD_DELAY = 1 generate
 
            -- generate read ack after a delay
            read_ack_p2 : process( wb_clk_i, wb_rst_i ) begin
 
               if wb_rst_i = '1' then
 
                  r_ack             <= '0';
                  r_err             <= '0';
                  r_rty             <= '0';
                  err_rty_count_r   <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
 
               elsif wb_clk_i'event and wb_clk_i = '1' then
 
                  if ( wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0'
                        and not (r_ack = '1' or r_rty = '1' or r_err = '1' ) ) then
 
                     if err_rty_count_r = ERR_RTY_COUNT_ZERO then
                        err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
                     else
                        err_rty_count_r <= err_rty_count_r - 1;
                     end if;
 
                     if ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
                        r_rty <= '1';
                        r_ack <= '0';
                        r_err <= '0';
                     elsif ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
                        r_rty <= '0';
                        r_ack <= '0';
                        r_err <= '1';
                     else
                        r_rty <= '0';
                        r_ack <= '1';
                        r_err <= '0';
                     end if;
 
                  else
                     r_ack <= '0';
                     r_err <= '0';
                     r_rty <= '0';
                  end if;
 
               end if;
 
            end process;
 
   end generate;
 
 
 
   gen_read_ack3 : if RD_DELAY = 0 generate
 
         read_ack_p3 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, err_rty_count_r ) begin
            if wb_rst_i = '1' then
               err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
            elsif wb_clk_i'event and wb_clk_i = '1' then
               if ( wb_cyc_i = '1' and wb_stb_i = '1'  and wb_we_i = '0' ) then
                  if err_rty_count_r = ERR_RTY_COUNT_ZERO then
                     err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
                  else
                     err_rty_count_r <= err_rty_count_r - 1;
                  end if;
               end if;
            end if;
 
            r_err <= '0';
            r_rty <= '0';
            r_ack <= '0';
 
            if ( wb_cyc_i = '1' and wb_stb_i = '1'  and wb_we_i = '0' ) then
 
               if ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
                  r_rty <= '1';
               elsif ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
                  r_err <= '1';
               else
                  r_ack <= '1';
               end if;
 
            end if;
 
 
 
         end process;
 
 
   end generate;
 
 
 
   gen_write_ack1 : if WR_DELAY > 1 generate
 
            -- generate write ack after a delay
            -- and write byte-wise data to ram, depending on select
            write_ack_p1 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, w_ack ) begin
 
               if wb_rst_i = '1' then
                  load_ram( ram );
                  w_err <= '0';
                  w_rty <= '0';
                  w_ack <= '0';
                  w_delay_count     <= std_logic_vector( to_unsigned( WR_DELAY, DELAY_COUNT_SIZE )             );
                  err_rty_count_w   <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE )   );
 
               elsif wb_clk_i'event and wb_clk_i = '1' then
 
                  w_delay_count <= std_logic_vector( to_unsigned( WR_DELAY, DELAY_COUNT_SIZE ) );
 
                  if wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1'
                     and not ( w_ack = '1' or w_err = '1' or w_rty = '1' ) then
                     w_delay_count <= w_delay_count -1;
 
                     if w_delay_count = DELAY_COUNT_ZERO then
                        w_delay_count <= std_logic_vector( to_unsigned( WR_DELAY, DELAY_COUNT_SIZE ) );
                        if err_rty_count_w = ERR_RTY_COUNT_ZERO then
                           err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
                        else
                           err_rty_count_w <= err_rty_count_w - 1;
                        end if;
                     end if;
                  end if;
 
                  if w_delay_count = DELAY_COUNT_ZERO and wb_cyc_i = '1' and wb_stb_i = '1' then
 
                     err_rty_count_w <= err_rty_count_w - 1;
 
                     if ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
                        w_err <= '0';
                        w_rty <= '1';
                        w_ack <= '0';
                     elsif ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
                        w_err <= '1';
                        w_rty <= '0';
                        w_ack <= '0';
                     else
                        w_err <= '0';
                        w_rty <= '0';
                        w_ack <= '1';
                        for i in 0 to ( WB_DAT_W/8)-1 loop
                           if ( wb_sel_i(i) = '1' ) then
                              ram( conv_integer( ram_adr ) )( (i+1)*8-1 downto i*8 ) <= wb_dat_i( (i+1)*8-1 downto i*8 );
                           end if;
                        end loop;
                     end if;
 
                  else
                     w_err <= '0';
                     w_rty <= '0';
                     w_ack <= '0';
                  end if;
 
               end if;
            end process;
 
   end generate;
 
 
   gen_write_ack2 : if WR_DELAY = 1 generate
 
            -- generate write ack after a delay
            -- and write byte-wise data to ram, depending on select
            write_ack_p2 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, w_ack, w_err, w_rty ) begin
 
               if wb_rst_i = '1' then
 
                  load_ram( ram );
                  err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
                  w_err <= '0';
                  w_rty <= '0';
                  w_ack <= '0';
 
               elsif wb_clk_i'event and wb_clk_i = '1' then
 
                  if wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1'
                     and not ( w_ack = '1' or w_err = '1' or w_rty = '1' ) then
 
                     if err_rty_count_w = ERR_RTY_COUNT_ZERO then
                        err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
                     else
                        err_rty_count_w <= err_rty_count_w - 1;
                     end if;
 
 
 
                     if ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
                        w_err <= '0';
                        w_rty <= '1';
                        w_ack <= '0';
                     elsif ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
                        w_err <= '1';
                        w_rty <= '0';
                        w_ack <= '0';
                     else
                        w_err <= '0';
                        w_rty <= '0';
                        w_ack <= '1';
                        for i in 0 to ( WB_DAT_W/8)-1 loop
                           if ( wb_sel_i(i) = '1' ) then
                              ram( conv_integer( ram_adr ) )( (i+1)*8-1 downto i*8 ) <= wb_dat_i( (i+1)*8-1 downto i*8 );
                           end if;
                        end loop;
                     end if;
                  else
                     w_err <= '0';
                     w_rty <= '0';
                     w_ack <= '0';
                  end if;
 
               end if;
 
 
 
 
            end process;
 
   end generate;
 
 
 
   gen_write_ack3 : if WR_DELAY = 0 generate
 
 
            write_ack_p3 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, err_rty_count_w ) begin
 
               if wb_rst_i = '1' then
                  load_ram( ram );
                  err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
               elsif wb_clk_i = '1' and wb_clk_i'event then
 
                  if w_ack = '1' or w_rty = '1' or w_err = '1' then
                     if err_rty_count_w = ERR_RTY_COUNT_ZERO then
                        err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );
                     else
                        err_rty_count_w <= err_rty_count_w - 1;
                     end if;
                  end if;
 
                  if w_ack = '1' then
 
                     for i in 0 to ( WB_DAT_W/8)-1 loop
                        if ( wb_sel_i(i) = '1' ) then
                           ram( conv_integer( ram_adr ) )( (i+1)*8-1 downto i*8 ) <= wb_dat_i( (i+1)*8-1 downto i*8 );
                        end if;
                     end loop;
                  end if;
               end if;
 
 
               w_err <= '0';
               w_rty <= '0';
               w_ack <= '0';
 
 
               if ( wb_cyc_i = '1' and wb_stb_i = '1'  and wb_we_i = '1' ) then
 
                  if ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then
                     w_rty <= '1';
                  elsif ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then
                     w_err <= '1';
                  else
                     w_ack <= '1';
                  end if;
 
               end if;
 
 
 
 
            end process;
 
   end generate;
 
 
 
   -- assign byte-wise ram output, depending on select line
   ram_line <= ram( conv_integer( ram_adr ) );
   output_loop : for i in 0 to WB_DAT_W/8-1 generate
      with wb_sel_i( i ) select
         wb_dat_o( (i+1)*8-1 downto i*8 ) <= ram_line( (i+1)*8-1 downto i*8 ) when '1',
                                                                  "00000000"  when others;
   end generate;
 
 
 
   wb_ack_o <= w_ack or r_ack;
   wb_err_o <= w_err or r_err;
   wb_rty_o <= w_rty or r_rty;
 
 
 
end architecture IMP;

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Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [EDK_Libs/] [WishboneIPLib/] [pcores/] [testram_v1_00_a/] [hdl/] [vhdl/] [testram.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	feddischso	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- PLB2WB-Bridge ----`
4			`---- ----`
5			`---- This file is part of the PLB-to-WB-Bridge project ----`
6			`---- http://opencores.org/project,plb2wbbridge ----`
7			`---- ----`
8			`---- Description ----`
9			`---- Implementation of a PLB-to-WB-Bridge according to ----`
10			`---- PLB-to-WB Bridge specification document. ----`
11			`---- ----`
12			`---- To Do: ----`
13			`---- Nothing ----`
14			`---- ----`
15			`---- Author(s): ----`
16			`---- - Christian Haettich ----`
17			`---- feddischson@opencores.org ----`
18			`---- ----`
19			`----------------------------------------------------------------------`
20			`---- ----`
21			`---- Copyright (C) 2010 Authors ----`
22			`---- ----`
23			`---- This source file may be used and distributed without ----`
24			`---- restriction provided that this copyright statement is not ----`
25			`---- removed from the file and that any derivative work contains ----`
26			`---- the original copyright notice and the associated disclaimer. ----`
27			`---- ----`
28			`---- This source file is free software; you can redistribute it ----`
29			`---- and/or modify it under the terms of the GNU Lesser General ----`
30			`---- Public License as published by the Free Software Foundation; ----`
31			`---- either version 2.1 of the License, or (at your option) any ----`
32			`---- later version. ----`
33			`---- ----`
34			`---- This source is distributed in the hope that it will be ----`
35			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
36			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
37			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
38			`---- details. ----`
39			`---- ----`
40			`---- You should have received a copy of the GNU Lesser General ----`
41			`---- Public License along with this source; if not, download it ----`
42			`---- from http://www.opencores.org/lgpl.shtml ----`
43			`---- ----`
44			`----------------------------------------------------------------------`
45
46			`library ieee;`
47			`use ieee.std_logic_1164.all;`
48			`use ieee.std_logic_unsigned.all;`
49			`use ieee.numeric_std.all;`
50
51
52			`use ieee.std_logic_textio.all;`
53			`use std.textio.all;`
54
55
56
57			`entity testram is`
58
59			`generic(`
60			`MEM_FILE_NAME : string := "onchip_ram.bin";`
61			`WB_ADR_W : integer := 32;`
62			`WB_DAT_W : integer := 32;`
63			`RAM_ADR_W : integer := 15;`
64
65			`RD_DELAY : natural := 1;`
66			`WR_DELAY : natural := 1;`
67			`WITH_ERR_OR_RTY : std_logic_vector( 1 downto 0 ) := "00"; -- "00" = none, "01" = err, "10" = rty", "11" = none`
68			`ERR_RTY_INTERVAL : integer := 0`
69			`);`
70			`port(`
71
72			`wb_clk_i : in std_logic;`
73			`wb_rst_i : in std_logic;`
74			`wb_adr_i : in std_logic_vector( WB_ADR_W-1 downto 0 );`
75			`wb_stb_i : in std_logic;`
76			`wb_cyc_i : in std_logic;`
77			`wb_we_i : in std_logic;`
78			`wb_sel_i : in std_logic_vector( (WB_ADR_W/8)-1 downto 0 );`
79			`wb_dat_i : in std_logic_vector( WB_DAT_W-1 downto 0 );`
80			`wb_dat_o : out std_logic_vector( WB_DAT_W-1 downto 0 );`
81			`wb_ack_o : out std_logic;`
82			`wb_err_o : out std_logic;`
83			`wb_rty_o : out std_logic`
84			`);`
85
86			`end entity testram;`
87
88
89
90			`architecture IMP of testram is`
91
92			`type ram_type is array( integer range <> ) of std_logic_vector( WB_DAT_W-1 downto 0 );`
93
94			`procedure load_ram(signal data_word : inout ram_type ) is`
95			`-- file ram_file : text open read_mode is MEM_FILE_NAME;`
96
97			`type CHRF is file of character;`
98			`file char_file : CHRF;`
99
100
101			`variable cbuf : character;`
102			`variable lbuf : line;`
103			`variable byte_index : integer := 0;`
104			`variable line_index : integer := 0;`
105			`variable data : std_logic_vector( WB_DAT_W-1 downto 0 );`
106			`begin`
107			`file_open( char_file, MEM_FILE_NAME, read_mode );`
108
109
110
111
112			`while not endfile( char_file ) and line_index < ( 2**RAM_ADR_W ) loop`
113
114			`for i in 0 to ( WB_DAT_W/8)-1 loop`
115			`read( char_file, cbuf );`
116			`data_word( line_index )( (i+1)8-1 downto i8 ) <= std_logic_vector( to_unsigned( character'pos(cbuf), 8 ) );`
117			`if endfile( char_file ) then`
118			`exit;`
119			`end if;`
120			`end loop;`
121			`line_index := line_index+1;`
122
123			`end loop;`
124
125			`while line_index < (2**RAM_ADR_W) loop`
126			`data_word( line_index ) <= (others => '0' );`
127			`line_index := line_index + 1;`
128			`end loop;`
129
130
131			`end procedure;`
132
133
134
135			`function log_2( x : positive ) return natural is`
136
137			`begin`
138			`if x <= 1 then`
139			`return 0;`
140			`else`
141			`return 1 + log_2( x/2 );`
142			`end if;`
143
144			`end function;`
145
146
147			`--`
148			`-- Returns the maximum of x and y. If x and y are less than 2, 2 is returned.`
149			`--`
150			`function get_delay_count_vsize( x,y : natural ) return positive is`
151			`variable temp : natural;`
152			`begin`
153			`if x > y then`
154			`temp := x;`
155			`else`
156			`temp := y;`
157			`end if;`
158
159			`if temp < 2 then`
160			`temp := 2;`
161			`end if;`
162			`return temp;`
163			`end function;`
164
165
166
167			`function vec_size ( x : natural ) return natural is`
168			`variable temp, i : natural;`
169			`begin`
170
171			`temp := 0;`
172			`i := 0;`
173			`while temp <= x loop`
174			`i := i + 1;`
175			`temp := 2**i;`
176			`end loop;`
177			`return i;`
178
179			`end function vec_size;`
180
181
182			`constant test_a : natural := vec_size( RD_DELAY );`
183			`constant test_b : natural := vec_size( WR_DELAY );`
184
185			`constant DELAY_COUNT_SIZE : natural := get_delay_count_vsize( vec_size( RD_DELAY ), vec_size( WR_DELAY ) );`
186			`constant DELAY_COUNT_ZERO : std_logic_vector( DELAY_COUNT_SIZE-1 downto 0 ) := ( others => '0' );`
187
188
189			`constant ERR_RTY_COUNT_SIZE : natural := vec_size( ERR_RTY_INTERVAL );`
190			`constant ERR_RTY_COUNT_ZERO : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 ) := ( others => '0' );`
191
192			`--`
193			`-- RAM_ADR_LB (low bit) and RAM_ADR_HB (high bit):`
194			`-- => used select the address lines, which we use to address the ram`
195			`--`
196			`-- eg. WB_ADR_W = 64 and RAM_ADR_W = 5:`
197			`--`
198			`-- We don't want to use the lower 3 bit, because one ram-line contains 8 byte`
199			`-- RAM_ADR_LB = 3`
200			`-- RAM_ADR_HB = 7`
201			`--`
202			`-- ==>> 7 downto 3 = 5 address line, which address 2*5 8 byte = 32 * 8 byte`
203			`--`
204			`constant RAM_ADR_LB : integer := log_2( WB_ADR_W/8);`
205			`constant RAM_ADR_HB : integer := RAM_ADR_LB + RAM_ADR_W - 1;`
206
207
208			`signal ram : ram_type(2**RAM_ADR_W -1 downto 0);`
209			`signal w_ack, r_ack : std_logic := '0';`
210			`signal w_err, r_err : std_logic := '0';`
211			`signal w_rty, r_rty : std_logic := '0';`
212			`signal r_delay_count : std_logic_vector( DELAY_COUNT_SIZE -1 downto 0 ) := ( others => '0' );`
213			`signal w_delay_count : std_logic_vector( DELAY_COUNT_SIZE -1 downto 0 ) := ( others => '0' );`
214			`signal ram_adr : std_logic_vector( RAM_ADR_W-1 downto 0 ) := ( others => '0' );`
215			`signal ram_line : std_logic_vector( WB_DAT_W-1 downto 0 ) := ( others => '0' );`
216
217			`signal err_rty_count_r : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 );`
218			`signal err_rty_count_w : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 );`
219			`constant err_rty_zero : std_logic_vector( ERR_RTY_COUNT_SIZE-1 downto 0 ) := ( others => '0' );`
220
221
222
223			`begin`
224
225
226			`with wb_rst_i select`
227			`ram_adr <= wb_adr_i( RAM_ADR_HB downto RAM_ADR_LB ) when '0',`
228			`( others => '0' ) when others;`
229
230			`gen_read_ack1 : if RD_DELAY > 1 generate`
231
232			`-- generate read ack after a delay`
233			`read_ack_p1 : process( wb_clk_i, wb_rst_i ) begin`
234			`if wb_rst_i = '1' then`
235
236			`r_rty <= '0';`
237			`r_ack <= '0';`
238			`r_err <= '0';`
239			`r_delay_count <= std_logic_vector( to_unsigned( RD_DELAY, DELAY_COUNT_SIZE ) );`
240			`err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
241
242			`elsif wb_clk_i'event and wb_clk_i = '1' then`
243
244			`r_delay_count <= std_logic_vector( to_unsigned( RD_DELAY, DELAY_COUNT_SIZE ) );`
245
246			`if wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0'`
247			`and not ( r_ack = '1' or r_rty = '1' or r_err = '1' ) then`
248
249			`r_delay_count <= r_delay_count -1;`
250
251			`if r_delay_count = DELAY_COUNT_ZERO then`
252
253			`r_delay_count <= std_logic_vector( to_unsigned( RD_DELAY, DELAY_COUNT_SIZE ) );`
254			`if err_rty_count_r = ERR_RTY_COUNT_ZERO then`
255			`err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
256			`else`
257			`err_rty_count_r <= err_rty_count_r - 1;`
258			`end if;`
259			`end if;`
260			`end if;`
261
262
263
264			`if r_delay_count = DELAY_COUNT_ZERO and wb_cyc_i = '1' and wb_stb_i = '1' then`
265			`err_rty_count_r <= err_rty_count_r - 1;`
266
267			`if ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then`
268			`r_rty <= '1';`
269			`r_ack <= '0';`
270			`r_err <= '0';`
271			`elsif ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then`
272			`r_rty <= '0';`
273			`r_ack <= '0';`
274			`r_err <= '1';`
275			`else`
276			`r_rty <= '0';`
277			`r_ack <= '1';`
278			`r_err <= '0';`
279			`end if;`
280
281			`else`
282			`r_rty <= '0';`
283			`r_ack <= '0';`
284			`r_err <= '0';`
285			`end if;`
286
287			`end if;`
288			`end process;`
289
290			`end generate;`
291
292			`gen_read_ack2 : if RD_DELAY = 1 generate`
293
294			`-- generate read ack after a delay`
295			`read_ack_p2 : process( wb_clk_i, wb_rst_i ) begin`
296
297			`if wb_rst_i = '1' then`
298
299			`r_ack <= '0';`
300			`r_err <= '0';`
301			`r_rty <= '0';`
302			`err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
303
304			`elsif wb_clk_i'event and wb_clk_i = '1' then`
305
306			`if ( wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0'`
307			`and not (r_ack = '1' or r_rty = '1' or r_err = '1' ) ) then`
308
309			`if err_rty_count_r = ERR_RTY_COUNT_ZERO then`
310			`err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
311			`else`
312			`err_rty_count_r <= err_rty_count_r - 1;`
313			`end if;`
314
315			`if ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then`
316			`r_rty <= '1';`
317			`r_ack <= '0';`
318			`r_err <= '0';`
319			`elsif ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then`
320			`r_rty <= '0';`
321			`r_ack <= '0';`
322			`r_err <= '1';`
323			`else`
324			`r_rty <= '0';`
325			`r_ack <= '1';`
326			`r_err <= '0';`
327			`end if;`
328
329			`else`
330			`r_ack <= '0';`
331			`r_err <= '0';`
332			`r_rty <= '0';`
333			`end if;`
334
335			`end if;`
336
337			`end process;`
338
339			`end generate;`
340
341
342
343			`gen_read_ack3 : if RD_DELAY = 0 generate`
344
345			`read_ack_p3 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, err_rty_count_r ) begin`
346			`if wb_rst_i = '1' then`
347			`err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
348			`elsif wb_clk_i'event and wb_clk_i = '1' then`
349			`if ( wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0' ) then`
350			`if err_rty_count_r = ERR_RTY_COUNT_ZERO then`
351			`err_rty_count_r <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
352			`else`
353			`err_rty_count_r <= err_rty_count_r - 1;`
354			`end if;`
355			`end if;`
356			`end if;`
357
358			`r_err <= '0';`
359			`r_rty <= '0';`
360			`r_ack <= '0';`
361
362			`if ( wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0' ) then`
363
364			`if ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then`
365			`r_rty <= '1';`
366			`elsif ( err_rty_count_r = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then`
367			`r_err <= '1';`
368			`else`
369			`r_ack <= '1';`
370			`end if;`
371
372			`end if;`
373
374
375
376			`end process;`
377
378
379			`end generate;`
380
381
382
383			`gen_write_ack1 : if WR_DELAY > 1 generate`
384
385			`-- generate write ack after a delay`
386			`-- and write byte-wise data to ram, depending on select`
387			`write_ack_p1 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, w_ack ) begin`
388
389			`if wb_rst_i = '1' then`
390			`load_ram( ram );`
391			`w_err <= '0';`
392			`w_rty <= '0';`
393			`w_ack <= '0';`
394			`w_delay_count <= std_logic_vector( to_unsigned( WR_DELAY, DELAY_COUNT_SIZE ) );`
395			`err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
396
397			`elsif wb_clk_i'event and wb_clk_i = '1' then`
398
399			`w_delay_count <= std_logic_vector( to_unsigned( WR_DELAY, DELAY_COUNT_SIZE ) );`
400
401			`if wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1'`
402			`and not ( w_ack = '1' or w_err = '1' or w_rty = '1' ) then`
403			`w_delay_count <= w_delay_count -1;`
404
405			`if w_delay_count = DELAY_COUNT_ZERO then`
406			`w_delay_count <= std_logic_vector( to_unsigned( WR_DELAY, DELAY_COUNT_SIZE ) );`
407			`if err_rty_count_w = ERR_RTY_COUNT_ZERO then`
408			`err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
409			`else`
410			`err_rty_count_w <= err_rty_count_w - 1;`
411			`end if;`
412			`end if;`
413			`end if;`
414
415			`if w_delay_count = DELAY_COUNT_ZERO and wb_cyc_i = '1' and wb_stb_i = '1' then`
416
417			`err_rty_count_w <= err_rty_count_w - 1;`
418
419			`if ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then`
420			`w_err <= '0';`
421			`w_rty <= '1';`
422			`w_ack <= '0';`
423			`elsif ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then`
424			`w_err <= '1';`
425			`w_rty <= '0';`
426			`w_ack <= '0';`
427			`else`
428			`w_err <= '0';`
429			`w_rty <= '0';`
430			`w_ack <= '1';`
431			`for i in 0 to ( WB_DAT_W/8)-1 loop`
432			`if ( wb_sel_i(i) = '1' ) then`
433			`ram( conv_integer( ram_adr ) )( (i+1)8-1 downto i8 ) <= wb_dat_i( (i+1)8-1 downto i8 );`
434			`end if;`
435			`end loop;`
436			`end if;`
437
438			`else`
439			`w_err <= '0';`
440			`w_rty <= '0';`
441			`w_ack <= '0';`
442			`end if;`
443
444			`end if;`
445			`end process;`
446
447			`end generate;`
448
449
450			`gen_write_ack2 : if WR_DELAY = 1 generate`
451
452			`-- generate write ack after a delay`
453			`-- and write byte-wise data to ram, depending on select`
454			`write_ack_p2 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, w_ack, w_err, w_rty ) begin`
455
456			`if wb_rst_i = '1' then`
457
458			`load_ram( ram );`
459			`err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
460			`w_err <= '0';`
461			`w_rty <= '0';`
462			`w_ack <= '0';`
463
464			`elsif wb_clk_i'event and wb_clk_i = '1' then`
465
466			`if wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1'`
467			`and not ( w_ack = '1' or w_err = '1' or w_rty = '1' ) then`
468
469			`if err_rty_count_w = ERR_RTY_COUNT_ZERO then`
470			`err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
471			`else`
472			`err_rty_count_w <= err_rty_count_w - 1;`
473			`end if;`
474
475
476
477			`if ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then`
478			`w_err <= '0';`
479			`w_rty <= '1';`
480			`w_ack <= '0';`
481			`elsif ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then`
482			`w_err <= '1';`
483			`w_rty <= '0';`
484			`w_ack <= '0';`
485			`else`
486			`w_err <= '0';`
487			`w_rty <= '0';`
488			`w_ack <= '1';`
489			`for i in 0 to ( WB_DAT_W/8)-1 loop`
490			`if ( wb_sel_i(i) = '1' ) then`
491			`ram( conv_integer( ram_adr ) )( (i+1)8-1 downto i8 ) <= wb_dat_i( (i+1)8-1 downto i8 );`
492			`end if;`
493			`end loop;`
494			`end if;`
495			`else`
496			`w_err <= '0';`
497			`w_rty <= '0';`
498			`w_ack <= '0';`
499			`end if;`
500
501			`end if;`
502
503
504
505
506			`end process;`
507
508			`end generate;`
509
510
511
512			`gen_write_ack3 : if WR_DELAY = 0 generate`
513
514
515			`write_ack_p3 : process( wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, err_rty_count_w ) begin`
516
517			`if wb_rst_i = '1' then`
518			`load_ram( ram );`
519			`err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
520			`elsif wb_clk_i = '1' and wb_clk_i'event then`
521
522			`if w_ack = '1' or w_rty = '1' or w_err = '1' then`
523			`if err_rty_count_w = ERR_RTY_COUNT_ZERO then`
524			`err_rty_count_w <= std_logic_vector( to_unsigned( ERR_RTY_INTERVAL, ERR_RTY_COUNT_SIZE ) );`
525			`else`
526			`err_rty_count_w <= err_rty_count_w - 1;`
527			`end if;`
528			`end if;`
529
530			`if w_ack = '1' then`
531
532			`for i in 0 to ( WB_DAT_W/8)-1 loop`
533			`if ( wb_sel_i(i) = '1' ) then`
534			`ram( conv_integer( ram_adr ) )( (i+1)8-1 downto i8 ) <= wb_dat_i( (i+1)8-1 downto i8 );`
535			`end if;`
536			`end loop;`
537			`end if;`
538			`end if;`
539
540
541			`w_err <= '0';`
542			`w_rty <= '0';`
543			`w_ack <= '0';`
544
545
546			`if ( wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1' ) then`
547
548			`if ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "10" ) then`
549			`w_rty <= '1';`
550			`elsif ( err_rty_count_w = err_rty_zero and WITH_ERR_OR_RTY = "01" ) then`
551			`w_err <= '1';`
552			`else`
553			`w_ack <= '1';`
554			`end if;`
555
556			`end if;`
557
558
559
560
561			`end process;`
562
563			`end generate;`
564
565
566
567			`-- assign byte-wise ram output, depending on select line`
568			`ram_line <= ram( conv_integer( ram_adr ) );`
569			`output_loop : for i in 0 to WB_DAT_W/8-1 generate`
570			`with wb_sel_i( i ) select`
571			`wb_dat_o( (i+1)8-1 downto i8 ) <= ram_line( (i+1)8-1 downto i8 ) when '1',`
572			`"00000000" when others;`
573			`end generate;`
574
575
576
577			`wb_ack_o <= w_ack or r_ack;`
578			`wb_err_o <= w_err or r_err;`
579			`wb_rty_o <= w_rty or r_rty;`
580
581
582
583			`end architecture IMP;`