OpenCores
URL https://opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk

Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [32bit_on_128bitPLB_asyn/] [simulation/] [test_cases/] [simple_burst_rw/] [transfers.bfl] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 feddischso
 
2
 set_alias(PART         = 1)
3
 set_alias(SUBPART      = 2)
4
 set_alias(SUBSUBPART   = 3)
5
 
6
 
7
 ---------------------------------
8
 --  32-Bit Master              --
9
 
10
 set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)
11
 configure(msize=00)
12
 
13
 mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
14
 mem_update(addr=f0000010,data=01111100_02111100_03111100_04111100)
15
 mem_update(addr=f0000020,data=01222200_02222200_03222200_04222200)
16
 mem_update(addr=f0000030,data=01333300_02333300_03333300_04333300)
17
 
18
 mem_update(addr=f1000000,data=01000011_02000011_03000011_04000011)
19
 mem_update(addr=f1000010,data=01111111_02111111_03111111_04111111)
20
 mem_update(addr=f1000020,data=01222211_02222211_03222211_04222211)
21
 mem_update(addr=f1000030,data=01333311_02333311_03333311_04333311)
22
 
23
-- mem_update(addr=f2000000,data=01000022_02000022_03000022_04000022)
24
-- mem_update(addr=f2000010,data=01111122_02111122_03111122_04111122)
25
-- mem_update(addr=f2000020,data=01222222_02222222_03222222_04222222)
26
-- mem_update(addr=f2000030,data=01333322_02333322_03333322_04333322)
27
--
28
-- mem_update(addr=f3000000,data=01000033_02000033_03000033_04000033)
29
-- mem_update(addr=f3000010,data=01111133_02111133_03111133_04111133)
30
-- mem_update(addr=f3000020,data=01222233_02222233_03222233_04222233)
31
-- mem_update(addr=f3000030,data=01333333_02333333_03333333_04333333)
32
 
33
 
34
 
35
 wait( level=PART )
36
 
37
 write   ( addr=f0000000, size=1010, be=1111 )
38
 wait    ( level=SUBSUBPART )
39
 wait    ( level=SUBSUBPART )
40
 wait    ( level=SUBSUBPART )
41
 write   ( addr=f1000000, size=1010, be=1000 )
42
 
43
 
44
 wait    ( level=SUBSUBPART )
45
 wait    ( level=SUBSUBPART )
46
 wait    ( level=SUBSUBPART )
47
 read    ( addr=f0000000, size=1010, be=1111 )
48
 
49
 wait    ( level=SUBSUBPART )
50
 wait    ( level=SUBSUBPART )
51
 wait    ( level=SUBSUBPART )
52
 read    ( addr=f1000000, size=1010, be=1000 )
53
 
54
 
55
 
56
 ---------------------------------
57
 --  64-Bit Master              --
58
 
59
 set_device(path=/system_tb/dut/plb_bfm_master_64/plb_bfm_master_64/master,device_type=plb_master)
60
 configure(msize=01)
61
 
62
 mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
63
 mem_update(addr=f0000010,data=01111100_02111100_03111100_04111100)
64
 mem_update(addr=f0000020,data=01222200_02222200_03222200_04222200)
65
 mem_update(addr=f0000030,data=01333300_02333300_03333300_04333300)
66
 
67
 mem_update(addr=f1000000,data=01000011_02000011_03000011_04000011)
68
 mem_update(addr=f1000010,data=01111111_02111111_03111111_04111111)
69
 mem_update(addr=f1000020,data=01222211_02222211_03222211_04222211)
70
 mem_update(addr=f1000030,data=01333311_02333311_03333311_04333311)
71
 
72
 
73
 
74
 wait( level=PART )
75
 wait( level=SUBPART )
76
 wait( level=SUBPART )
77
 
78
 
79
 write   ( addr=f0000000, size=1010, be=1101 )
80
 wait    ( level=SUBSUBPART )
81
 wait    ( level=SUBSUBPART )
82
 wait    ( level=SUBSUBPART )
83
 write   ( addr=f1000000, size=1010, be=0100 )
84
 
85
 wait    ( level=SUBSUBPART )
86
 wait    ( level=SUBSUBPART )
87
 wait    ( level=SUBSUBPART )
88
 read    ( addr=f0000000, size=1010, be=1101 )
89
 
90
 wait    ( level=SUBSUBPART )
91
 wait    ( level=SUBSUBPART )
92
 wait    ( level=SUBSUBPART )
93
 read    ( addr=f1000000, size=1010, be=0100 )
94
 
95
 
96
 
97
 
98
 ---------------------------------
99
 --  128-Bit Master              --
100
 
101
 set_device(path=/system_tb/dut/plb_bfm_master_128/plb_bfm_master_128/master,device_type=plb_master)
102
 configure(msize=10)
103
 
104
 mem_update(addr=f0000000,data=01000000_02000000_03000000_04000000)
105
 mem_update(addr=f0000010,data=01111100_02111100_03111100_04111100)
106
 mem_update(addr=f0000020,data=01222200_02222200_03222200_04222200)
107
 mem_update(addr=f0000030,data=01333300_02333300_03333300_04333300)
108
 
109
 mem_update(addr=f1000000,data=01000011_02000011_03000011_04000011)
110
 mem_update(addr=f1000010,data=01111111_02111111_03111111_04111111)
111
 mem_update(addr=f1000020,data=01222211_02222211_03222211_04222211)
112
 mem_update(addr=f1000030,data=01333311_02333311_03333311_04333311)
113
 
114
 
115
 
116
 
117
 
118
 wait( level=PART )
119
 wait( level=SUBPART )
120
 wait( level=SUBPART )
121
 wait( level=SUBPART )
122
 
123
 
124
 write   ( addr=f0000000, size=1010, be=0001 )
125
 wait    ( level=SUBSUBPART )
126
 wait    ( level=SUBSUBPART )
127
 wait    ( level=SUBSUBPART )
128
 write   ( addr=f1000000, size=1010, be=1110 )
129
 
130
 wait    ( level=SUBSUBPART )
131
 wait    ( level=SUBSUBPART )
132
 wait    ( level=SUBSUBPART )
133
 read    ( addr=f0000000, size=1010, be=0001 )
134
 
135
 wait    ( level=SUBSUBPART )
136
 wait    ( level=SUBSUBPART )
137
 wait    ( level=SUBSUBPART )
138
 read    ( addr=f1000000, size=1010, be=1110 )
139
 
140
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.