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[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [32bit_on_128bitPLB_syn/] [system.mhs] - Blame information for rev 2

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1 2 feddischso 
 
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# ##############################################################################
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# Created by Base System Builder Wizard for Xilinx EDK 11.4 Build EDK_LS4.68
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# Fri Mar  5 18:02:26 2010
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# Target Board:  Xilinx Virtex 5 ML501 Evaluation Platform Rev 1
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# Family:    virtex5
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# Device:    xc5vlx50
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# Package:   ff676
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# Speed Grade:  -1
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# Processor number: 1
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# Processor 1: microblaze_0
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# System clock frequency: 125.0
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# Debug Interface: On-Chip HW Debug Module
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# ##############################################################################
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 PARAMETER VERSION = 2.1.0
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 PORT sys_clk_pin = clk_100MHz, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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 PORT sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
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 PORT to_synch_in_pin = synch_in, DIR = I, VEC = [0:31]
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 PORT from_synch_out_pin = synch_out, DIR = O, VEC = [0:31]
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BEGIN plb_v46
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 PARAMETER INSTANCE = mb_plb
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 PARAMETER HW_VER = 1.04.a
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 PARAMETER C_EXT_RESET_HIGH = 1
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 PARAMETER C_DCR_INTFCE = 1
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 PARAMETER C_BASEADDR = 0b0000000000
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 PARAMETER C_HIGHADDR = 0b1111111111
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 PORT PLB_Clk = clk_100MHz
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 PORT SYS_Rst = sys_rst_s
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END
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BEGIN plbv46_master_bfm
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 PARAMETER INSTANCE = plb_bfm_master_32
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER PLB_MASTER_SIZE = 0b10
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 PARAMETER PLB_MASTER_NUM = 0b0000
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 PARAMETER C_MPLB_NATIVE_DWIDTH = 128
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 PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
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 BUS_INTERFACE MPLB = mb_plb
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 PORT SYNCH_OUT = bfm_synch_out_0
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 PORT SYNCH_IN = synch_in
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END
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BEGIN plbv46_master_bfm
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 PARAMETER INSTANCE = plb_bfm_master_64
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
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 PARAMETER PLB_MASTER_SIZE = 0b10
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 PARAMETER PLB_MASTER_NUM = 0b0001
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 PARAMETER C_MPLB_NATIVE_DWIDTH = 128
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 BUS_INTERFACE MPLB = mb_plb
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 PORT SYNCH_OUT = bfm_synch_out_1
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 PORT SYNCH_IN = synch_in
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END
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BEGIN plbv46_master_bfm
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 PARAMETER INSTANCE = plb_bfm_master_128
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER PLB_MASTER_ADDR_HI_0 = 0xffffffff
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 PARAMETER C_MPLB_NATIVE_DWIDTH = 128
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 PARAMETER PLB_MASTER_NUM = 0b0010
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 BUS_INTERFACE MPLB = mb_plb
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 PORT SYNCH_OUT = bfm_synch_out_2
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 PORT SYNCH_IN = synch_in
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END
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BEGIN plbv46_monitor_bfm
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 PARAMETER INSTANCE = plb_bfm_monitor
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 PARAMETER HW_VER = 1.00.a
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 BUS_INTERFACE MON_PLB = mb_plb
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 PORT SYNCH_OUT = bfm_synch_out_3
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 PORT SYNCH_IN = synch_in
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END
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BEGIN plbv46_slave_bfm
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 PARAMETER INSTANCE = plb_bfm_slave
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER PLB_SLAVE_ADDR_LO_0 = 0xF8000000
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 PARAMETER PLB_SLAVE_ADDR_HI_0 = 0xFFFFfFFF
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 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
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 PARAMETER PLB_SLAVE_SIZE = 0b00
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 BUS_INTERFACE SPLB = mb_plb
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 PORT SYNCH_IN = synch_in
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 PORT SYNCH_OUT = bfm_synch_out_4
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END
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BEGIN bfm_synch
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 PARAMETER INSTANCE = plb_bfm_synch
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_NUM_SYNCH = 5
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 PORT TO_SYNCH_IN = synch_out
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 PORT FROM_SYNCH_OUT = bfm_synch_out_0 & bfm_synch_out_1 & bfm_synch_out_2 & bfm_synch_out_3 & bfm_synch_out_4
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END
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BEGIN plb2wb_bridge
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 PARAMETER INSTANCE = plb2wb_bridge_0
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_BASEADDR = 0xf0000000
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 PARAMETER C_HIGHADDR = 0xf7ffffff
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 PARAMETER WB_ADR_OFFSET = 0xf0000000
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 PARAMETER WB_ADR_OFFSET_NEG = 1
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 PARAMETER WB_PIC_INTS = 1
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 BUS_INTERFACE SPLB = mb_plb
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 BUS_INTERFACE MWB = wb_conbus_0
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 PORT SPLB_Clk = clk_100MHz
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 PORT wb_clk_i = clk_100MHz
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 PORT wb_rst_i = sys_rst_s
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 PORT wb_pic_int_i = net_gnd
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END
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BEGIN wb_conbus
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 PARAMETER INSTANCE = wb_conbus_0
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER wb_s0_addr = 0x00
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 PARAMETER wb_s27_addr_w = 8
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 PARAMETER wb_s1_addr = 0x01
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 PARAMETER wb_s2_addr = 0x02
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 PARAMETER wb_s3_addr = 0x03
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 PARAMETER wb_s4_addr = 0x04
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 PARAMETER wb_s5_addr = 0x05
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 PARAMETER wb_s6_addr = 0x06
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 PARAMETER wb_s7_addr = 0x07
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 PARAMETER wb_s0_addr_w = 8
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 PARAMETER wb_s1_addr_w = 8
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 PORT wb_rst_i = sys_rst_s
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 PORT wb_clk_i = clk_100MHz
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END
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BEGIN testram
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 PARAMETER INSTANCE = onchip_ram_0
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER RD_DELAY = 0
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 PARAMETER WR_DELAY = 0
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 BUS_INTERFACE SWB = wb_conbus_0
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 PORT wb_rst_i = sys_rst_s
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 PORT wb_clk_i = clk_100MHz
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END
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BEGIN testram
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 PARAMETER INSTANCE = onchip_ram_1
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER RD_DELAY = 1
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 PARAMETER WR_DELAY = 1
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 BUS_INTERFACE SWB = wb_conbus_0
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 PORT wb_clk_i = clk_100MHz
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 PORT wb_rst_i = sys_rst_s
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END
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BEGIN testram
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 PARAMETER INSTANCE = onchip_ram_2
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER RD_DELAY = 3
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 PARAMETER WR_DELAY = 3
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 BUS_INTERFACE SWB = wb_conbus_0
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 PORT wb_clk_i = clk_100MHz
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 PORT wb_rst_i = sys_rst_s
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END
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BEGIN testram
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 PARAMETER INSTANCE = onchip_ram_3
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER RD_DELAY = 5
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 PARAMETER WR_DELAY = 5
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 BUS_INTERFACE SWB = wb_conbus_0
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 PORT wb_clk_i = clk_100MHz
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 PORT wb_rst_i = sys_rst_s
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END
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