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feddischso |
#################################################################
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# Makefile generated by Xilinx Platform Studio
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# Project:/home/christian/share/semesterproject/trunk/systems/test_system_sim/wb_err_and_rst/system.xmp
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#
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# WARNING : This file will be re-generated every time a command
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# to run a make target is invoked. So, any changes made to this
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# file manually, will be lost when make is invoked next.
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#################################################################
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XILINX_EDK_DIR = /opt/Xilinx/11.1/EDK
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NON_CYG_XILINX_EDK_DIR = /opt/Xilinx/11.1/EDK
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SYSTEM = system
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MHSFILE = system.mhs
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MSSFILE = system.mss
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FPGA_ARCH = virtex5
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DEVICE = xc5vlx50ff676-1
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LANGUAGE = vhdl
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SEARCHPATHOPT = -lp /home/christian/share/semesterproject/trunk/systems/EDK_Libs/
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GLOBAL_SEARCHPATHOPT =
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SUBMODULE_OPT =
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PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst
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LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst
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OBSERVE_PAR_OPTIONS = -error yes
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MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
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PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
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PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
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BOOTLOOP_DIR = bootloops
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BRAMINIT_ELF_FILES =
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BRAMINIT_ELF_FILE_ARGS =
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ALL_USER_ELF_FILES =
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SIM_CMD = vsim
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BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do
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STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do
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TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do
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DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
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MIX_LANG_SIM_OPT = -mixed yes
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SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s mti
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LIBRARIES =
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LIBSCLEAN_TARGETS =
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PROGRAMCLEAN_TARGETS =
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CORE_STATE_DEVELOPMENT_FILES =
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WRAPPER_NGC_FILES = implementation/mb_plb_wrapper.ngc \
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implementation/plb2wb_bridge_0_wrapper.ngc \
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implementation/wb_conbus_0_wrapper.ngc \
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implementation/onchip_ram_0_wrapper.ngc \
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implementation/onchip_ram_1_wrapper.ngc \
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implementation/onchip_ram_2_wrapper.ngc \
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implementation/onchip_ram_3_wrapper.ngc \
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implementation/onchip_ram_4_wrapper.ngc \
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implementation/onchip_ram_5_wrapper.ngc
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POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
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SYSTEM_BIT = implementation/$(SYSTEM).bit
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DOWNLOAD_BIT = implementation/download.bit
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SYSTEM_ACE = implementation/$(SYSTEM).ace
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UCF_FILE = data/system.ucf
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BMM_FILE = implementation/$(SYSTEM).bmm
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BITGEN_UT_FILE = etc/bitgen.ut
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XFLOW_OPT_FILE = etc/fast_runtime.opt
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XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)
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XPLORER_DEPENDENCY = __xps/xplorer.opt
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XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7
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FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY)
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SDK_EXPORT_DIR = SDK/SDK_Export/hw
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SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml
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SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit
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SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT)
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