URL https://opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk

Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_irqs/] [simulation/] [Makefile] - Blame information for rev 2

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SIM_DIR=$(shell pwd)
 
XPS_PROJ_DIR=$(SIM_DIR)/..
SIM_BIN_DIR=$(SIM_DIR)/sim_bin
COMMON_DIR=$(SIM_DIR)/../../common
LOG_DIR=$(SIM_DIR)/log
PLB_BFM_SETUP_DIR=$(SIM_DIR)/../../plb_bfm_setup
 
 
include $(COMMON_DIR)/Makefile
 
 
 
all: sim
 
 
 
WORK_TARGET=$(SIM_BIN_DIR)/work/system/_primary.dat
 
 
 
###
#
#       note: WORK_TARGET is defined some lines above, the rest in ../../common/Makefile
#
COMPILE_COMPONENTS=$(TESTRAM_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET) $(PLB_BFM_TARGET) $(WORK_TARGET)
 
 
 
#
#       Generate Simulation HDL Files
#   (This is the same than  XPS-Gui->Simulation->Generate Simulation HDL Files)
#
$(SIM_DIR)/behavioral: $(XPS_PROJ_DIR)/system.mhs
        @mkdir -p $(LOG_DIR)
        simgen $(XPS_PROJ_DIR)/system.mhs       -lang vhdl                                      \
                                                                                                        -p virtex5                              \
                                                                                                        -m beh                                          \
                                                                                                        -od $(XPS_PROJ_DIR)/    \
                                                                                                        -s mti                                          \
                                                                                                        -lp $(LIB_DIR)                          \
                                                                                                        -log $(LOG_DIR)/simgen
        @mv simgen.opt log      # there is no simgen-flag for this!
 
 
 
 
 
# PLB_BFM_TARGET=$(SIM_BIN_DIR)/plbv46_bfm/system/_primary.dat
# #BFM_SOURCE=$() TODO
# $(PLB_BFM_TARGET):
# cd $(SIM_BIN_DIR);                                                                                                                                                                                            \
# vlib plbv46_bfm;                                                                                                                                                                                                      \
# vmap plbv46_bfm plbv46_bfm;                                                                                                                                                                   \
# vlib plbv46_master_bfm_v1_00_a;                                                                                                                                                               \
# vmap plbv46_master_bfm_v1_00_a plbv46_master_bfm_v1_00_a;                                                                                     \
# vlib plbv46_monitor_bfm_v1_00_a;                                                                                                                                                              \
# vmap plbv46_monitor_bfm_v1_00_a plbv46_monitor_bfm_v1_00_a;                                                                                   \
# vlib plbv46_slave_bfm_v1_00_a;                                                                                                                                                                \
# vmap plbv46_slave_bfm_v1_00_a plbv46_slave_bfm_v1_00_a;                                                                                               \
# vcom $(VHDL_CFLAGS) -work plbv46_bfm                                                                                                                                          \
#       "$(PLB_BFM_SETUP_DIR)/plb_dcl_128.vhd";                                                                                                                         \
# vcom $(VHDL_CFLAGS) -work plbv46_master_bfm_v1_00_a                                                                                                   \
#       "$(PLB_BFM_LIB_DIR)/pcores/plbv46_master_bfm_v1_00_a/hdl/vhdl/plbv46_master_bfm.vhd" ; \
# vcom $(VHDL_CFLAGS) -work plbv46_monitor_bfm_v1_00_a                                                                                                  \
#       "$(PLB_BFM_LIB_DIR)/pcores/plbv46_monitor_bfm_v1_00_a/hdl/vhdl/plbv46_monitor_bfm.vhd";\
# vcom $(VHDL_CFLAGS) -work plbv46_slave_bfm_v1_00_a                                                                                                            \
#       "$(PLB_BFM_LIB_DIR)/pcores/plbv46_slave_bfm_v1_00_a/hdl/vhdl/plbv46_slave_bfm.vhd";
 
 
 
 
 
$(WORK_TARGET): $(SIM_DIR)/behavioral  $(SIM_BIN_DIR)/../testbench/system_tb.vhd
        cd $(SIM_BIN_DIR);      \
        vlib work;                              \
        vmap work work;         \
        vlog -novopt -93 -work work  "../behavioral/wb_conbus_0_wrapper.v";                     \
        vcom $(VHDL_CFLAGS) -work work \
                              "../behavioral/onchip_ram_0_wrapper.vhd"        \
                              "../behavioral/mb_plb_wrapper.vhd"              \
                              "../behavioral/plb_bfm_master_32_wrapper.vhd"   \
                              "../behavioral/plb_bfm_monitor_wrapper.vhd"     \
                              "../behavioral/plb_bfm_synch_wrapper.vhd"       \
                              "../behavioral/plb2wb_bridge_0_wrapper.vhd"     \
                              "../behavioral/system.vhd"                      \
                              "../testbench/system_tb.vhd"
 
 
 
 
 
 
compile: $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS)
 
 
 
 
 
 
clean:
        @echo "cleaning sim bin dir in retries\n"
        rm -rf                                          \
        $(SIM_DIR)/behavioral   \
        $(SIM_BIN_DIR)                          \
        $(LOG_DIR)
 

Line No.	Rev	Author	Line
1	2	feddischso	`SIM_DIR=$(shell pwd)`
2
3			`XPS_PROJ_DIR=$(SIM_DIR)/..`
4			`SIM_BIN_DIR=$(SIM_DIR)/sim_bin`
5			`COMMON_DIR=$(SIM_DIR)/../../common`
6			`LOG_DIR=$(SIM_DIR)/log`
7			`PLB_BFM_SETUP_DIR=$(SIM_DIR)/../../plb_bfm_setup`
8
9
10			`include $(COMMON_DIR)/Makefile`
11
12
13
14			`all: sim`
15
16
17
18			`WORK_TARGET=$(SIM_BIN_DIR)/work/system/_primary.dat`
19
20
21
22			`###`
23			`#`
24			`# note: WORK_TARGET is defined some lines above, the rest in ../../common/Makefile`
25			`#`
26			`COMPILE_COMPONENTS=$(TESTRAM_TARGET) $(PLB2WB_BRIDGE_TARGET) $(WB_TARGET) $(PLB_BFM_TARGET) $(WORK_TARGET)`
27
28
29
30			`#`
31			`# Generate Simulation HDL Files`
32			`# (This is the same than XPS-Gui->Simulation->Generate Simulation HDL Files)`
33			`#`
34			`$(SIM_DIR)/behavioral: $(XPS_PROJ_DIR)/system.mhs`
35			`@mkdir -p $(LOG_DIR)`
36			`simgen $(XPS_PROJ_DIR)/system.mhs -lang vhdl \`
37			`-p virtex5 \`
38			`-m beh \`
39			`-od $(XPS_PROJ_DIR)/ \`
40			`-s mti \`
41			`-lp $(LIB_DIR) \`
42			`-log $(LOG_DIR)/simgen`
43			`@mv simgen.opt log # there is no simgen-flag for this!`
44
45
46
47
48
49			`# PLB_BFM_TARGET=$(SIM_BIN_DIR)/plbv46_bfm/system/_primary.dat`
50			`# #BFM_SOURCE=$() TODO`
51			`# $(PLB_BFM_TARGET):`
52			`# cd $(SIM_BIN_DIR); \`
53			`# vlib plbv46_bfm; \`
54			`# vmap plbv46_bfm plbv46_bfm; \`
55			`# vlib plbv46_master_bfm_v1_00_a; \`
56			`# vmap plbv46_master_bfm_v1_00_a plbv46_master_bfm_v1_00_a; \`
57			`# vlib plbv46_monitor_bfm_v1_00_a; \`
58			`# vmap plbv46_monitor_bfm_v1_00_a plbv46_monitor_bfm_v1_00_a; \`
59			`# vlib plbv46_slave_bfm_v1_00_a; \`
60			`# vmap plbv46_slave_bfm_v1_00_a plbv46_slave_bfm_v1_00_a; \`
61			`# vcom $(VHDL_CFLAGS) -work plbv46_bfm \`
62			`# "$(PLB_BFM_SETUP_DIR)/plb_dcl_128.vhd"; \`
63			`# vcom $(VHDL_CFLAGS) -work plbv46_master_bfm_v1_00_a \`
64			`# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_master_bfm_v1_00_a/hdl/vhdl/plbv46_master_bfm.vhd" ; \`
65			`# vcom $(VHDL_CFLAGS) -work plbv46_monitor_bfm_v1_00_a \`
66			`# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_monitor_bfm_v1_00_a/hdl/vhdl/plbv46_monitor_bfm.vhd";\`
67			`# vcom $(VHDL_CFLAGS) -work plbv46_slave_bfm_v1_00_a \`
68			`# "$(PLB_BFM_LIB_DIR)/pcores/plbv46_slave_bfm_v1_00_a/hdl/vhdl/plbv46_slave_bfm.vhd";`
69
70
71
72
73
74			`$(WORK_TARGET): $(SIM_DIR)/behavioral $(SIM_BIN_DIR)/../testbench/system_tb.vhd`
75			`cd $(SIM_BIN_DIR); \`
76			`vlib work; \`
77			`vmap work work; \`
78			`vlog -novopt -93 -work work "../behavioral/wb_conbus_0_wrapper.v"; \`
79			`vcom $(VHDL_CFLAGS) -work work \`
80			`"../behavioral/onchip_ram_0_wrapper.vhd" \`
81			`"../behavioral/mb_plb_wrapper.vhd" \`
82			`"../behavioral/plb_bfm_master_32_wrapper.vhd" \`
83			`"../behavioral/plb_bfm_monitor_wrapper.vhd" \`
84			`"../behavioral/plb_bfm_synch_wrapper.vhd" \`
85			`"../behavioral/plb2wb_bridge_0_wrapper.vhd" \`
86			`"../behavioral/system.vhd" \`
87			`"../testbench/system_tb.vhd"`
88
89
90
91
92
93
94			`compile: $(SIM_BIN_DIR)/modelsim.ini $(COMPILE_COMPONENTS)`
95
96
97
98
99
100
101			`clean:`
102			`@echo "cleaning sim bin dir in retries\n"`
103			`rm -rf \`
104			`$(SIM_DIR)/behavioral \`
105			`$(SIM_BIN_DIR) \`
106			`$(LOG_DIR)`
107

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Subversion Repositories plb2wbbridge

[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_irqs/] [simulation/] [Makefile] - Blame information for rev 2