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----------------------------------------------------------------------
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----                                                              ----
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---- PlTbUtils Components                                         ----
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----                                                              ----
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---- This file is part of the PlTbUtils project                   ----
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---- http://opencores.org/project,pltbutils                       ----
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----                                                              ----
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---- Description:                                                 ----
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---- PlTbUtils is a collection of functions, procedures and       ----
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---- components for easily creating stimuli and checking response ----
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---- in automatic self-checking testbenches.                      ----
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----                                                              ----
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---- pltbutils_comp.vhd (this file) defines testbench components. ----
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----                                                              ----
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----                                                              ----
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---- To Do:                                                       ----
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---- -                                                            ----
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----                                                              ----
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---- Author(s):                                                   ----
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---- - Per Larsson, pela.opencores@gmail.com                      ----
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----                                                              ----
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----------------------------------------------------------------------
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----                                                              ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG                 ----
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----                                                              ----
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---- This source file may be used and distributed without         ----
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---- restriction provided that this copyright statement is not    ----
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---- removed from the file and that any derivative work contains  ----
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---- the original copyright notice and the associated disclaimer. ----
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----                                                              ----
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---- This source file is free software; you can redistribute it   ----
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---- and/or modify it under the terms of the GNU Lesser General   ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any   ----
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---- later version.                                               ----
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----                                                              ----
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---- This source is distributed in the hope that it will be       ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
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---- PURPOSE. See the GNU Lesser General Public License for more  ----
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---- details.                                                     ----
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----                                                              ----
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---- You should have received a copy of the GNU Lesser General    ----
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---- Public License along with this source; if not, download it   ----
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---- from http://www.opencores.org/lgpl.shtml                     ----
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----                                                              ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- pltbutils_clkgen
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-- Creates a clock for use in a testbech.
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-- A non-inverted as well as an inverted output is available, 
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-- use one or both depending on if you need a single-ended or
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-- differential clock.
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-- The clock stops when input port stop_sim goes '1'.
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-- This makes the simulator stop (unless there are other infinite 
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-- processes running in the simulation).
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity pltbutils_clkgen is
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  generic (
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    G_PERIOD        : time := 10 ns;
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    G_INITVALUE     : std_logic := '0'
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  );
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  port (
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    clk_o           : out std_logic;
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    clk_n_o         : out std_logic;
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    stop_sim_i      : in  std_logic
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  );
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end entity pltbutils_clkgen;
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architecture bhv of pltbutils_clkgen is
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  constant C_HALF_PERIOD    : time := G_PERIOD / 2;
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  signal   clk              : std_logic := G_INITVALUE;
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begin
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  clk       <= not clk and not stop_sim_i after C_HALF_PERIOD;
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  clk_o     <= clk;
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  clk_n_o   <= not clk;
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end architecture bhv;
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