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[/] [powersupplysequencer/] [vhdl/] [tb/] [PowerSupply/] [PowerSupply_tb.vhd] - Blame information for rev 2

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1 2 dk4xp
-- Testbed for the power supply
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-- (c) 2009.. Gerhard Hoffmann  opencores@hoffmann-hochfrequenz.de
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-- published under BSD conditions.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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entity PowerSupply_tb is end entity PowerSupply_tb;
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architecture tb of PowerSupply_tb is
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  signal defective: boolean;
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  signal ena:       std_logic;
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  signal pgood:     std_logic;
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  signal vout:      real;
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begin
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ena       <= '0', '1' after 10 ms, '0' after 20 ms, '1' after 35 ms;
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defective <= false, true after 50 ms;
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uut: entity work.PowerSupply
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generic map (
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  voltage    => 3.3,
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  risetime   => 2.0e-3
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)
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port map (
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  defective => defective,
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  ena       => ena,
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  pgood     => pgood,
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  vout      => vout
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);
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end architecture tb;
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