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[/] [powersupplysequencer/] [vhdl/] [tb/] [clk_rst/] [clk_rst_tb.vhd] - Blame information for rev 2

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1 2 dk4xp
--
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--  testbed for entity clk_rst.vhd
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--  (c) jul 2007...  Gerhard Hoffmann, opencores@hoffmann-hochfrequenz.de
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--  open source under BSD conditions
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library IEEE;
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use     IEEE.STD_LOGIC_1164.all;
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use     IEEE.numeric_std.all;
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entity clk_rst_tb is
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end entity clk_rst_tb;
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architecture rtl of clk_rst_tb is
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signal tb_clk: std_logic;
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signal tb_rst: std_logic;
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begin
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uut: entity work.clk_rst
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  generic  map(
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    verbose           => true,
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    clock_frequency   => 100.0e6,
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    min_resetwidth    => 153 ns
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  )
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  port map(
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    clk               => tb_clk,
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    rst               => tb_rst
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  );
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end architecture rtl;
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