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[/] [present/] [trunk/] [32BitIO/] [rtl/] [vhdl/] [PresentStateMachine.vhd] - Blame information for rev 4

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1 4 gajos
-----------------------------------------------------------------------
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----                                                               ----
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---- Present - a lightweight block cipher project                  ----
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----                                                               ----
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---- This file is part of the Present - a lightweight block        ----
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---- cipher project                                                ----
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---- http://www.http://opencores.org/project,present               ----
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----                                                               ----
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---- Description:                                                  ----
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----     State machine for Present encoder with 32 bit IO. For more----
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---- informations                                                  ----
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---- see below.                                                    ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
45 2 gajos
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.kody.ALL;
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entity PresentStateMachine is
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        generic (
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                        w_2 : integer := 2;
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                        w_4 : integer := 4;
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                        w_5 : integer := 5;
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                        w_32: integer := 32;
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                        w_64: integer := 64;
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                        w_80: integer := 80
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        );
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        port (
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                clk, reset : in std_logic;
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                info : in std_logic_vector (w_2-1 downto 0);
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                ctrl : in std_logic_vector (w_4-1 downto 0);
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                key_ctrl: out std_logic_vector (w_2-1 downto 0);
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                plain_ctrl: out std_logic_vector (w_2-1 downto 0);
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                outReg : out std_logic_vector (w_2-1 downto 0);
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                ready, cnt_res, ctrl_mux64, ctrl_mux80: out std_logic
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        );
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end PresentStateMachine;
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architecture Behavioral of PresentStateMachine is
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        signal stan : stany;
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        signal stan_nast : stany;
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        begin
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                States : process(stan, ctrl, info)
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                        begin
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                                stan_nast<= stan;
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                                case stan is
82 4 gajos
                                    -- waiting for start
83 2 gajos
                                        when NOP =>
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                                                ready <= '0';
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                                                outReg <= out_reg_Z;
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                                                cnt_res <= '0';
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                                                ctrl_mux64 <= '0';
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                                                ctrl_mux80 <= '0';
89 4 gajos
                                                -- read first 32 bits of key
90 2 gajos
                                                if (ctrl = crdk1) then
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                                                        key_ctrl <= in_ld_reg_L;
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                                                        stan_nast <= RDK1;
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                                                else
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                                                        stan_nast <= NOP;
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                                                end if;
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                                        when RDK1 =>
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                                            -- read second 32 bits of key
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                                                if (ctrl = crdk2) then
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                                                        key_ctrl <= in_ld_reg_H;
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                                                        stan_nast <= RDK2;
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                                                -- wait for next 32 bits of key
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                                                elsif (ctrl = crdk1) then
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                                                        key_ctrl <= in_ld_reg_L;
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                                                else
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                                                        stan_nast <= NOP;
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                                                end if;
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                                        when RDK2 =>
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                                            -- read last 16 bits of key
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                                                if (ctrl = crdk3) then
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                                                        key_ctrl <= in_ld_reg_HH;
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                                                        stan_nast <= RDK3;
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                                                -- wait for next 16 bits of key
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                                                elsif (ctrl = crdk2) then
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                                                        key_ctrl <= in_ld_reg_H;
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                                                else
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                                                        stan_nast <= NOP;
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                                                end if;
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                                        when RDK3 =>
119 4 gajos
                                            -- read first 32 bits of text
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                                                if (ctrl = crdt1) then
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                                                        key_ctrl <= in_reg_Z;
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                                                        plain_ctrl <= in_ld_reg_L;
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                                                        stan_nast <= RDT1;
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                                                -- wait for first 32 bits of text
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                                                elsif (ctrl = crdk3) then
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                                                        key_ctrl <= in_ld_reg_HH;
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                                                else
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                                                        stan_nast <= NOP;
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                                                end if;
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                                        when RDT1 =>
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                                            -- read second 32 bits of text
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                                                if (ctrl = crdt2) then
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                                                        plain_ctrl <= in_ld_reg_H;
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                                                        stan_nast <= RDT2;
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                                                -- wait for second 32 bits of text
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                                                elsif (ctrl = crdt1) then
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                                                        plain_ctrl <= in_ld_reg_L;
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                                                else
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                                                        stan_nast <= NOP;
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                                                end if;
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                                        when RDT2 =>
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                                            --- Encode data
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                                                if (ctrl = ccod) then
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                                                        plain_ctrl <= in_reg_Z;
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                                                        stan_nast <= COD;
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                                                        cnt_res <= '1';
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                                                -- Wait for encode
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                                                elsif (ctrl = crdt2) then
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                                                        plain_ctrl <= in_ld_reg_H;
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                                                else
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                                                        stan_nast <= NOP;
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                                                end if;
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                                        when COD =>
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                                            -- Encode data
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                                                if (ctrl = ccod) then
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                                                    -- Ready
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                                                        if (info = "00") then
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                                                                stan_nast <= CTO1;
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                                                                outReg <= out_ld_reg;
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                                                                ready <= '1';
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                                                                cnt_res <= '0';
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                                                                ready <= '1';
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                                                        -- encoding
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                                                        elsif (info = "01") then
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                                                                ctrl_mux64 <= '1';
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                                                                ctrl_mux80 <= '1';
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                                                        end if;
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                                                else
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                                                        stan_nast <= NOP;
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                                                end if;
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                                        when CTO1 =>
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                                            -- send first 32 bits of data
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                                                if (ctrl = ccto2) then
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                                                        stan_nast <= CTO2;
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                                                        outReg <= out_reg_L;
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                                                -- wait for sending second 32 bits of data
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                                                elsif ((ctrl = ccto1) or (ctrl = ccod)) then
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                                                        outReg <= out_reg_L;
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                                                else
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                                                        stan_nast <= NOP;
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                                                end if;
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                                        when CTO2 =>
183 4 gajos
                                            -- send second 32 bits of data
184 2 gajos
                                                if (ctrl = ccto2) then
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                                                        stan_nast <= CTO2;
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                                                        outReg <= out_reg_H;
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                                                else
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                                                        stan_nast <= NOP;
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                                                end if;
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                                end case;
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                end process States;
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                inne : process (clk, reset)
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                        begin
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                                if (reset = '1') then
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                                        stan <= NOP;
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                                elsif (clk'Event and clk = '1') then
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                                        stan <= stan_nast;
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                                end if;
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                        end process inne;
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        end Behavioral;
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