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[/] [present/] [trunk/] [PureTesting/] [rtl/] [vhdl/] [PresentEnc.vhd] - Blame information for rev 4

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1 4 gajos 
-----------------------------------------------------------------------
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----                                                               ----
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---- Present - a lightweight block cipher project                  ----
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----                                                               ----
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---- This file is part of the Present - a lightweight block        ----
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---- cipher project                                                ----
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---- http://www.http://opencores.org/project,present               ----
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----                                                               ----
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---- Description:                                                  ----
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----     Top level of present encoder. For more information see    ----
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---- below and http://homes.esat.kuleuven.be/~abogdano/papers/     ----
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---- present_ches07.pdf                                            ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
45 3 gajos 
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity PresentEnc is
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        generic (
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                        w_2: integer := 2;
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                        w_4: integer := 4;
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                        w_5: integer := 5;
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                        w_32: integer := 32;
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                        w_64: integer := 64;
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                        w_80: integer := 80
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        );
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        port(
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                plaintext  : in std_logic_vector(w_64 - 1 downto 0);
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                key               : in std_logic_vector(w_80 - 1 downto 0);
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                ciphertext : out std_logic_vector(w_64 - 1 downto 0);
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                start, clk, reset : in std_logic;
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                ready : out std_logic
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        );
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end PresentEnc;
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architecture Behavioral of PresentEnc is
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        component Reg is
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                generic(width : integer := w_64);
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                port(
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                        input  : in  STD_LOGIC_VECTOR(width - 1 downto 0);
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                        output : out STD_LOGIC_VECTOR(width - 1 downto 0);
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                        enable : in  STD_LOGIC;
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                        clk    : in  STD_LOGIC;
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                        reset  : in  STD_LOGIC
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                );
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        end component Reg;
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        component AsyncMux is
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                generic (
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                        width : integer := 64
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        );
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        port (
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                input0 : in  STD_LOGIC_VECTOR(width - 1 downto 0);
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                input1 : in  STD_LOGIC_VECTOR(width - 1 downto 0);
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                ctrl   : in  STD_LOGIC;
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                output : out STD_LOGIC_VECTOR(width - 1 downto 0)
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        );
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        end component AsyncMux;
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        component PresentStateMachine is
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                generic (
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                        w_5 : integer := 5
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                );
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                port (
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                        clk, reset, start : in std_logic;
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                        ready, cnt_res, ctrl_mux, RegEn: out std_logic;
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                        num : in std_logic_vector (w_5-1 downto 0)
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                );
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        end component;
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105 4 gajos 
        -- substitution layer for decoding
106 3 gajos 
        component slayer is
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                generic (
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                                w_4 : integer := 4
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                );
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                port (
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                        input : in std_logic_vector(w_4-1 downto 0);
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                        output : out std_logic_vector(w_4-1 downto 0)
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                );
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        end component;
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116 4 gajos 
        -- permutation layer for decoding
117 3 gajos 
        component pLayer is
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                generic(w_64 : integer := 64);
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                port(
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                        input : in std_logic_vector(w_64-1 downto 0);
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                        output : out std_logic_vector(w_64-1 downto 0)
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                );
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        end component;
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125 4 gajos 
        -- key update for decoding
126 3 gajos 
        component keyupd is
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                generic(
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                        w_5 : integer := 5;
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                        w_80: integer := 80
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                );
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                port(
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                        num : in std_logic_vector(w_5-1 downto 0);
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                        key : in std_logic_vector(w_80-1 downto 0);
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                        keyout : out std_logic_vector(w_80-1 downto 0)
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                );
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        end component;
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138 4 gajos 
        -- counter for decoding. It is counting up!!!
139 3 gajos 
        component counter is
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                generic (
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                        w_5 : integer := 5
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                );
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                port (
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                        clk, reset, cnt_res : in std_logic;
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                        num : out std_logic_vector (w_5-1 downto 0)
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                );
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        end component;
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149 4 gajos 
        -- signals
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151 3 gajos 
        signal keynum : std_logic_vector (w_5-1 downto 0);
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        signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0);
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        signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0);
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        signal ready_sig, mux_ctrl,  cnt_res, RegEn : std_logic;
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        begin
157 4 gajos 
 
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            -- connections
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160 3 gajos 
                mux_64: AsyncMux generic map(width => w_64) port map(
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                        input0 => plaintext,
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                        input1 => Pout,
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                        ctrl => mux_ctrl,
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                        output => textToReg
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                );
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                regText : Reg generic map(width => w_64) port map(
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                        input  => textToReg,
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                        output  => toXor,
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                        enable  => RegEn,
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                        clk  => clk,
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                        reset  => reset
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                );
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                mux_80: AsyncMux generic map(width => w_80) port map(
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                        input0 => key,
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                        input1 => kupd,
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                        ctrl => mux_ctrl,
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                        output => keyToReg
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                );
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                regKey : Reg generic map(width => w_80) port map(
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                        input  => keyToReg,
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                        output  => keyfout,
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                        enable  => RegEn,
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                        clk  => clk,
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                        reset  => reset
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                );
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                slayers : for N in 15 downto 0 generate
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                        s_x: slayer port map(
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                                input => ciph(4*N+3 downto 4*N),
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                                output => P(4*N+3 downto 4*N)
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                        );
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                end generate slayers;
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                p1: pLayer port map(
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                        input => P,
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                        output => Pout
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                );
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                mixer: keyupd port map(
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                        key => keyfout,
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                        num => keynum,
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                        keyout => kupd
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                );
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                SM: PresentStateMachine port map(
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                        start => start,
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                        reset => reset,
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                        ready => ready_sig,
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                        cnt_res => cnt_res,
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                        ctrl_mux => mux_ctrl,
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                        clk => clk,
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                        num => keynum,
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                        RegEn => RegEn
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                );
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                count: counter port map(
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                        clk => clk,
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                        reset => reset,
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                        cnt_res => cnt_res,
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                        num => keynum
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                );
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                ciph <= toXor xor keyfout(79 downto 16);
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                ciphertext <= ciph;
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                ready <= ready_sig;
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end Behavioral;

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