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[/] [product_code_iterative_decoder/] [trunk/] [bench/] [input.vhdl] - Blame information for rev 18

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1 18 arif_endro
-- ------------------------------------------------------------------------
2 14 arif_endro
-- Copyright (C) 2005 Arif Endro Nugroho
3 18 arif_endro
-- All rights reserved.
4 2 arif_endro
-- 
5 18 arif_endro
-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
8 2 arif_endro
-- 
9 18 arif_endro
-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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--    notice, this list of conditions and the following disclaimer in the
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--    documentation and/or other materials provided with the distribution.
14 2 arif_endro
-- 
15 18 arif_endro
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
26 2 arif_endro
-- 
27 18 arif_endro
-- End Of License.
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-- ------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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entity input is
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   port (
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      clock   : out bit;
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      start   : out bit;
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      rxin    : out bit_vector (07 downto 00)
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      );
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end input;
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architecture test_bench of input is
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type char_to_stdlogic_t is array (character) of std_logic;
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constant to_std_logic : char_to_stdlogic_t := (
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   'U' => 'U',
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   'X' => 'X',
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   '0' => '0',
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   '1' => '1',
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   'Z' => 'Z',
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   'W' => 'L',
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   'H' => 'H',
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   '-' => '-',
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others => 'X'
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   );
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file start_ptr : text open read_mode is "../data/start.txt";
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file rxin_ptr  : text open read_mode is "../data/rxin100DB.txt";
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begin
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   process
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   variable start_ln  : line;
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   variable rxin_ln   : line;
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   variable delay     : time := 1 ns;
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   variable start_str : string (01 to 01) := " ";
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   variable rxin_str  : string (01 to 08) := "        ";
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   variable rxin_len  : integer;
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   variable start_var : std_logic;
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   variable rxin_var  : std_logic_vector (07 downto 00);
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   begin
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      while not (endfile(start_ptr) and endfile(rxin_ptr)) loop
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      readline(start_ptr, start_ln);
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      if (not(endfile(rxin_ptr))) then
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         readline(rxin_ptr, rxin_ln);
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      else
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         write(rxin_ln, string'("00000000"));
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      end if;
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      if (start_ln /= NULL) and (start_ln'length > 0) and (rxin_ln /= NULL) and (rxin_ln'length > 0) then
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         read(start_ln, start_str);
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         read(rxin_ln, rxin_str);
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         rxin_len  := rxin_str'length - 1;
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         start_var := to_std_logic (start_str(01));
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         for b in rxin_str'range loop
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            rxin_var(rxin_len)   := to_std_logic (rxin_str(b));
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            rxin_len             := rxin_len - 1;
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         end loop;
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         start    <= to_bit       (start_var);
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         rxin     <= to_bitvector (rxin_var);
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         clock <= '1';
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         wait for delay;
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         clock <= '0';
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         wait for delay;
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      end if;
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      end loop;
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   wait;
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   end process;
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end test_bench;

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