Subversion Repositories product_code_iterative_decoder

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-- Copyright (C) 2005 Arif Endro Nugroho

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library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use std.textio.all;

entity output is

   port (

      start : in bit;

      y0    : in bit;

      y1    : in bit;

      y2    : in bit;

      y3    : in bit

      );

end output;

architecture test_bench of output is

file send_out_ptr : text open write_mode is "send_out.txt";

signal send_out   : bit_vector (03 downto 00);

begin -- architecture test_bench

   process (start)

   variable send_out_ln  : line;

   begin

      if (start = '0' and start'event) then

         for a in send_out'range loop

            write(send_out_ln, send_out(a));

            writeline(send_out_ptr, send_out_ln);

         end loop;

      end if;

   end process;

   send_out <= ( y0 & y1 & y2 & y3 );

end test_bench;