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[/] [product_code_iterative_decoder/] [trunk/] [source/] [comparator_7bit.vhdl] - Blame information for rev 18

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1 18 arif_endro 
-- ------------------------------------------------------------------------
2 14 arif_endro 
-- Copyright (C) 2005 Arif Endro Nugroho
3 18 arif_endro 
-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
8 2 arif_endro 
--
9 18 arif_endro 
-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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--    notice, this list of conditions and the following disclaimer in the
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--    documentation and/or other materials provided with the distribution.
14 2 arif_endro 
--
15 18 arif_endro 
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- End Of License.
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-- ------------------------------------------------------------------------
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30 
library IEEE;
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use IEEE.std_logic_1164.all;
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entity comparator_7bit is
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   port (
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   a_7bit_i   : in  bit_vector (06 downto 00);
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   b_7bit_i   : in  bit_vector (06 downto 00);
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   a_eq_b     : out bit;
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   a_gt_b     : out bit;
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   a_lt_b     : out bit
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   );
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end comparator_7bit;
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architecture structural of comparator_7bit is
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   component bit_comparator
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       port (
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          a_i   : in  bit;
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          b_i   : in  bit;
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          eq_i  : in  bit;
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          gt_i  : in  bit;
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          lt_i  : in  bit;
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          eq_o  : out bit;
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          gt_o  : out bit;
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          lt_o  : out bit
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          );
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   end component;
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signal eq_i_0 : bit;
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signal gt_i_0 : bit;
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signal lt_i_0 : bit;
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signal eq_o_0 : bit;
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signal gt_o_0 : bit;
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signal lt_o_0 : bit;
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signal eq_o_1 : bit;
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signal gt_o_1 : bit;
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signal lt_o_1 : bit;
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signal eq_o_2 : bit;
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signal gt_o_2 : bit;
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signal lt_o_2 : bit;
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signal eq_o_3 : bit;
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signal gt_o_3 : bit;
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signal lt_o_3 : bit;
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signal eq_o_4 : bit;
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signal gt_o_4 : bit;
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signal lt_o_4 : bit;
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signal eq_o_5 : bit;
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signal gt_o_5 : bit;
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signal lt_o_5 : bit;
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signal eq_o_6 : bit;
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signal gt_o_6 : bit;
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signal lt_o_6 : bit;
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begin
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eq_i_0 <= '1'; -- 20051015 Fixed
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gt_i_0 <= '0';
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lt_i_0 <= '0';
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a_eq_b <= eq_o_6;
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a_gt_b <= gt_o_6;
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a_lt_b <= lt_o_6;
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cmp6 : bit_comparator
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   port map (
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     a_i   =>  a_7bit_i (06),
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     b_i   =>  b_7bit_i (06),
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     eq_i  =>  eq_o_5,
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     gt_i  =>  gt_o_5,
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     lt_i  =>  lt_o_5,
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     eq_o  =>  eq_o_6,
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     gt_o  =>  gt_o_6,
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     lt_o  =>  lt_o_6
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     );
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cmp5 : bit_comparator
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   port map (
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     a_i   =>  a_7bit_i (05),
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     b_i   =>  b_7bit_i (05),
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     eq_i  =>  eq_o_4,
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     gt_i  =>  gt_o_4,
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     lt_i  =>  lt_o_4,
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     eq_o  =>  eq_o_5,
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     gt_o  =>  gt_o_5,
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     lt_o  =>  lt_o_5
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     );
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cmp4 : bit_comparator
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   port map (
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     a_i   =>  a_7bit_i (04),
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     b_i   =>  b_7bit_i (04),
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     eq_i  =>  eq_o_3,
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     gt_i  =>  gt_o_3,
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     lt_i  =>  lt_o_3,
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     eq_o  =>  eq_o_4,
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     gt_o  =>  gt_o_4,
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     lt_o  =>  lt_o_4
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     );
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cmp3 : bit_comparator
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   port map (
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     a_i   =>  a_7bit_i (03),
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     b_i   =>  b_7bit_i (03),
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     eq_i  =>  eq_o_2,
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     gt_i  =>  gt_o_2,
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     lt_i  =>  lt_o_2,
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     eq_o  =>  eq_o_3,
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     gt_o  =>  gt_o_3,
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     lt_o  =>  lt_o_3
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     );
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cmp2 : bit_comparator
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   port map (
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     a_i   =>  a_7bit_i (02),
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     b_i   =>  b_7bit_i (02),
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     eq_i  =>  eq_o_1,
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     gt_i  =>  gt_o_1,
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     lt_i  =>  lt_o_1,
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     eq_o  =>  eq_o_2,
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     gt_o  =>  gt_o_2,
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     lt_o  =>  lt_o_2
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     );
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cmp1 : bit_comparator
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   port map (
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     a_i   =>  a_7bit_i (01),
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     b_i   =>  b_7bit_i (01),
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     eq_i  =>  eq_o_0,
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     gt_i  =>  gt_o_0,
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     lt_i  =>  lt_o_0,
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     eq_o  =>  eq_o_1,
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     gt_o  =>  gt_o_1,
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     lt_o  =>  lt_o_1
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     );
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cmp0 : bit_comparator
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   port map (
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     a_i   =>  a_7bit_i (00),
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     b_i   =>  b_7bit_i (00),
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     eq_i  =>  eq_i_0,
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     gt_i  =>  gt_i_0,
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     lt_i  =>  lt_i_0,
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     eq_o  =>  eq_o_0,
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     gt_o  =>  gt_o_0,
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     lt_o  =>  lt_o_0
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     );
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end structural;

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