Subversion Repositories product_code_iterative_decoder

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-- Copyright (C) 2004 Arif Endro Nugroho

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library IEEE;

use IEEE.std_logic_1164.ALL;

entity fulladder is

   port (

     addend   : in   bit;

     augend   : in   bit;

     carry_in : in   bit;

     sum      : out  bit;

     carry    : out  bit

     );

end fulladder;

architecture data_flow of fulladder is

begin

     sum    <= ((addend xor augend) xor carry_in);

     carry  <= ((addend and augend) or (carry_in and (addend or augend)));

end data_flow;