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[/] [product_code_iterative_decoder/] [trunk/] [xilinx/] [analyze.vhdl] - Blame information for rev 18

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1 18 arif_endro
-- ------------------------------------------------------------------------
2 14 arif_endro
-- Copyright (C) 2005 Arif Endro Nugroho
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-- All rights reserved.
4 9 arif_endro
-- 
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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-- 
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-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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--    notice, this list of conditions and the following disclaimer in the
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--    documentation and/or other materials provided with the distribution.
14 9 arif_endro
-- 
15 18 arif_endro
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- 
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-- End Of License.
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-- ------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity analyze is
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   port (
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      clear   : in  bit;
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      start   : in  bit;
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      match   : in  bit_vector (3 downto 0);
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      col_0   : out integer;
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      col_1   : out integer;
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      col_2   : out integer;
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      col_3   : out integer;
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      result  : out integer
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      );
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end analyze;
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architecture analyzer of analyze is
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signal col_0_int  : integer range 0 to 19999;
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signal col_1_int  : integer range 0 to 19999;
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signal col_2_int  : integer range 0 to 19999;
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signal col_3_int  : integer range 0 to 19999;
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signal result_int : integer range 0 to 19999;
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begin
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process (start,clear)
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begin
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if (clear = '1') then
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   col_0_int  <= 0;
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   col_1_int  <= 0;
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   col_2_int  <= 0;
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   col_3_int  <= 0;
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   result_int <= 0;
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-- sample at rising edge then show the result at falling edge.
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elsif (start = '1' and start'event) then
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   if (match(0) = '0') then
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      if (col_0_int < 19999) then
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         col_0_int <= col_0_int + 1;
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      else
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         col_0_int <= 0;
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      end if;
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   end if;
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   if (match(1) = '0') then
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      if (col_1_int < 19999) then
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         col_1_int <= col_1_int + 1;
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      else
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         col_1_int <= 0;
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      end if;
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   end if;
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   if (match(2) = '0') then
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      if (col_2_int < 19999) then
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         col_2_int <= col_2_int + 1;
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      else
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         col_2_int <= 0;
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      end if;
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   end if;
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   if (match(3) = '0') then
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      if (col_3_int < 19999) then
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         col_3_int <= col_3_int + 1;
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      else
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         col_3_int <= 0;
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      end if;
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   end if;
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end if;
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result_int <= col_0_int + col_1_int + col_2_int + col_3_int;
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end process;
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result   <= result_int;
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col_0    <= col_0_int;
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col_1    <= col_1_int;
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col_2    <= col_2_int;
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col_3    <= col_3_int;
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end analyzer;

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