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[/] [pwm/] [trunk/] [testbench/] [PWM_tb.v] - Blame information for rev 2

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//Author: Zhuxu
//Email: m99a1@yahoo.cn
module  PWM_tb();
reg     wb_clk=0,extclk=0;
reg     rst=1;
 
initial #20 rst=0;
 
always #10 wb_clk=~wb_clk;
 
always #1 extclk=~extclk;
 
///////test cases configuration data///////////
wire    [31:0]configdata[0:20];
//PWM test 0
 
assign  configdata[0]=32'h40303;
assign  configdata[1]=32'h600ed;
assign  configdata[2]=31'h17;
//continous timer test 0
assign  configdata[3]=32'h80;
assign  configdata[4]=32'h20005;
assign  configdata[5]=32'h401a1;
assign  configdata[6]=32'h1c;
//continous timer test 1
assign  configdata[7]=32'h1c;
//PWM test 1
assign  configdata[8]=32'h41d00;
assign  configdata[9]=32'h61000;
assign  configdata[10]=32'h56;
//discontinous timer test 0
 
assign  configdata[11]=32'h80;
assign  configdata[12]=32'h20008;
assign  configdata[13]=32'h400aa;
assign  configdata[14]=32'h15;
//discontinous timer test 1
assign  configdata[15]=32'h15;
//continous timer test 2
assign  configdata[16]=32'h80;
assign  configdata[17]=32'h20005;
assign  configdata[18]=32'h401a1;
assign  configdata[19]=32'h15;
//continous timer test 3
assign  configdata[20]=32'h15;
 
 
 
////////////////////////////////////////////////
 
 
/////driver///////////////////////////////////
reg     [15:0]wb_data=0;
reg     [15:0]wb_adr=0;
reg     wb_cyc=0,wb_stb=0,wb_we=0;
wire    wb_ack;
wire    [15:0]extDC;
assign  extDC=60;
reg     [4:0]nconfig=0;
 
task    driver;
        begin
        @(posedge wb_clk);
        wb_cyc<=1;
        wb_stb<=1;
        wb_we<=1;
        wb_adr<=configdata[nconfig][31:16];
        wb_data<=configdata[nconfig][15:0];
        nconfig<=nconfig+1;
        while(!wb_ack)begin
                @(posedge wb_clk);
        end
        wb_cyc<=0;
        wb_stb<=0;
        wb_we<=0;
        end
endtask
//////////////////////////////////////////////
 
//////////////monitor/////////////////////
wire    pwm;
reg     [63:0]ct_period=0;
reg     [63:0]ct_DC=0;
reg     ready=1;
reg     [3:0]state=0;
reg     [1:0]state_mp=0;
reg     [1:0]state_mt=0;
reg     [3:0]nperiod=0;
reg     pwm_1=0;
always@(posedge extclk)
        if(!rst)begin
                pwm_1<=pwm;
                case(state)
                        0:if(wb_stb&&wb_we)begin
                                case(wb_adr)
                                        0:if(wb_data[7])ready<=1;
                                        else if(wb_data[2])begin
                                                ready<=0;
                                                if(wb_data[1])state<=1;
                                                else state<=2;
                                        end
                                        default:ready<=1;
                                endcase
                        end
                        1:begin
                                case(state_mp)
 
                                        0:begin
                                                if(pwm&&(!pwm_1))begin
                                                        if(nperiod==15)begin
                                                                nperiod<=0;
                                                                state_mp<=1;
                                                        end
                                                        else nperiod<=nperiod+1;
                                                end
                                        end
                                        1:begin
                                                if(pwm&&pwm_1)begin
                                                        ct_DC<=ct_DC+2;
                                                        ct_period<=ct_period+2;
                                                end
                                                else if((!pwm)&&pwm_1)begin
                                                        $display("ct_DC=%d",ct_DC);
                                                        ct_DC<=0;
                                                        ct_period<=ct_period+2;
                                                end
                                                else if(pwm&&(!pwm_1))begin
                                                        ct_period<=0;
                                                        $display("ct_period=%d",ct_period);
                                                        state_mp<=0;
                                                        state<=0;
                                                        ready<=1;
                                                end
                                                else ct_period<=ct_period+2;
                                        end
                                endcase
                        end
                        2:begin
                                if(!pwm)ct_period<=ct_period+2;
                                else if(pwm&&(!pwm_1))begin
                                        ct_period<=0;
                                        $display("ct_period=%d",ct_period);
                                        state<=0;
                                        ready<=1;
                                end
                        end
                endcase
        end
////////////////////////////////////////////
 
////////////////scoreboard/////////////////////
reg     [15:0]ctrl_sb=0;
reg     [15:0]divisor_sb=0;
reg     [15:0]period_sb=0;
reg     [15:0]DC_sb=0;
wire    [15:0]DC;
assign  DC=wb_data[6]?extDC:DC_sb;
wire    [15:0]divisor_sb_1;
assign  divisor_sb_1=(divisor_sb==0)?1:divisor_sb;
always@(posedge wb_clk)
        if(!rst)begin
                if(wb_stb&&wb_we)begin
                        case(wb_adr)
                                0:begin
                                ctrl_sb<=wb_data;
                                if(wb_data[2])begin
                                        if(wb_data[1])begin
                                                if(wb_data[0])begin
                                                        $display("PWM starts    scoreboard:     period=2*divisor_sb*period_sb=2*%d*%d=%d",divisor_sb_1,period_sb,2*divisor_sb_1*period_sb);
                                                        $display("PWM starts    scoreboard:     DC=2*divisor_sb*DC_sb=2*%d*%d=%d",divisor_sb_1,DC,2*divisor_sb_1*DC);
                                                end
                                                else begin
                                                        $display("PWM starts    scoreboard:     period=20*divisor_sb*period_sb=20*%d*%d=%d",divisor_sb_1,period_sb,20*divisor_sb_1*period_sb);
                                                        $display("PWM starts    scoreboard:     DC=20*divisor_sb*DC_sb=20*%d*%d=%d",divisor_sb_1,DC,20*divisor_sb_1*DC);
                                                end
                                        end
                                        else begin
                                                if(wb_data[3])$write("timer starts      continuous run");
                                                else $write("timer starts       single run");
                                                if(wb_data[0])begin
                                                        $write("        scoreboard:     period=2*divisor_sb*period_sb=2*%d*%d=%d\n",divisor_sb_1,period_sb,2*divisor_sb_1*period_sb);
                                                end
                                                else begin
                                                        $write("        scoreboard:     period=20*divisor_sb*period_sb=20*%d*%d=%d\n",divisor_sb_1,period_sb,20*divisor_sb_1*period_sb);
                                                end
 
                                        end
                                end
                                end
                                2:divisor_sb<=wb_data;
                                4:period_sb<=wb_data;
                                6:DC_sb<=wb_data;
                        endcase
                end
        end
/////////////////////////////////////////////////
 
 
//test process///////////////
initial begin
        while(1)begin
                #1;
                if(ready&&(!rst))driver;
        end
end
/////////////////////////////
 
wire    [15:0]wb_o_data;
 
PWM     PWM_0(
wb_clk,
rst,
wb_cyc,
wb_stb,
wb_we,
wb_adr,
wb_data,
wb_o_data,
wb_ack,
extclk,
extDC,
1'b1,
pwm
);
 
 
 
 
 
 
endmodule

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[/] [pwm/] [trunk/] [testbench/] [PWM_tb.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	m99	`//Author: Zhuxu`
2			`//Email: m99a1@yahoo.cn`
3			`module PWM_tb();`
4			`reg wb_clk=0,extclk=0;`
5			`reg rst=1;`
6
7			`initial #20 rst=0;`
8
9			`always #10 wb_clk=~wb_clk;`
10
11			`always #1 extclk=~extclk;`
12
13			`///////test cases configuration data///////////`
14			`wire [31:0]configdata[0:20];`
15			`//PWM test 0`
16
17			`assign configdata[0]=32'h40303;`
18			`assign configdata[1]=32'h600ed;`
19			`assign configdata[2]=31'h17;`
20			`//continous timer test 0`
21			`assign configdata[3]=32'h80;`
22			`assign configdata[4]=32'h20005;`
23			`assign configdata[5]=32'h401a1;`
24			`assign configdata[6]=32'h1c;`
25			`//continous timer test 1`
26			`assign configdata[7]=32'h1c;`
27			`//PWM test 1`
28			`assign configdata[8]=32'h41d00;`
29			`assign configdata[9]=32'h61000;`
30			`assign configdata[10]=32'h56;`
31			`//discontinous timer test 0`
32
33			`assign configdata[11]=32'h80;`
34			`assign configdata[12]=32'h20008;`
35			`assign configdata[13]=32'h400aa;`
36			`assign configdata[14]=32'h15;`
37			`//discontinous timer test 1`
38			`assign configdata[15]=32'h15;`
39			`//continous timer test 2`
40			`assign configdata[16]=32'h80;`
41			`assign configdata[17]=32'h20005;`
42			`assign configdata[18]=32'h401a1;`
43			`assign configdata[19]=32'h15;`
44			`//continous timer test 3`
45			`assign configdata[20]=32'h15;`
46
47
48
49			`////////////////////////////////////////////////`
50
51
52			`/////driver///////////////////////////////////`
53			`reg [15:0]wb_data=0;`
54			`reg [15:0]wb_adr=0;`
55			`reg wb_cyc=0,wb_stb=0,wb_we=0;`
56			`wire wb_ack;`
57			`wire [15:0]extDC;`
58			`assign extDC=60;`
59			`reg [4:0]nconfig=0;`
60
61			`task driver;`
62			`begin`
63			`@(posedge wb_clk);`
64			`wb_cyc<=1;`
65			`wb_stb<=1;`
66			`wb_we<=1;`
67			`wb_adr<=configdata[nconfig][31:16];`
68			`wb_data<=configdata[nconfig][15:0];`
69			`nconfig<=nconfig+1;`
70			`while(!wb_ack)begin`
71			`@(posedge wb_clk);`
72			`end`
73			`wb_cyc<=0;`
74			`wb_stb<=0;`
75			`wb_we<=0;`
76			`end`
77			`endtask`
78			`//////////////////////////////////////////////`
79
80			`//////////////monitor/////////////////////`
81			`wire pwm;`
82			`reg [63:0]ct_period=0;`
83			`reg [63:0]ct_DC=0;`
84			`reg ready=1;`
85			`reg [3:0]state=0;`
86			`reg [1:0]state_mp=0;`
87			`reg [1:0]state_mt=0;`
88			`reg [3:0]nperiod=0;`
89			`reg pwm_1=0;`
90			`always@(posedge extclk)`
91			`if(!rst)begin`
92			`pwm_1<=pwm;`
93			`case(state)`
94			`0:if(wb_stb&&wb_we)begin`
95			`case(wb_adr)`
96			`0:if(wb_data[7])ready<=1;`
97			`else if(wb_data[2])begin`
98			`ready<=0;`
99			`if(wb_data[1])state<=1;`
100			`else state<=2;`
101			`end`
102			`default:ready<=1;`
103			`endcase`
104			`end`
105			`1:begin`
106			`case(state_mp)`
107
108			`0:begin`
109			`if(pwm&&(!pwm_1))begin`
110			`if(nperiod==15)begin`
111			`nperiod<=0;`
112			`state_mp<=1;`
113			`end`
114			`else nperiod<=nperiod+1;`
115			`end`
116			`end`
117			`1:begin`
118			`if(pwm&&pwm_1)begin`
119			`ct_DC<=ct_DC+2;`
120			`ct_period<=ct_period+2;`
121			`end`
122			`else if((!pwm)&&pwm_1)begin`
123			`$display("ct_DC=%d",ct_DC);`
124			`ct_DC<=0;`
125			`ct_period<=ct_period+2;`
126			`end`
127			`else if(pwm&&(!pwm_1))begin`
128			`ct_period<=0;`
129			`$display("ct_period=%d",ct_period);`
130			`state_mp<=0;`
131			`state<=0;`
132			`ready<=1;`
133			`end`
134			`else ct_period<=ct_period+2;`
135			`end`
136			`endcase`
137			`end`
138			`2:begin`
139			`if(!pwm)ct_period<=ct_period+2;`
140			`else if(pwm&&(!pwm_1))begin`
141			`ct_period<=0;`
142			`$display("ct_period=%d",ct_period);`
143			`state<=0;`
144			`ready<=1;`
145			`end`
146			`end`
147			`endcase`
148			`end`
149			`////////////////////////////////////////////`
150
151			`////////////////scoreboard/////////////////////`
152			`reg [15:0]ctrl_sb=0;`
153			`reg [15:0]divisor_sb=0;`
154			`reg [15:0]period_sb=0;`
155			`reg [15:0]DC_sb=0;`
156			`wire [15:0]DC;`
157			`assign DC=wb_data[6]?extDC:DC_sb;`
158			`wire [15:0]divisor_sb_1;`
159			`assign divisor_sb_1=(divisor_sb==0)?1:divisor_sb;`
160			`always@(posedge wb_clk)`
161			`if(!rst)begin`
162			`if(wb_stb&&wb_we)begin`
163			`case(wb_adr)`
164			`0:begin`
165			`ctrl_sb<=wb_data;`
166			`if(wb_data[2])begin`
167			`if(wb_data[1])begin`
168			`if(wb_data[0])begin`
169			`$display("PWM starts scoreboard: period=2divisor_sbperiod_sb=2%d%d=%d",divisor_sb_1,period_sb,2divisor_sb_1period_sb);`
170			`$display("PWM starts scoreboard: DC=2divisor_sbDC_sb=2%d%d=%d",divisor_sb_1,DC,2divisor_sb_1DC);`
171			`end`
172			`else begin`
173			`$display("PWM starts scoreboard: period=20divisor_sbperiod_sb=20%d%d=%d",divisor_sb_1,period_sb,20divisor_sb_1period_sb);`
174			`$display("PWM starts scoreboard: DC=20divisor_sbDC_sb=20%d%d=%d",divisor_sb_1,DC,20divisor_sb_1DC);`
175			`end`
176			`end`
177			`else begin`
178			`if(wb_data[3])$write("timer starts continuous run");`
179			`else $write("timer starts single run");`
180			`if(wb_data[0])begin`
181			`$write(" scoreboard: period=2divisor_sbperiod_sb=2%d%d=%d\n",divisor_sb_1,period_sb,2divisor_sb_1period_sb);`
182			`end`
183			`else begin`
184			`$write(" scoreboard: period=20divisor_sbperiod_sb=20%d%d=%d\n",divisor_sb_1,period_sb,20divisor_sb_1period_sb);`
185			`end`
186
187			`end`
188			`end`
189			`end`
190			`2:divisor_sb<=wb_data;`
191			`4:period_sb<=wb_data;`
192			`6:DC_sb<=wb_data;`
193			`endcase`
194			`end`
195			`end`
196			`/////////////////////////////////////////////////`
197
198
199			`//test process///////////////`
200			`initial begin`
201			`while(1)begin`
202			`#1;`
203			`if(ready&&(!rst))driver;`
204			`end`
205			`end`
206			`/////////////////////////////`
207
208			`wire [15:0]wb_o_data;`
209
210			`PWM PWM_0(`
211			`wb_clk,`
212			`rst,`
213			`wb_cyc,`
214			`wb_stb,`
215			`wb_we,`
216			`wb_adr,`
217			`wb_data,`
218			`wb_o_data,`
219			`wb_ack,`
220			`extclk,`
221			`extDC,`
222			`1'b1,`
223			`pwm`
224			`);`
225
226
227
228
229
230
231			`endmodule`