URL https://opencores.org/ocsvn/pwm_with_dithering/pwm_with_dithering/trunk

Subversion Repositories pwm_with_dithering

[/] [pwm_with_dithering/] [trunk/] [Implementation_results.txt] - Blame information for rev 6

Details | Compare with Previous | View Log


Timing and usage after synthesis reported for Xilinx Artix7 (XC7A100T-2csg324) with bits=16 and dithering=5. Xilinx ISE 14.7 was used, with default settings. No optimizations of any parameters or tool settings were applied. Also, all of the code is in pure VHDL, and no Xilinx specific IP blocks or hard macros have been used.
 
Summary:
                minimal ineq    reg     p_small pipelined
LUTs            36      43      35      40      49
REGs            17      17      30      31      43
MHz             259     211     382     437     483
sensitive       yes     no      no      no      no
latency         none    none    1sc     1sc+1c  1sc+2c
 
Where sensitive means that the implementation can produce incorrect output for a short duration during input value change, and latency units are sc = subcycle, c = clock cycle.
 
 
For minimal implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
 Number of Slice Registers:              17  out of  126800     0%
 Number of Slice LUTs:                   36  out of  63400     0%
    Number used as Logic:                36  out of  63400     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     36
   Number with an unused Flip Flop:      19  out of     36    52%
   Number with an unused LUT:             0  out of     36     0%
   Number of fully used LUT-FF pairs:    17  out of     36    47%
   Number of unique control sets:         1
 
IO Utilization:
 Number of IOs:                          18
 Number of bonded IOBs:                  18  out of    210     8%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
 
Timing Summary: (after synthesis)
---------------
   Minimum period: 3.854ns (Maximum Frequency: 259.491MHz)
   Minimum input arrival time before clock: 3.646ns
   Maximum output required time after clock: 0.742ns
   Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     3.387ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.287ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
 
 
For pipelined implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
 Number of Slice Registers:              43  out of  126800     0%
 Number of Slice LUTs:                   49  out of  63400     0%
    Number used as Logic:                49  out of  63400     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     50
   Number with an unused Flip Flop:       7  out of     50    14%
   Number with an unused LUT:             1  out of     50     2%
   Number of fully used LUT-FF pairs:    42  out of     50    84%
   Number of unique control sets:         2
 
IO Utilization:
 Number of IOs:                          18
 Number of bonded IOBs:                  18  out of    210     8%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
 
Timing Summary: (after synthesis)
---------------
   Minimum period: 2.069ns (Maximum Frequency: 483.255MHz)
   Minimum input arrival time before clock: 1.606ns
   Maximum output required time after clock: 0.742ns
   Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     2.027ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.209ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
 
 
For inequality based implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
 Number of Slice Registers:              17  out of  126800     0%
 Number of Slice LUTs:                   43  out of  63400     0%
    Number used as Logic:                43  out of  63400     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     44
   Number with an unused Flip Flop:      27  out of     44    61%
   Number with an unused LUT:             1  out of     44     2%
   Number of fully used LUT-FF pairs:    16  out of     44    36%
   Number of unique control sets:         2
 
IO Utilization:
 Number of IOs:                          18
 Number of bonded IOBs:                  18  out of    210     8%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
 
Timing Summary: (after synthesis)
---------------
   Minimum period: 4.737ns (Maximum Frequency: 211.113MHz)
   Minimum input arrival time before clock: 4.529ns
   Maximum output required time after clock: 0.742ns
   Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     4.390ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.287ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
 
 
For register based implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
 Number of Slice Registers:              30  out of  126800     0%
 Number of Slice LUTs:                   35  out of  63400     0%
    Number used as Logic:                35  out of  63400     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     36
   Number with an unused Flip Flop:       6  out of     36    16%
   Number with an unused LUT:             1  out of     36     2%
   Number of fully used LUT-FF pairs:    29  out of     36    80%
   Number of unique control sets:         2
 
IO Utilization:
 Number of IOs:                          18
 Number of bonded IOBs:                  18  out of    210     8%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
 
Timing Summary: (after synthesis)
   Minimum period: 2.618ns (Maximum Frequency: 381.912MHz)
   Minimum input arrival time before clock: 2.410ns
   Maximum output required time after clock: 0.742ns
   Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     2.436ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.212ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
 
 
For small pipelined implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
 Number of Slice Registers:              31  out of  126800     0%
 Number of Slice LUTs:                   40  out of  63400     0%
    Number used as Logic:                40  out of  63400     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     41
   Number with an unused Flip Flop:      10  out of     41    24%
   Number with an unused LUT:             1  out of     41     2%
   Number of fully used LUT-FF pairs:    30  out of     41    73%
   Number of unique control sets:         3
 
IO Utilization:
 Number of IOs:                          18
 Number of bonded IOBs:                  18  out of    210     8%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
 
Timing Summary: (after synthesis)
   Minimum period: 2.286ns (Maximum Frequency: 437.350MHz)
   Minimum input arrival time before clock: 1.868ns
   Maximum output required time after clock: 0.742ns
   Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     2.083ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.201ns|            |       0|           0
----------------------------------------------------------------------------------------------------------

Browse

Tools

Subversion Repositories pwm_with_dithering

[/] [pwm_with_dithering/] [trunk/] [Implementation_results.txt] - Blame information for rev 6

Line No.	Rev	Author	Line
1	5	TeroS	`Timing and usage after synthesis reported for Xilinx Artix7 (XC7A100T-2csg324) with bits=16 and dithering=5. Xilinx ISE 14.7 was used, with default settings. No optimizations of any parameters or tool settings were applied. Also, all of the code is in pure VHDL, and no Xilinx specific IP blocks or hard macros have been used.`
2
3	6	TeroS	`Summary:`
4			`minimal ineq reg p_small pipelined`
5			`LUTs 36 43 35 40 49`
6			`REGs 17 17 30 31 43`
7			`MHz 259 211 382 437 483`
8			`sensitive yes no no no no`
9			`latency none none 1sc 1sc+1c 1sc+2c`
10	5	TeroS
11	6	TeroS	`Where sensitive means that the implementation can produce incorrect output for a short duration during input value change, and latency units are sc = subcycle, c = clock cycle.`
12
13
14	5	TeroS	`For minimal implementation:`
15
16			`Device utilization summary:`
17			`---------------------------`
18
19			`Selected Device : 7a100tcsg324-2`
20
21			`Slice Logic Utilization:`
22			`Number of Slice Registers: 17 out of 126800 0%`
23			`Number of Slice LUTs: 36 out of 63400 0%`
24			`Number used as Logic: 36 out of 63400 0%`
25
26			`Slice Logic Distribution:`
27			`Number of LUT Flip Flop pairs used: 36`
28			`Number with an unused Flip Flop: 19 out of 36 52%`
29			`Number with an unused LUT: 0 out of 36 0%`
30			`Number of fully used LUT-FF pairs: 17 out of 36 47%`
31			`Number of unique control sets: 1`
32
33			`IO Utilization:`
34			`Number of IOs: 18`
35			`Number of bonded IOBs: 18 out of 210 8%`
36
37			`Specific Feature Utilization:`
38			`Number of BUFG/BUFGCTRLs: 1 out of 32 3%`
39
40			`Timing Summary: (after synthesis)`
41			`---------------`
42			`Minimum period: 3.854ns (Maximum Frequency: 259.491MHz)`
43			`Minimum input arrival time before clock: 3.646ns`
44			`Maximum output required time after clock: 0.742ns`
45			`Maximum combinational path delay: No path found`
46
47			`After place and route:`
48			`----------------------------------------------------------------------------------------------------------`
49			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
50			`\| \| Slack \| Achievable \| Errors \| Score`
51			`----------------------------------------------------------------------------------------------------------`
52			`Autotimespec constraint for clock net clk \| SETUP \| N/A\| 3.387ns\| N/A\| 0`
53			`_BUFGP \| HOLD \| 0.287ns\| \| 0\| 0`
54			`----------------------------------------------------------------------------------------------------------`
55
56
57			`For pipelined implementation:`
58
59			`Device utilization summary:`
60			`---------------------------`
61
62			`Selected Device : 7a100tcsg324-2`
63
64			`Slice Logic Utilization:`
65			`Number of Slice Registers: 43 out of 126800 0%`
66			`Number of Slice LUTs: 49 out of 63400 0%`
67			`Number used as Logic: 49 out of 63400 0%`
68
69			`Slice Logic Distribution:`
70			`Number of LUT Flip Flop pairs used: 50`
71			`Number with an unused Flip Flop: 7 out of 50 14%`
72			`Number with an unused LUT: 1 out of 50 2%`
73			`Number of fully used LUT-FF pairs: 42 out of 50 84%`
74			`Number of unique control sets: 2`
75
76			`IO Utilization:`
77			`Number of IOs: 18`
78			`Number of bonded IOBs: 18 out of 210 8%`
79
80			`Specific Feature Utilization:`
81			`Number of BUFG/BUFGCTRLs: 1 out of 32 3%`
82
83			`Timing Summary: (after synthesis)`
84			`---------------`
85			`Minimum period: 2.069ns (Maximum Frequency: 483.255MHz)`
86			`Minimum input arrival time before clock: 1.606ns`
87			`Maximum output required time after clock: 0.742ns`
88			`Maximum combinational path delay: No path found`
89
90			`After place and route:`
91			`----------------------------------------------------------------------------------------------------------`
92			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
93			`\| \| Slack \| Achievable \| Errors \| Score`
94			`----------------------------------------------------------------------------------------------------------`
95			`Autotimespec constraint for clock net clk \| SETUP \| N/A\| 2.027ns\| N/A\| 0`
96			`_BUFGP \| HOLD \| 0.209ns\| \| 0\| 0`
97			`----------------------------------------------------------------------------------------------------------`
98
99
100			`For inequality based implementation:`
101
102			`Device utilization summary:`
103			`---------------------------`
104
105			`Selected Device : 7a100tcsg324-2`
106
107			`Slice Logic Utilization:`
108			`Number of Slice Registers: 17 out of 126800 0%`
109			`Number of Slice LUTs: 43 out of 63400 0%`
110			`Number used as Logic: 43 out of 63400 0%`
111
112			`Slice Logic Distribution:`
113			`Number of LUT Flip Flop pairs used: 44`
114			`Number with an unused Flip Flop: 27 out of 44 61%`
115			`Number with an unused LUT: 1 out of 44 2%`
116			`Number of fully used LUT-FF pairs: 16 out of 44 36%`
117			`Number of unique control sets: 2`
118
119			`IO Utilization:`
120			`Number of IOs: 18`
121			`Number of bonded IOBs: 18 out of 210 8%`
122
123			`Specific Feature Utilization:`
124			`Number of BUFG/BUFGCTRLs: 1 out of 32 3%`
125
126			`Timing Summary: (after synthesis)`
127			`---------------`
128			`Minimum period: 4.737ns (Maximum Frequency: 211.113MHz)`
129			`Minimum input arrival time before clock: 4.529ns`
130			`Maximum output required time after clock: 0.742ns`
131			`Maximum combinational path delay: No path found`
132
133			`After place and route:`
134			`----------------------------------------------------------------------------------------------------------`
135			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
136			`\| \| Slack \| Achievable \| Errors \| Score`
137			`----------------------------------------------------------------------------------------------------------`
138			`Autotimespec constraint for clock net clk \| SETUP \| N/A\| 4.390ns\| N/A\| 0`
139			`_BUFGP \| HOLD \| 0.287ns\| \| 0\| 0`
140			`----------------------------------------------------------------------------------------------------------`
141
142
143			`For register based implementation:`
144
145			`Device utilization summary:`
146			`---------------------------`
147
148			`Selected Device : 7a100tcsg324-2`
149
150			`Slice Logic Utilization:`
151			`Number of Slice Registers: 30 out of 126800 0%`
152			`Number of Slice LUTs: 35 out of 63400 0%`
153			`Number used as Logic: 35 out of 63400 0%`
154
155			`Slice Logic Distribution:`
156			`Number of LUT Flip Flop pairs used: 36`
157			`Number with an unused Flip Flop: 6 out of 36 16%`
158			`Number with an unused LUT: 1 out of 36 2%`
159			`Number of fully used LUT-FF pairs: 29 out of 36 80%`
160			`Number of unique control sets: 2`
161
162			`IO Utilization:`
163			`Number of IOs: 18`
164			`Number of bonded IOBs: 18 out of 210 8%`
165
166			`Specific Feature Utilization:`
167			`Number of BUFG/BUFGCTRLs: 1 out of 32 3%`
168
169			`Timing Summary: (after synthesis)`
170			`Minimum period: 2.618ns (Maximum Frequency: 381.912MHz)`
171			`Minimum input arrival time before clock: 2.410ns`
172			`Maximum output required time after clock: 0.742ns`
173			`Maximum combinational path delay: No path found`
174
175			`After place and route:`
176			`----------------------------------------------------------------------------------------------------------`
177			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
178			`\| \| Slack \| Achievable \| Errors \| Score`
179			`----------------------------------------------------------------------------------------------------------`
180			`Autotimespec constraint for clock net clk \| SETUP \| N/A\| 2.436ns\| N/A\| 0`
181			`_BUFGP \| HOLD \| 0.212ns\| \| 0\| 0`
182			`----------------------------------------------------------------------------------------------------------`
183
184
185			`For small pipelined implementation:`
186
187			`Device utilization summary:`
188			`---------------------------`
189
190			`Selected Device : 7a100tcsg324-2`
191
192			`Slice Logic Utilization:`
193			`Number of Slice Registers: 31 out of 126800 0%`
194			`Number of Slice LUTs: 40 out of 63400 0%`
195			`Number used as Logic: 40 out of 63400 0%`
196
197			`Slice Logic Distribution:`
198			`Number of LUT Flip Flop pairs used: 41`
199			`Number with an unused Flip Flop: 10 out of 41 24%`
200			`Number with an unused LUT: 1 out of 41 2%`
201			`Number of fully used LUT-FF pairs: 30 out of 41 73%`
202			`Number of unique control sets: 3`
203
204			`IO Utilization:`
205			`Number of IOs: 18`
206			`Number of bonded IOBs: 18 out of 210 8%`
207
208			`Specific Feature Utilization:`
209			`Number of BUFG/BUFGCTRLs: 1 out of 32 3%`
210
211			`Timing Summary: (after synthesis)`
212			`Minimum period: 2.286ns (Maximum Frequency: 437.350MHz)`
213			`Minimum input arrival time before clock: 1.868ns`
214			`Maximum output required time after clock: 0.742ns`
215			`Maximum combinational path delay: No path found`
216
217			`After place and route:`
218			`----------------------------------------------------------------------------------------------------------`
219			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
220			`\| \| Slack \| Achievable \| Errors \| Score`
221			`----------------------------------------------------------------------------------------------------------`
222			`Autotimespec constraint for clock net clk \| SETUP \| N/A\| 2.083ns\| N/A\| 0`
223			`_BUFGP \| HOLD \| 0.201ns\| \| 0\| 0`
224			`----------------------------------------------------------------------------------------------------------`