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[/] [pwm_with_dithering/] [trunk/] [testbench/] [test_top.vhd] - Blame information for rev 2

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1 2 TeroS 
--------------------------------------------------------------------------------
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-- Company:             Aboa Space Research Oy (ASRO)
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-- Engineer:            Tero Säntti
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--
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-- Create Date:   14:58:12 01/27/2021
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-- Design Name:   PWM test top
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-- Project Name:  PWM
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-- Target Device: None / Simulation ONLY
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-- Tool versions: None / non-specific
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-- Description:   Very generic testbench for pwm
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY test_top IS
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        generic(
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                bits            :integer:=16;
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                vdd             :real:=3.3;
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                dithering:integer:=5
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        );
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END test_top;
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ARCHITECTURE behavior OF test_top IS
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COMPONENT pwm
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    Generic (
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                                bits: integer:=16;
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                                dithering:integer:=5
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                                );
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    PORT(
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         clk : IN  std_logic;
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         set : IN  std_logic_vector(bits-1 downto 0);
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         o : OUT  std_logic
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        );
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END COMPONENT;
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COMPONENT pwm_pipelined
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    Generic (
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                                bits: integer:=16;
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                                dithering:integer:=5
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                                );
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    PORT(
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         clk : IN  std_logic;
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         set : IN  std_logic_vector(bits-1 downto 0);
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         o : OUT  std_logic
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        );
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END COMPONENT;
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COMPONENT pwm_pipelined_small
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    Generic (
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                                bits: integer:=16;
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                                dithering:integer:=5
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                                );
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    PORT(
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         clk : IN  std_logic;
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         set : IN  std_logic_vector(bits-1 downto 0);
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         o : OUT  std_logic
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        );
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END COMPONENT;
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COMPONENT pwm_ineq
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    Generic (
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                                bits: integer:=16;
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                                dithering:integer:=5
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                                );
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    PORT(
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         clk : IN  std_logic;
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         set : IN  std_logic_vector(bits-1 downto 0);
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         o : OUT  std_logic
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        );
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END COMPONENT;
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COMPONENT pwm_reg
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    Generic (
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                                bits: integer:=16;
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                                dithering:integer:=5
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                                );
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    PORT(
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         clk : IN  std_logic;
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         set : IN  std_logic_vector(bits-1 downto 0);
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         o : OUT  std_logic
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        );
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END COMPONENT;
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component pwm_to_voltage is
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    Generic (
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                                autorefresh_interval : time;
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                                autorefresh_enabled : boolean;
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                                supply_voltage : real:=3.3;
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                                R : real:=100.0;
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                                C : real:=0.0001
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                                );
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    Port ( pwm : in  STD_LOGIC;
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           voltage : out real;
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                          frequency : out real
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                          );
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end component;
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component rc_filter is
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    Generic (
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                                autorefresh_interval : time;
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                                autorefresh_enabled : boolean;
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                                supply_voltage : real:=3.3;
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                                R : real:=100.0;
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                                C : real:=0.0001
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                                );
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    Port ( v_in : in  real;
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           v_out : out real
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                          );
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end component;
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component pseudo_ADC is
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    Generic (
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                                bits : integer :=bits;
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                                supply_voltage : real:=3.3
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                                );
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    Port ( v_in : in  real;
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                          digital_out : out std_logic_vector(bits-1 downto 0)
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                          );
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end component;
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component analyzer is
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    Generic (
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                                supply_voltage : real:=3.3;
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                                filter_strength: real:=0.99
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                                );
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    Port ( enable : in std_logic;
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                          v_in : in  real;
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           v_out : buffer real;
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                          v_max : buffer real;
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                          v_min : buffer real;
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                          v_p2p : out real
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                          );
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end component;
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   --Inputs
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   signal clk : std_logic := '0';
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   signal set : std_logic_vector(bits-1 downto 0) := (others => '0');
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        --Outputs
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   signal o : std_logic;
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        signal volts:real;
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        signal frequency:real;
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        signal filtered_volts:real;
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   signal read_back : std_logic_vector(bits-1 downto 0);
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        signal analyzed_volts: real;
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        signal analyzed_min: real;
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        signal analyzed_max: real;
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        signal analyzed_p2p: real;
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        signal analyzer_enable: std_logic;
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   -- Clock period definitions
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   constant clk_period : time := 8.3333333 ns; -- AKA 120MHz
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BEGIN
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        -- Instantiate the Unit Under Test (UUT)
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   uut: pwm_pipelined_small
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    Generic map(
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                                bits             => bits,
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                                dithering => dithering
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                                )
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         PORT MAP (
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          clk => clk,
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          set => set,
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          o => o
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        );
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   -- Clock process definitions
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   clk_process :process
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   begin
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                clk <= '0';
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                wait for clk_period/2;
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                clk <= '1';
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                wait for clk_period/2;
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   end process;
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   -- Stimulus process (Set your test patterns here, or make a more automated test structure as needed)
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        -- This is set for running 100ms.
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   stim_proc: process
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   begin
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                analyzer_enable <= '0';
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      set <= "1000000000010000";
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                wait for 30 ms;
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                analyzer_enable <= '1';
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                wait for 20 ms;
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                analyzer_enable <= '0';
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      set <= "0010111001000101";
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                wait for 30 ms;
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                analyzer_enable <= '1';
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      wait;
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   end process;
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voltage_generator: pwm_to_voltage
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    Generic map(
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                                autorefresh_interval => 0.1 us,--: time;
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                                autorefresh_enabled  => true,--: boolean;
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                                supply_voltage          => vdd,--: real:=3.3;
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                                R                                                       => 100000.0,-- 100k
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                                C                                                       => 0.000000018 -- 18n
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                                )
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    Port map(
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                                pwm              => o,--: in  STD_LOGIC;
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                                voltage          => volts,--: out real;
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                           frequency => frequency--: out real
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                                );
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Secondary_RC_filter: rc_filter
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    Generic map(
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                                autorefresh_interval => 1 us,--: time;
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                                autorefresh_enabled  => false,--: boolean; -- IF previous stages are set to update often, then this can be false
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                                supply_voltage          => vdd,--: real:=3.3;
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                                R                                                       => 100.0,--: real:=100.0; 0.1k
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                                C                                                       => 0.000000200 -- 200n
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                                )
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    Port map(
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                                v_in                    => volts,--: in  real;
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            v_out                       => filtered_volts--: out real;
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                           );
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Output_analyzer: analyzer
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    Generic map(
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                                supply_voltage  => vdd,--: real:=3.3;
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                                filter_strength => 0.999--: real:=0.99
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                                )
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    Port map(
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                                enable => analyzer_enable,--: in std_logic;
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                           v_in          => filtered_volts,--: in  real;
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            v_out  => analyzed_volts,--: buffer real;
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                           v_max  => analyzed_max,--: buffer real;
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                           v_min  => analyzed_min,--: buffer real;
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                           v_p2p  => analyzed_p2p--: out real
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                          );
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read_back_ADC:pseudo_ADC
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    Generic map(
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                                bits                            => bits,--: integer :=16;
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                                supply_voltage => vdd--: real:=3.3
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                                )
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    Port map(
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                                v_in => analyzed_volts,--: in  real;
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                           digital_out => read_back--: out std_logic_vector(bits-1 downto 0)
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                          );
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END;

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