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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module tb_top();
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// --------------------------------------------------------------------
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// test bench clock & reset
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wire clk_200mhz;
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wire tb_clk = clk_200mhz;
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wire tb_rst;
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wire aclk = tb_clk;
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wire aresetn = ~tb_rst;
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tb_base #( .PERIOD(5_000) ) tb( clk_200mhz, tb_rst );
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// --------------------------------------------------------------------
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//
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import avf_1_tile_4_outputs_class_pkg::*;
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avf_1_tile_4_outputs_class a_h;
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axis_if #(.N(AVF_N), .U(AVF_U)) avf_axis[TILES](.*);
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initial
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a_h = new(.avf_axis_in_if(avf_axis), .avf_axis_out_if(avf_axis));
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// --------------------------------------------------------------------
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// sim models
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// | | | | | | | | | | | | | | | | |
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// \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
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// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
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// --------------------------------------------------------------------
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//
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// ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
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// /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
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// | | | | | | | | | | | | | | | | |
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// sim models
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// test
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the_test test( tb_clk, tb_rst );
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initial
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begin
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test.run_the_test();
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$display("^^^---------------------------------");
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$display("^^^ %16.t | Testbench done.", $time);
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$display("^^^---------------------------------");
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$display("^^^---------------------------------");
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$stop();
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end
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endmodule
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