OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [PCIe/] [sim/] [tests/] [tb_riffa_register_file/] [tb_top.sv] - Blame information for rev 50

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 50 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
module tb_top;
29
  import uvm_pkg::*;
30
  import tb_top_pkg::*;
31
  import riffa_pkg::*;
32
  `include "uvm_macros.svh"
33
 
34
  // --------------------------------------------------------------------
35
  wire clk_100mhz;
36
  wire tb_clk = clk_100mhz;
37
  wire tb_rst;
38
  wire clk_1000mhz;
39
 
40
  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
41
 
42
  // --------------------------------------------------------------------
43
  wire clk = clk_100mhz;
44
  wire reset;
45
 
46
  sync_reset sync_reset_i(tb_clk, tb_rst, reset);
47
 
48
  // --------------------------------------------------------------------
49
  riffa_chnl_if #(N) chnl_bus(.*);
50
  riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
51
 
52
  riffa_register_file #(.N(N), .B(B))
53
    dut(.*);
54
 
55
  // --------------------------------------------------------------------
56
  for(genvar j = 0; j < r_if.RC; j++)
57
    assign r_if.register_in[j] = r_if.register_out[j];
58
 
59
  // --------------------------------------------------------------------
60
  riffa_config #(N) cfg_h = new(chnl_bus);
61
 
62
  initial
63
  begin
64
    uvm_config_db #(riffa_config #(N))::set(null, "*", "riffa_config", cfg_h);
65
    run_test("t_debug");
66
  end
67
 
68
// --------------------------------------------------------------------
69
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.