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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [PCIe_debug.sv] - Blame information for rev 33

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1 33 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  PCIe_debug
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  (
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    PCIe_debug_if dbg_bus,
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    input [31:0] h0,
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    input [31:0] h1,
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    input [31:0] h2,
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    input [31:0] h3,
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    input enable,
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    input reset,
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    input clk
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  );
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  // --------------------------------------------------------------------
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  //
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  always_ff @(posedge clk)
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  begin
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    dbg_bus.h0_r      <= h0;
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    dbg_bus.h1_r      <= h1;
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    dbg_bus.h2_r      <= h2;
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    dbg_bus.h3_r      <= h3;
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    dbg_bus.enable_r  <= enable;
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  end
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  // --------------------------------------------------------------------
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  //
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  always_ff @(posedge clk)
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    if(dbg_bus.enable_r)
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    begin
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      dbg_bus.tlp_fmt     <= dbg_bus.h0_r[31:29];
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      dbg_bus.tlp_type    <= dbg_bus.h0_r[28:24];
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      dbg_bus.tlp_tc      <= dbg_bus.h0_r[22:20];
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      dbg_bus.tlp_th      <= dbg_bus.h0_r[16];
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      dbg_bus.tlp_td      <= dbg_bus.h0_r[15];
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      dbg_bus.tlp_ep      <= dbg_bus.h0_r[14];
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      dbg_bus.tlp_attr    <= {dbg_bus.h0_r[18], dbg_bus.h0_r[13:12]};
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      dbg_bus.tlp_at      <= dbg_bus.h0_r[11:10];
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      dbg_bus.tlp_length  <= dbg_bus.h0_r[9:0];
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    end
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  // --------------------------------------------------------------------
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  //
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  assign dbg_bus.tlp_is_3dw   = ~dbg_bus.h0_r[29];
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  assign dbg_bus.tlp_is_4dw   = dbg_bus.h0_r[29];
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  assign dbg_bus.tlp_address  = dbg_bus.tlp_is_4dw
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                              ? {dbg_bus.h2_r,  dbg_bus.h3_r}
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                              : {32'h0,         dbg_bus.h2_r};
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// --------------------------------------------------------------------
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//
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endmodule
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