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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_if.sv] - Blame information for rev 32

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1 32 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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interface
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  riffa_chnl_if #(N); // data bus width in bytes
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        wire              rx_clk;
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        wire              rx_reset;
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        wire              rx;
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        wire              rx_ack;
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        wire              rx_last;
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        wire  [31:0]      rx_len;
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        wire  [30:0]      rx_off;
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        wire  [(8*N)-1:0] rx_data;
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        wire              rx_data_valid;
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        wire              rx_data_ren;
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        wire              tx_clk;
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        wire              tx_reset;
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        wire              tx;
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        wire              tx_ack;
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        wire              tx_last;
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        wire  [31:0]      tx_len;
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        wire  [30:0]      tx_off;
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        wire  [(8*N)-1:0] tx_data;
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        wire              tx_data_valid;
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        wire              tx_data_ren;
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// --------------------------------------------------------------------
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// synthesis translate_off
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// from the RIFFA channel
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  clocking cb_ep_rx @(posedge rx_clk);
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    input rx;
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    output rx_ack;
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    input rx_last;
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    input rx_len;
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    input rx_off;
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    input rx_data;
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    input rx_data_valid;
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    output rx_data_ren;
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  endclocking
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// from the RIFFA channel
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  clocking cb_ep_tx @(posedge tx_clk);
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    output tx;
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    input tx_ack;
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    output tx_last;
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    output tx_len;
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    output tx_off;
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    output tx_data;
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    output tx_data_valid;
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    input tx_data_ren;
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  endclocking
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  // from the PCIe
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  clocking cb_rp_tx @(posedge rx_clk);
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    output rx;
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    input rx_ack;
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    output rx_last;
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    output rx_len;
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    output rx_off;
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    output rx_data;
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    output rx_data_valid;
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    input rx_data_ren;
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  endclocking
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  // from the PCIe
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  clocking cb_rp_rx @(posedge tx_clk);
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    input tx;
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    output tx_ack;
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    input tx_last;
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    input tx_len;
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    input tx_off;
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    input tx_data;
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    input tx_data_valid;
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    output tx_data_ren;
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  endclocking
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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endinterface: riffa_chnl_if
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