OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_if.sv] - Blame information for rev 36

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 32 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
 
29
interface
30
  riffa_chnl_if #(N); // data bus width in bytes
31
 
32
        wire              rx_clk;
33
        wire              rx_reset;
34
        wire              rx;
35
        wire              rx_ack;
36
        wire              rx_last;
37
        wire  [31:0]      rx_len;
38
        wire  [30:0]      rx_off;
39
        wire  [(8*N)-1:0] rx_data;
40
        wire              rx_data_valid;
41
        wire              rx_data_ren;
42
 
43
        wire              tx_clk;
44
        wire              tx_reset;
45
        wire              tx;
46
        wire              tx_ack;
47
        wire              tx_last;
48
        wire  [31:0]      tx_len;
49
        wire  [30:0]      tx_off;
50
        wire  [(8*N)-1:0] tx_data;
51
        wire              tx_data_valid;
52
        wire              tx_data_ren;
53
 
54
 
55
// --------------------------------------------------------------------
56
// synthesis translate_off
57
 
58
// from the RIFFA channel
59
  clocking cb_ep_rx @(posedge rx_clk);
60
    input rx;
61
    output rx_ack;
62
    input rx_last;
63
    input rx_len;
64
    input rx_off;
65
    input rx_data;
66
    input rx_data_valid;
67
    output rx_data_ren;
68
  endclocking
69
 
70
// from the RIFFA channel
71
  clocking cb_ep_tx @(posedge tx_clk);
72
    output tx;
73
    input tx_ack;
74
    output tx_last;
75
    output tx_len;
76
    output tx_off;
77
    output tx_data;
78
    output tx_data_valid;
79
    input tx_data_ren;
80
  endclocking
81
 
82
  // from the PCIe
83
  clocking cb_rp_tx @(posedge rx_clk);
84
    output rx;
85
    input rx_ack;
86
    output rx_last;
87
    output rx_len;
88
    output rx_off;
89
    output rx_data;
90
    output rx_data_valid;
91
    input rx_data_ren;
92
  endclocking
93
 
94
  // from the PCIe
95
  clocking cb_rp_rx @(posedge tx_clk);
96
    input tx;
97
    output tx_ack;
98
    input tx_last;
99
    input tx_len;
100
    input tx_off;
101
    input tx_data;
102
    input tx_data_valid;
103
    output tx_data_ren;
104
  endclocking
105
// synthesis translate_on
106
// --------------------------------------------------------------------
107
 
108
 
109
// --------------------------------------------------------------------
110
//
111
endinterface: riffa_chnl_if
112
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.