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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module

  riffa_chn_rx

  #(

    N //  data bus width in bytes

  )

  (

    riffa_chnl_if chnl_bus,

    input rx_ready,

    output rx_done,

    output reg [30:0] rx_index,

    output reg rx_last,

    output reg [31:0] rx_len,

    output reg [30:0] rx_off,

    // output rx_data_ren, // shouldn't be here??

    output rd_empty,

    output [(8*N)-1:0] rd_data,

    input rd_en,

    input clk,

    input reset

  );

  // --------------------------------------------------------------------

  //

  riffa_chnl_rx_fsm

    riffa_chnl_rx_fsm_i

    (

      .rx(chnl_bus.rx),

      .rx_data_valid(chnl_bus.rx_data_valid),

      .rx_ack(chnl_bus.rx_ack),

      .*

    );

  // --------------------------------------------------------------------

  //

  always_ff @(posedge clk)

    if(chnl_bus.rx & chnl_bus.rx_ack)

    begin

      rx_last <= chnl_bus.rx_last;

      rx_len <= chnl_bus.rx_len;

      rx_off <= chnl_bus.rx_off;

    end

  // --------------------------------------------------------------------

  //

  wire [(8*N)-1:0] wr_data = chnl_bus.rx_data;

  wire wr_full;

  wire wr_en = chnl_bus.rx_data_ren & chnl_bus.rx_data_valid;

  tiny_sync_fifo #(.W((8*N)))

    tiny_sync_fifo_i(.*);

  // --------------------------------------------------------------------

  //

  always_ff @(posedge clk)

    if(reset | rx_done)

      rx_index <= 0;

    else if(rd_en)

      rx_index <= rx_index + (N/4); // increment by 32 bit words

  // --------------------------------------------------------------------

  //

  // assign rx_data_ren = ~wr_full; // shouldn't be here??

  assign chnl_bus.rx_data_ren = ~wr_full;

// --------------------------------------------------------------------

//

endmodule