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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_tx.sv] - Blame information for rev 39

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  riffa_chn_tx
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  #(
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    N // data bus width in bytes
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  )
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  (
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    riffa_chnl_if chnl_bus,
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    input tx_ready,
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    input tx_done,
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    output acked,
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    output reg [30:0] tx_index,
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    input tx_last,
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    input [31:0] tx_len,
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    input [30:0] tx_off,
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    input clk,
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    input reset
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  );
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  // --------------------------------------------------------------------
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  //
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  riffa_chnl_tx_fsm
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    riffa_chnl_tx_fsm_i
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    (
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      .tx(chnl_bus.tx),
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      .tx_ack(chnl_bus.tx_ack),
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      .*
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    );
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  // --------------------------------------------------------------------
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  //
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  always_ff @(posedge clk)
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    if(reset | ~chnl_bus.tx | tx_done)
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      tx_index = 0;
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    else if(chnl_bus.tx_data_valid & chnl_bus.tx_data_ren)
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      tx_index <= tx_index + (N/4); // increment by 32 bit words
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// --------------------------------------------------------------------
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//
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endmodule
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