Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

module

  riffa_chnl_tx_fsm

  (

    input   tx_ready,

    output  tx,

    input   tx_ack,

    input   tx_done,

    input   reset,

    input   clk

  );

  //---------------------------------------------------

  //  state machine binary definitions

  enum reg [3:0]

    {

      IDLE    = 4'b0001,

      ACK     = 4'b0010,

      TX      = 4'b0100,

      ERROR   = 4'b1000

    } state, next_state;

  //---------------------------------------------------

  //  state machine flop

  always_ff @(posedge clk)

    if(reset)

      state <= IDLE;

    else

      state <= next_state;

  //---------------------------------------------------

  //  state machine

  always_comb

    case(state)

      IDLE:     if(tx_ready)

                  next_state <= ACK;

                else

                  next_state <= IDLE;

      ACK:      if(tx_ack)

                  next_state <= TX;

                else

                  next_state <= ACK;

      TX:       if(~tx_done)

                  next_state <= TX;

                else

                  next_state <= IDLE;

      ERROR:    next_state <= IDLE;

      default:  next_state <= ERROR;

    endcase

  // --------------------------------------------------------------------

  //

  assign tx = (state == ACK) | (state == TX);

// --------------------------------------------------------------------

//

endmodule