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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_w.sv] - Blame information for rev 39

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1 32 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  riffa_chnl_w
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  #(
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    parameter C_NUM_CHNL,
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    parameter C_PCI_DATA_WIDTH,
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    parameter SIG_CHNL_LENGTH_W,
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    parameter SIG_CHNL_OFFSET_W
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  )
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  (
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    // RIFFA Interface Signals
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    output  [C_NUM_CHNL-1:0]                      CHNL_RX_CLK, // Channel read clock
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    input   [C_NUM_CHNL-1:0]                      CHNL_RX, // Channel read receive signal
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    output  [C_NUM_CHNL-1:0]                      CHNL_RX_ACK, // Channel read received signal
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    input   [C_NUM_CHNL-1:0]                      CHNL_RX_LAST, // Channel last read
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    input   [(C_NUM_CHNL*SIG_CHNL_LENGTH_W)-1:0]  CHNL_RX_LEN, // Channel read length
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    input   [(C_NUM_CHNL*SIG_CHNL_OFFSET_W)-1:0]  CHNL_RX_OFF, // Channel read offset
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    input   [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_RX_DATA, // Channel read data
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    input   [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_VALID, // Channel read data valid
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    output  [C_NUM_CHNL-1:0]                      CHNL_RX_DATA_REN, // Channel read data has been received
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    output  [C_NUM_CHNL-1:0]                      CHNL_TX_CLK, // Channel write clock
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    output  [C_NUM_CHNL-1:0]                      CHNL_TX, // Channel write receive signal
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    input   [C_NUM_CHNL-1:0]                      CHNL_TX_ACK, // Channel write acknowledgment signal
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    output  [C_NUM_CHNL-1:0]                      CHNL_TX_LAST, // Channel last write
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    output  [(C_NUM_CHNL*SIG_CHNL_LENGTH_W)-1:0]  CHNL_TX_LEN, // Channel write length (in 32 bit words)
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    output  [(C_NUM_CHNL*SIG_CHNL_OFFSET_W)-1:0]  CHNL_TX_OFF, // Channel write offset
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    output  [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]   CHNL_TX_DATA, // Channel write data
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    output  [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_VALID, // Channel write data valid
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    input   [C_NUM_CHNL-1:0]                      CHNL_TX_DATA_REN, // Channel write data has been received
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    riffa_chnl_if chnl_bus[C_NUM_CHNL]
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  );
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  // --------------------------------------------------------------------
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  //
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  genvar i;
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  generate
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    for (i = 0; i < C_NUM_CHNL; i = i + 1)
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    begin : channels
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      assign CHNL_RX_CLK[i] = chnl_bus[i].rx_clk;
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      assign chnl_bus[i].rx = CHNL_RX[i];
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      assign CHNL_RX_ACK[i] = chnl_bus[i].rx_ack;
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      assign chnl_bus[i].rx_last = CHNL_RX_LAST[i];
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      assign chnl_bus[i].rx_len = CHNL_RX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W];
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      assign chnl_bus[i].rx_off = CHNL_RX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W];
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      assign chnl_bus[i].rx_data = CHNL_RX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH];
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      assign chnl_bus[i].rx_data_valid = CHNL_RX_DATA_VALID[i];
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      assign CHNL_RX_DATA_REN[i] = chnl_bus[i].rx_data_ren;
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      assign CHNL_TX_CLK[i] = chnl_bus[i].tx_clk;
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      assign CHNL_TX[i] = chnl_bus[i].tx;
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      assign chnl_bus[i].tx_ack = CHNL_TX_ACK[i];
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      assign CHNL_TX_LAST[i] = chnl_bus[i].tx_last;
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      assign CHNL_TX_LEN[SIG_CHNL_LENGTH_W*i +:SIG_CHNL_LENGTH_W] = chnl_bus[i].tx_len;
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      assign CHNL_TX_OFF[SIG_CHNL_OFFSET_W*i +:SIG_CHNL_OFFSET_W] = chnl_bus[i].tx_off;
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      assign CHNL_TX_DATA[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH] = chnl_bus[i].tx_data;
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      assign CHNL_TX_DATA_VALID[i] = chnl_bus[i].tx_data_valid;
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      assign chnl_bus[i].tx_data_ren = CHNL_TX_DATA_REN[i];
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    end
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  endgenerate
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  // // --------------------------------------------------------------------
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  // //
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  // wire [C_NUM_CHNL-1:0]                     CHNL_RX_CLK;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_RX;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_RX_ACK;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_RX_LAST;
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  // wire [(C_NUM_CHNL*32)-1:0]                CHNL_RX_LEN;
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  // wire [(C_NUM_CHNL*31)-1:0]                CHNL_RX_OFF;
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  // wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]  CHNL_RX_DATA;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_RX_DATA_VALID;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_RX_DATA_REN;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_TX_CLK;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_TX;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_TX_ACK;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_TX_LAST;
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  // wire [(C_NUM_CHNL*32)-1:0]                CHNL_TX_LEN;
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  // wire [(C_NUM_CHNL*31)-1:0]                CHNL_TX_OFF;
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  // wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]  CHNL_TX_DATA;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_TX_DATA_VALID;
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  // wire [C_NUM_CHNL-1:0]                     CHNL_TX_DATA_REN;
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// --------------------------------------------------------------------
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//
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endmodule
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