OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_register_file.sv] - Blame information for rev 35

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 32 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
module
29
  riffa_register_file
30
  #(
31
    N, //  data bus width in bytes
32 35 qaztronic
    B // number of register banks
33 32 qaztronic
  )
34
  (
35
    riffa_chnl_if chnl_in,
36
    riffa_register_if r_if,
37
    input clk,  // must be same clock domain as rx_clk & tx_clk
38
    input reset // must be same clock domain as rx_clk & tx_clk
39
  );
40
 
41
// --------------------------------------------------------------------
42
// synthesis translate_off
43
    initial
44 35 qaztronic
    begin
45 32 qaztronic
      a_data_bus_mod: assert(N % 4 == 0) else $fatal;
46 35 qaztronic
      a_data_bus_power_of_2: assert((N != 0) & ((N & (N - 1)) == 0)) else $fatal;
47
    end
48 32 qaztronic
// synthesis translate_on
49
// --------------------------------------------------------------------
50
 
51
 
52
  // --------------------------------------------------------------------
53
  //
54
  localparam RW = (N/4); // width of the bus in 32 bit words
55 35 qaztronic
  localparam RC = RW * B; // number of available registers
56 32 qaztronic
 
57
 
58
  // --------------------------------------------------------------------
59
  //
60 35 qaztronic
  wire rx_ready = ~reset;
61 32 qaztronic
  wire rx_done;
62 35 qaztronic
  wire [30:0] rx_index;
63 32 qaztronic
  wire rx_last;
64
  wire [31:0] rx_len;
65 35 qaztronic
  wire [30:0] rx_off; // offset ignored, always start from offset 0
66
  // wire rx_data_ren;
67 32 qaztronic
  wire rd_empty;
68
  wire [(8*N)-1:0] rd_data;
69
  wire rd_en;
70
 
71
  riffa_chn_rx #(.N(N))
72 35 qaztronic
    riffa_chn_rx_i(.chnl_bus(chnl_in), .*);
73 32 qaztronic
 
74
 
75
  // --------------------------------------------------------------------
76
  //
77 35 qaztronic
  wire register_select [RC-1:0];
78
  genvar j, k;
79 32 qaztronic
 
80
  generate
81 35 qaztronic
    for(j = 0; j < B; j = j + 1)
82
    begin: register_j_gen
83
      for(k = 0; k < RW; k = k + 1)
84
      begin: register_k_gen
85
        assign register_select[(j*RW) + k] = (rx_index[30:$clog2(RW)] == j);
86 32 qaztronic
 
87 35 qaztronic
        always_ff @(posedge clk)
88
          if(reset)
89
            r_if.register_out[(j*RW) + k] <= 0;
90
          else if(rd_en & register_select[(j*RW) + k])
91
            r_if.register_out[(j*RW) + k] <= rd_data[k*32 +: 32];
92
      end
93 32 qaztronic
    end
94
  endgenerate
95
 
96
 
97
  // --------------------------------------------------------------------
98
  //
99 35 qaztronic
  // assign chnl_in.rx_data_ren = rx_data_ren;
100 32 qaztronic
  assign rd_en = ~rd_empty;
101
 
102
 
103
  // --------------------------------------------------------------------
104
  //
105
  wire tx_ready = 1;
106
  wire tx_last = 1;
107 35 qaztronic
  wire acked;
108
  wire [31:0] tx_len = RC;
109 32 qaztronic
  wire [30:0] tx_off = 0;
110 35 qaztronic
  wire [30:0] tx_index;
111 32 qaztronic
  wire tx_done = (tx_index >= chnl_in.tx_len - RW);
112
 
113
  riffa_chn_tx #(.N(N))
114
    riffa_chn_tx_i(.*);
115
 
116
 
117
  // --------------------------------------------------------------------
118
  //
119 35 qaztronic
  wire [(N*8)-1:0] data_in [(2 ** $clog2(B))-1:0];
120
 
121
  generate
122
    for(j = 0; j < B; j = j + 1)
123
    begin: data_in_j_gen
124
      for(k = 0; k < RW; k = k + 1)
125
      begin: data_in_k_gen
126
        assign data_in[j][k*32 +: 32] = r_if.register_out[(j*RW) + k];
127
      end
128
    end
129
  endgenerate
130
 
131
 
132
  // --------------------------------------------------------------------
133
  //
134
  recursive_mux #(.A($clog2(B)), .W(N*8))
135 32 qaztronic
    recursive_mux_i
136
    (
137 35 qaztronic
      .select(tx_index[$clog2(B) + $clog2(RW) - 1:$clog2(RW)]),
138
      .data_out(chnl_in.tx_data),
139
      .*
140 32 qaztronic
    );
141
 
142
 
143
  // --------------------------------------------------------------------
144
  //
145
  assign chnl_in.rx_clk = clk;
146
  assign chnl_in.tx_clk = clk;
147
  assign chnl_in.rx_reset = reset;
148
  assign chnl_in.tx_reset = reset;
149
  assign chnl_in.tx_last = 1;
150 35 qaztronic
  assign chnl_in.tx_len = RC;
151 32 qaztronic
  assign chnl_in.tx_off = 0;
152 35 qaztronic
  assign chnl_in.tx_data_valid = acked;
153 32 qaztronic
 
154
 
155
// --------------------------------------------------------------------
156
//
157
endmodule
158
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.