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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_rx_to_axis.sv] - Blame information for rev 39

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1 39 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  riffa_rx_to_axis
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  #(
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    N // RIFFA bus width in bytes
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  )
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  (
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    axis_if       axis_out,
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    riffa_chnl_if chnl_bus,
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    input         rx_ready,
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    output        rx_done,
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    output [30:0] rx_index,
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    output        rx_last,
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    output [31:0] rx_len,
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    output [30:0] rx_off,
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    input         clk,
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    input         reset
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  );
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  // --------------------------------------------------------------------
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  //
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  wire rd_empty;
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  wire [(8*N)-1:0] rd_data;
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  wire rd_en = axis_out.tvalid & axis_out.tready;
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  riffa_chn_rx #(.N(N))
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    riffa_chn_rx_i(.*);
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  // --------------------------------------------------------------------
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  //
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  assign chnl_bus.rx_clk    = clk;
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  assign chnl_bus.rx_reset  = reset;
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  assign axis_out.tvalid    = ~rd_empty;
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  assign axis_out.tdata     = rd_data;
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// --------------------------------------------------------------------
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//
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endmodule
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